JPH0290756A - Double buffer line setting device - Google Patents

Abstract

PURPOSE:To set a double buffer line with use of a single RAM by respectively writing and reading information for the former half and latter half of the respective sections of line information. CONSTITUTION:Respective pieces of line information A, B, C,..., which are inputted from an input terminal 108 and whose one cycle respectively consists of an N piece of data, are written into a RAM 101 at the former half low level, and read from the RAM 101 at the latter-half high level by a RAM write/ read control signal inputted from an input terminal 109, whose level is low for the former half of the section of the respective data and high for the latter half. In addition, by a control signal from the input terminal 109, when the RAM 101 is in a write condition, 21 selectors 102 and 103 select A side, and when it is in a read condition, they select B side. Thus, the double buffer line setting using a single RAM is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a double buffer line setting device.

[Conventional technology]

Conventionally, this type of line setting device using a double poor sofa uses two RAMs as shown in FIG. 4, and creates line setting data by alternately writing or reading them. That is, one RAM 202 is put into a writing state, and the line information input from the terminal 210 is sequentially stored in that RAM at an address set by the counter 209 that counts one cycle of the line information, and at the same time, the other RAM 203 is written. It is set in a read state, and is arbitrarily read from the address set by the output from the ROM 20B and outputted from the terminal 213 to the outside. Furthermore, when the line information has been written for one cycle, the RAM 202, which was in the write state, is set to the read state, and the line information taken in in the previous cycle is read by the ROM2O3.
M2O3 is put into a writing state, and sequential writing is performed by the counter 209. The purpose was achieved by repeating the above state for each cycle of line information.

Note that the 2-1 selectors 206 and 207 are the counters 209
This is for selecting either the outputs 00 to 1 of the ROM2O3 or the output of the ROM2O3 and outputting it to the RAM2O2, 203. In addition, the selection circuit 201 sets the Ig 210 in front of the line to R.
to either AM202 or RAM M2O3, 2
-1 selector 204 is RAM M2O2 or RAM M2
This is for selecting any of the data read from O3 and outputting it as line setting data.

These selection circuits 201, selectors 204.20
All writing and reading of RAM M2O2 and 203 is controlled by a RAM write/read control signal inputted to a terminal 211.

C invention tries to solve a! [Problem] However, the above-mentioned conventional double-poor software single line setting device has a drawback that the mounting area of the components becomes large because two independent RAM 2 O 2, 203 are used.

SUMMARY OF THE INVENTION An object of the present invention is to provide a double buffer 7 line setting device which eliminates such drawbacks and reduces the mounting area of components.

[Means to solve the problem]

The present invention includes a RAM, first and second 2-1 selectors, a ROM, an n+l bit counter that outputs an overflow, an l bit counter that has an overflow input, and a D flip-flop. An input terminal for external data is connected to a data input terminal of the RAM, an output terminal of the RAM is connected to a D input terminal of the D flip-flop, and a Q output terminal of the D flip-flop is used to output line setting data. Connect to the terminal,
An input terminal for an external RAM write/read control signal is connected to the select signal input terminal of the first and second 2-1 selectors and the RAM write/read control terminal, and a clock pulse is input from the outside. A terminal is connected to a clock input terminal of the n+1-bit counter, a clock input terminal of the 1-bit counter, and a clock input terminal of the D flip-flop, and a count output terminal from the n+1-bit counter is connected to the address input terminal of the ROM and the clock input terminal of the D flip-flop. The output terminal of the ROM is connected to the B input terminal of the second 2-1 selector, and the non-inverting output terminal of the 1-bit counter is connected to the A input terminal of the second 2-1 selector. The inverting output terminal of the l-bit counter is connected to the A input terminal of the 2-1 selector of the first
Connect to the B input terminal of the 2-1 selector of the first 2-1 selector.
-1 selector output terminal and the second 2-1 selector output terminal are connected to the address input terminal of the RAM,
The overflow output terminal of the n+1 bit counter is connected to the l
The feature is that it is connected to the overflow input terminal of the bit counter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a double buffer line setting device according to the present invention. This double-poor/7-way line setting device includes a RAM 10I, a 2-1 selector 102.103, a ROM 104, an n+1-bit N-ary counter 105 that outputs an overflow, and a 1-bit binary counter 106 that has an overflow input. , and a D flip-flop 107. Then, the input terminal 108 for inputting data from the outside is connected to the data input terminal of RAMl0I, the output terminal of RAMl0I is connected to the D input terminal of the D flip-flop 107, and the Q output terminal of the D flip-flop 107 is connected to the data output terminal. 111, and connect the input terminal 109 of the external RAM write/read control signal to the select signal input terminal of the 2-1 selector 102 and 103 and the write/read control terminal of the RAM MIOI, and The input terminal 110 of the n+1 bit N-ary counter 105 is connected to the clock input terminal of the 1-bit counter 106 and the clock input terminal of the D flip-flop 107, and the count output terminal of the n+1 bit N-ary counter 105 is connected to the clock input terminal of the n+1 bit N-ary counter 105, and the clock input terminal of the D flip-flop 107. Connect the address input terminal and the input terminal of the 2-1 selector 103, connect the output terminal of the ROM 104 to the B input terminal of the 2-1 selector 103,
Connect the non-reverse output terminal (Qo) of the 1-bit counter 106 to the input terminal of the 2-1 selector 102, and connect the inverted output terminal (do) of the 1-bit counter 106 to the B input terminal of the 2-1 selector 102. 2-1 selector 10
The Y output of the 2-1 selector 103 is used as the highest address input of the RAM 101, and the Y output of the 2-1 selector 103 is used as the remaining address input of the RAM 10I.
The overflow output terminal of the 1-biwato counter 106 is connected to the overflow input terminal of the 1-biwato counter 106.

Next, the operation of this embodiment will be explained in Figs. 1, 2, and 3.
This will be explained using figures. Input from input terminal 108, N
Line information A, B, C, . . . where one period consists of data of
is a RAM input from the input terminal 109 which becomes low level in the first half of each data division and high level in the second half.
According to the write/read control signal, it is written to RAM10I at low level in the first half, and written to RAM10I at high level in the second half.
Read from Ml0I. In addition, this input terminal 109
The 2-1 selectors 102 and 103 select the A side when the RAM 10I is in the write state, and select the B side when the RAM 10I is in the read state. Now, if the non-inverted output Q0 of the 1-bit counter 106 is at low level, the line information is the non-inverted output Q0 of the 1-bit counter 106.
is sequentially written from the lower address of the RAM by the counter output and the inverted output d of the l-bit counter.
0 and the output from the ROM 104, the data is arbitrarily read from the upper address of RAMl0I and output. The usage state of the memory at this time is shown in FIG. 2(a). Next, when one cycle of line information ends, the n+1 bit N-ary counter 1
The Q0 output of the 1-bit counter 106 is inverted by the overflow output of 05 and the clock pulse from the terminal 110.

Therefore, one cycle until the next digit error occurs is reversely R.
The data is sequentially written to the upper addresses of AMl0I and read out by the ROM 104 from the lower addresses. The usage state of the memory at this time is shown in FIG. 2(b).

The above series of operations will be explained using the time chart shown in FIG. In FIG. 3, (a) is the clock pulse input to the terminal 110, (b) is the input data from the input terminal 10B, (C) is the write/read control signal input to the terminal 109, and (d) is the clock pulse input to the terminal 110. Q output of the n+l bit N-ary counter 106, (e) is the output of the 2-1 selector 103, (f) is the non-inverted output Q of the 1-bit binary counter 106, and (g) is the output of the 2-1 selector 102. , (h)
is the address input of RAMl0I. As shown in FIG. 3, when the read/write control signal (C) is at low level, the value (d) of the counter 106 is output as the output (e) of the 2-1 selector 103, and the value (d) of the counter 106 is output as the output (e) of the 2-1 selector 103. As the output (g) of 102, the Qo value (f) of the binary counter is output. Furthermore, when the RAM write/read control signal (C) is at high level, the 2-1 selector 10
The value of ROM104 is output as the output (6) of 2.
The inverted value of Qo of the binary counter 106 is output as the output (g) of the -1 selector 102, and when one cycle of line information ends, the Q0 output of the binary counter 106 is inverted.

Through the above operations, it becomes possible to set up a double poor sofa line using one RAM.

〔Effect of the invention〕

As explained above, the double-poor 7-line setting device of the present invention has a configuration in which writing and reading are performed in the first half and the second half of each division of line information, so that double-poor 7-line setting can be performed using one RAM. . Therefore, compared to the conventional double amplifier line setting device using two RAMs, the mounting area of components can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the double buffer line setting device according to the present invention, and FIGS. 2(a) and 2(b) are memory maps of the RAM constituting the line setting device of FIG. figure(
a) shows a state where the lower address is writing and an upper address is reading; FIG. 2(b) shows a state where the lower address is reading and the upper address is writing; FIG. 3 is a time chart to show the operation; FIG. 4 is a circuit diagram showing a conventional double buffer line setting device using two RAMs. 101...RAM 102, 103...2-1 selector 104...ROM 105...n+l bit N-ary counter 106
...・l-bit binary counter 107・
・ ・ ・ ・D flip-flop 108 ・・・・
-Data input terminal 109...RAM write/read control signal input terminal 110...Clock pulse input terminal 111
...Data output terminal 201 ...Selection circuit 202, 203...RAM 204, 206.207 ...2-1 selector 20
9...n+l bit counter 210...
...Data input terminal 211 ...RAM write/read control signal input terminal 213 ...Data output terminal

Claims (1)

[Claims] (1) Consists of RAM, first and second 2-1 selectors, ROM, n+1-bit counter that outputs overflow, 1-bit counter with overflow input, and D flip-flop, and external A data input terminal from the RAM is connected to a data input terminal of the RAM, an output terminal of the RAM is connected to a D input terminal of the D flip-flop, and a Q output terminal of the D flip-flop is connected to a line setting data output terminal. connect to
An input terminal for an external RAM write/read control signal is connected to the select signal input terminal of the first and second 2-1 selectors and the RAM write/read control terminal, and a clock pulse is input from the outside. A terminal is connected to a clock input terminal of the n+1-bit counter, a clock input terminal of the 1-bit counter, and a clock input terminal of the D flip-flop, and a count output terminal from the n+1-bit counter is connected to the address input terminal of the ROM and the clock input terminal of the D flip-flop. The output terminal of the ROM is connected to the B input terminal of the second 2-1 selector, and the non-inverting output terminal of the 1-bit counter is connected to the A input terminal of the second 2-1 selector. The inverting output terminal of the 1-bit counter is connected to the A input terminal of the 2-1 selector of the first
Connect to the B input terminal of the 2-1 selector of the first 2-1 selector.
-1 selector output terminal and the second 2-1 selector output terminal are connected to the address input terminal of the RAM,
The overflow output terminal of the n+1 bit counter is connected to the 1
A double buffer line setting device characterized by being connected to an overflow input terminal of a bit counter.