JP3249280B2 - Interleave circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave circuit. This interleave circuit is used in a communication terminal device or the like, and performs interleave / deinterleave in order to disperse data errors generated in a burst due to the influence of noise or the like.

Communication terminal devices tend to be smaller and lighter year by year. In particular, the tendency is remarkable for automobile telephones, mobile telephones, and the like, and rapid miniaturization is being implemented. For this reason, there is a demand for a configuration in which the interleave circuit built in the communication device can be realized on a small scale.

[0003]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional interleave circuit, and its description will be given. The interleave circuit shown in FIG. 1 is used, for example, in a communication terminal, and depends on the communication mode, m ₁ × n ₁ , m ₂ × n ₂ , m ₃ × n
₃ is performed three types of interleaving.

In the case of m × n interleaving, for example, 3 × 4 interleaving, each numerical value of a matrix table of 3 rows × 4 columns shown in FIG. 5 is traced from left to right in a horizontal direction, and this trace is traced from top to bottom. A sequence of numbers that are shifted one by one to rows and arranged sequentially
0, 3, 6, 9, 1, 4, 7, A, 2, 5, 8, B (1
(Hexadecimal number) as a write address signal of the memory device, the input signal is written by designating the address of the memory device with this signal, and each numerical value of the matrix table is traced vertically from top to bottom, and this trace is traced from left to right. To 0,1,2,3,4,5,6,7,8,9, A, B
(Increment data) as a read address signal,
With this signal, data previously stored in the memory device is read and used as output data.

In FIG. 4, 1 is a dual port RAM.
(DPRAM), 2, 3, and 4 are write address generation circuits,
5 is a selector and 6 is a read address generation circuit. The write address generation circuit 2 generates a write address signal WS1 for performing m ₁ × n ₁ interleaving, and the write address generation circuit 3 generates a write address signal WS2 for performing m ₂ × n ₂ interleaving. And the write address generating circuit 4 generates a write address signal WS3 for performing m ₃ × n ₃ interleaving.

The selector 5 selects one of the write address signals WS1, WS2 and WS3 according to the mode identification signal Mode and outputs the selected signal to the write address signal input terminal WA of the DPRAM 1.

The read address generating circuit 6 outputs a read address signal RA1. However, the read address signal RA1 is 0, 1, 2, 3, ..., 9, A, B,
.. (In hexadecimal).

The DPRAM 1 stores input data Di according to write address signals WS1, WS2, WS3 input from one port, and outputs the stored data according to a read address signal RA1 input from the other port. It is output as data Do.

For example, a 3 × 4 interleave is performed in the first mode, a 2 × 6 interleave is performed in the second mode, and a 4 × 3 interleave is performed in the third mode. A write address signal for performing the 4 × 3 interleave is used. Is generated by the write address generation circuit 2, the write address generation circuit 3 generates a write address signal for performing 2 × 6 interleaving, and the write address signal for performing 4 × 3 interleaving. It is assumed that the generation circuit 4 generates the signal.

The 3 × 4 interleaving is performed by using 0, 3, 6, 9, 1, 4, 7, A,
The input data Di is written by designating the address of the DPRAM1 with the write address signal WS1 of a sequence of 2, 5, 8, and B (hexadecimal), and the written data is read address signal RA1 of the increment data obtained from the matrix table. And output data Do.

The 2 × 6 interleave is obtained from 0, 2, 4, 6, 8, A, 1, 3, obtained from the matrix table shown in FIG.
The address of the DPRAM1 is designated by the write address signal WS2 of the sequence of 5, 7, 9, and B (hexadecimal) to write the input data Di, and the written data is read by the read address signal RA1 obtained from the matrix table. The output data is Do.

The 4 × 3 interleaving is performed using 0, 4, 8, 1, 5, 9, 2, 6, and 6 obtained from the matrix table shown in FIG.
The address of the DPRAM1 is designated by the write address signal WS3 of a sequence of A, 3, 7, and B (hexadecimal) to write the input data Di, and the written data is read by the read address signal RA1 obtained from the matrix table. The output data is Do.

That is, in the interleave circuit shown in FIG. 4, the write address signals WS1, WS2 and WS3 are selected by the selector 5 in accordance with the mode identification signal Mode, and the input data Di is converted to the DPRAM1 by the selected write address signal. Is stored. Then, it is read out as output data Do by the read address signal RA1.

By performing interleaving in this way, it is possible to disperse data errors that occur consecutively, so that error correction after interleave processing can be performed correctly. If errors are continuous, error correction cannot be performed correctly.

[0015]

As described above, in the conventional interleave circuit, one port is used only for writing and the other port is used only for reading while using the DPRAM 1 so that the control is not complicated. When a plurality of types of interleaving are to be controlled by separate / read address generation circuits, and dedicated write address generation circuits 2 to 4 corresponding to each interleave,
And the selector 5 is used for switching.

In the configuration using such a DPRAM, the number of control signals increases when the DPRAM is used as an external RAM.
AM). Also, DP
When the RAM is built in an LSI, the number of gates of the circuit increases. Further, an address generation circuit for two ports is required. Further, when performing a plurality of types of interleaving, a number of address generating circuits corresponding to the types are required.

As described above, the conventional interleave circuit has a problem that the scale becomes large. The present invention has been made in view of such a point, and an object of the present invention is to provide an interleave circuit capable of performing a plurality of types of interleaving on a small scale.

[0018]

FIG. 1 shows a principle diagram of an interleave circuit according to the present invention. The interleave circuit has a number of rows m × number of columns n, and an array of numerical values increasing in increments of “1” from the first row of the first column to the m-th row of the n-th column by going from top to bottom in each column. From the first column to the n-th
Trace in the column direction and trace this trace from the first row to the n-th
Data Di is written in the storage means (11) by using a numerical value obtained by shifting each row to the row as a write address signal, and the numerical values in the matrix are traced from the first row to the nth row. By performing this trace by shifting each line from the first column to the m-th column by one row, using a numerical value obtained sequentially as a read address signal, performing interleaving such as reading data written in the storage means (11). It is.

A feature of the present invention is that the first setting means 13 sets a first setting value M which is a numerical value corresponding to the number m of rows.
And a second set value N which is a numerical value corresponding to the number of columns n described above.
Setting means 14 for setting the value “1” from the second setting value
Is obtained by cumulatively adding "1" to the initial value and the initial value of the first row of the first column in the matrix described above. This is sequentially performed for each numerical value, and a sequence obtained by performing this process until a numerical value obtained by subtracting “1” from the number m of rows is added to the initial value is output as an address signal Awr corresponding to the write address signal. When the predetermined numerical value set by the first setting means 13 is set as the first setting value M, the number of times corresponding to the numerical value obtained by subtracting “1” from the initial value and the calculation result of the number of rows m × the number of columns n Address generating means 12 for outputting a sequence of numerical values sequentially obtained by cumulatively adding "1" to the initial value as an address signal Awr corresponding to the read address signal. is there.

[0020]

According to the present invention described above, the address generating means 1
2 can output a read / write common address signal Awr, so that the storage means 11 can be a single-port RAM. Further, even when a plurality of types of interleaving are performed, the number of rows m
And the first and second set values M and N corresponding to the number n of columns and the number of columns, can be handled by one address generating means 12.

Conventionally, a dual-port RAM must be used, and a write address signal and a read address signal are generated by different generating means. Further, when a plurality of types of interleaving are performed, A corresponding number of write address signal generating means must be used.

Comparing the RAMs, the single-port RAM is 1/2 to 1/3 the size of the dual-port RAM, and the address generating means 12 becomes smaller as the number of types of interleaving increases. ,
According to the present invention, the whole circuit can be made very small.

Further, even if the values of m and n are changed by the use change, it is possible to easily cope with the change.

[0024]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing a configuration of an interleave circuit according to one embodiment of the present invention.

In this figure, 11 is a single port R
AM (hereinafter referred to as RAM), 12 is an address generation circuit,
13 is an address addition value setting unit, and 14 is an address addition frequency setting unit.

The address generation circuit 12 determines the addition value M set by the address addition value setting section 13 and the addition number N set by the address addition number setting section 14.
Write / read address signals Awr3 to Awr0 for performing m × n interleaving described in the conventional example.
To the address signal input terminals AD3 to AD0 of the RAM 11.

However, the setting addition value M corresponds to the number of rows m, and is set as 4-bit addition value data Ad3 to Ad0 by the address addition value setting unit 13. This setting is performed by turning on / off each of the switches 16, 17, 18, and 19. For example, when the setting addition value M is set to “4”, only the switch 17 is turned on and the addition value data Ad3 to Ad
0 is set to “0100” in order from the upper bit.

The set addition number N corresponds to the column number n-1, and is set as 4-bit addition number data CT3 to CT0 by the address addition number setting unit 14. This setting is performed by turning on / off each of the switches 21, 22, 23, and 24. For example, when the set addition number N is set to "2", only the switch 23 is turned on and the addition value data CT3
ＣＴCT0 is “0010” in order from the upper bit.

The above setting is for the case of outputting a write address signal. To output the read address signal, only the switch 19 is turned on and the added value data A
This is because only the least significant bit of d3 to Ad0 is set to "1". In this case, the increment data is output as a read address signal.

The LD input to the address generating circuit 12 is a load signal for starting writing / reading of data to / from the RAM 11, the EN is an enable signal, and the CLK is
Is a clock signal, and RST is a reset signal.

The address generating circuit 12 includes an adder (ADD) 27 for adding two sets of 4-bit data, a 4-bit down counter (DCT) 28, a 4-bit up counter (UCT) 28, A selector (SEL) 30 for selecting any one set of 4-bit data, a 4-bit flip-flop (FF) 31, a 4-input type OR circuit 32 having one input terminal inverted, It has two input type AND circuits 33 and 34 and a two input type AND circuit 35 with one input terminal being an inverting terminal.

The ADD 27 is for adding the values of the address signals Awr3 to Awr0 output as write address signals while skipping by the number corresponding to the number m of rows, and one of the data input terminals b3 to b0 of one set. , And the address signals Awr3-Awr0 output from the output terminals Q3-Q0 of the FF 31 are input to the other set of data input terminals A3-A0.

The DCT 28 limits the number of times (the number of columns n) of adding the address signals Awr3 to Awr0 output as the write address signal while skipping the number by the number corresponding to the number m of rows. Input count data CT3 to CT0 are input to input terminals d3 to d0, output data of AND circuit 35 is input to load terminal L, which is an inverting terminal, and clock signal CL is input to a clock terminal.
K, an enable signal EN is input to an enable terminal EN, a reset signal RST is input to a reset terminal R,
Carry input terminal CI is fixed at "H" level.

DCT2 is connected to the inverting input terminal of the AND circuit 35.
8 carry signal C output from carry output terminal CO
O1 is input, and the load signal LD is input to the other input terminal.

In the UCT 29, the values of the address signals Awr3 to Awr0 output as the write address signals are added while being skipped by the number corresponding to the number m of rows.
When the number of times of addition becomes equal to the number n of columns, the value of the address signals Awr3 to Awr0 is shifted to the head of the next row.

In the UCT 29, the data input terminals d3 to d1 of the fourth to second bits are fixed at the "L" level,
The data input terminal d0 of the bit is fixed at the “H” level, the load signal LD is input to the load terminal L which is the inverting terminal, the clock signal CLK is supplied to the clock terminal, the enable signal EN is supplied to the enable terminal EN, Carry input end C
A carry signal CO1 is inputted to I, and a reset signal RST is inputted to a reset terminal R.

When the output data of the AND circuit 33 is at the "L" level, the SEL 30 has one of the input terminals A3 to A3.
0, the output data AS3 to AS0 from the output terminals S3 to S0 of the ADD 27 are selected, and when the output data of the AND circuit 33 is at the "H" level, the other set of input terminals b
The output data UQ3 to UQ0 from the output terminals Q3 to Q0 of the UCT 29 supplied to 3 to b0 are selected and output.

The carry signal CO1 is input to one input terminal of the AND circuit 33, and the output data of the OR circuit 32 is input to the other input terminal. The addition value data Ad0 is input to the inverting input terminal of the OR circuit 32, and the addition value data Ad3 to Ad1 are input to the other three input terminals.

The FF 31 outputs the output data SS from the output terminals S3 to S0 of the SEL 30 supplied to the input terminals d3 to d0.
3 to SS0 are triggered by the clock signal CLK and held, and the held data is stored in the address signals Awr3 to Awr3.
wr0 to the address terminals AD3 to AD0 of the RAM 11, and the enable signal is output to the enable terminal.
N, a clock signal CLK is input to a clock terminal CK, and output data of the AND circuit 34 is input to a reset terminal R.

The load signal LD is inputted to one input terminal of the AND circuit 34, and the reset signal RST is inputted to the other input terminal. The operation when 3 × 4 interleaving (see FIG. 5) is performed in the interleave circuit having such a configuration will be described with reference to the timing chart of FIG.

However, in FIG. 3, the count value of the DCT 28 and the output data UQ3 to UQ0 of the UCT 29 are decimal numbers, and the output data AS3 to AS0 and SEL3 of the ADD 27.
0 output data SS3 to SS0 and an address signal Aw
r3 to Awr0 are represented by hexadecimal numbers (HEX).

First, the write operation will be described. In the case of writing, since m = 3 and n = 4, the set addition value M is set to 3 and the set addition number N is set to 3. That is, the switches 18 and 19 of the address addition value setting unit 13 are turned on, and the switches 23 and 24 of the address addition number setting unit 14 are turned on.
As a result, the addition value data Ad3 to Ad0 become “0011” in order from the most significant bit, and the addition number data CT
3-CT0 becomes "0011".

At time t1, reset signal RST changes from "L" level to "H" level. At time t2, when the load signal LD goes to “L” level, the output data of the AND circuit 34 goes to “L” level, whereby the FF 31 is reset and the address signals Awr3 to Aw
r0 becomes “0”. Then, in the RAM 11, the input data Di is written and stored in the storage area of the address of “0”.

When the load signal LD is at the "L" level,
At time t3, when the edge of the clock signal CLK rises, the DCT 28 is loaded with “3” of the additional value data Ad3 to Ad0, and the carry signal CO1 of the DCT 28 is loaded.
Becomes the "L" level, the fixed value "1" is loaded into the UCT 29, and the output data UQ3 to UQ0 of the UCT 29 become "1".

At this time, ADD27 is the added value data Ad3
"0" of the address signals Awr3 to Awr0 are added to output the data AS3 to AS0 of "3", so that when the carry signal CO1 becomes "L" level, the AND circuit 33 is output. Becomes the "L" level, and the SEL 30 selects the data AS3 to AS0 of "3" and outputs it as the data SS3 to SS0.

At time t4, the load signal LD becomes "H".
Level and the enable signal EN attains the “H” level, and at time t5, the edge of the clock signal CLK rises.
T28 counts down, the count value changes from “3” to “2”, and the FF 31 is triggered, and SEL30
Of the output data SS3 to SS0 is held. As a result, the address signals Awr3 to Awr0 become “3”. In the RAM 11, the input data Di is stored in the storage area at the address of “3”.

Since "3" of the address signals Awr3 to Awr0 is input to the ADD 27, "3" and "3" of the additional value data Ad3 to Ad0 are added, and AD3 is added.
The output data AS3 to AS0 of D27 is “6”. Since carry signal CO1 remains at "L" level, SEL
30 selects “6” and outputs the output data S of the SEL 30.
S3 to SS0 become “6”.

At time t6, the DCT 28 counts down from "2" to "1" due to the rising edge of the clock signal CLK, and the FF 31 is triggered to hold "6" of the data SS3 to SS0. As a result, the address signals Awr3 to Awr0 become “6”, and the input data Di is stored in the RAM 11 in the storage area of the address of “6”.

Further, "6" of the address signals Awr3 to Awr0 is input to the ADD 27, and the data AS3 to AS0 are inputted.
Becomes “9”, and the output data SS3 to SS0 of the SEL 30 for selecting “9” become “9”.

At time t7, the rising edge of the clock signal CLK causes the DCT 28 to count down from "1" to "0", the FF 31 is triggered, and "9" of the data SS3 to SS0 is held. As a result, the address signals Awr3 to Awr0 become “9”, and the input data Di is stored in the RAM 11 in the storage area of the address of “9”.

Further, "9" of the address signals Awr3 to Awr0 is input to the ADD 27, and the data AS3 to AS0 are inputted.
Becomes “C”. Since DCT 28 is "0", carry signal CO1 attains "H" level, whereby the output data of AND circuit 33 attains "H" level, and SEL 30 outputs data UQ3-UQ of UCT 29.
Select "1" of 0. As a result, the output data SS3 to SS0 of the SEL 30 become “1”.

At time t8, the rising edge of the clock signal CLK causes the DCT 28 to count down from "0" to "3", the FF 31 is triggered, and "1" of the data SS3 to SS0 is held. As a result, the address signals Awr3 to Awr0 become “1”, and the input data Di is stored in the RAM 11 in the storage area of the address of “1”.

Further, "1" of the address signals Awr3 to Awr0 is inputted to the ADD 27, and the data AS3 to AS0 are inputted.
Becomes “4”. Since DCT 28 is "3", carry signal CO1 attains "L" level, which causes SEL 30 to output data AS3-AS of ADD 27.
Select "4" of 0. As a result, the output data SS3 to SS0 of the SEL 30 become “4”. UCT 29 counts up from "1" to "2" when carry signal CO1 attains "L" level, whereby data UQ3 to UQ0 become "2".

Thereafter, similarly, each time the edge of the clock signal CLK rises, the value of the address signals Awr3 to Awr0 is set to "4", "7", "A", "2", "5", "8",
The value changes to “B”, and the input data Di is stored in the storage area of the address indicated by those values.

When the enable signal EN goes low at time t9, the write operation ends. Next, a read operation will be described. For reading,
The set addition value M is set to “1”, and the set addition number N is set to an arbitrary value.

That is, since only the switch 19 is turned on in the address addition value setting section 13, the addition value data A
d3 to Ad0 become “0001”. Therefore, OR circuit 3
2 is fixed at the “L” level, the output data of the AND circuit 33 becomes the “L” level, and SEL
30 is fixed to a state of selecting only the output data AS3 to AS0 of the ADD 27.

In this state, when the clock signal CLK is sequentially supplied, the circuit circulating through the ADD 27, the SEL 30, and the FF 31 performs an accumulator operation for accumulating and adding only "1". As a result, "0, 1, 2,3,4
.., B "are output to the RAM 11 as read address signals Awr3 to Awr0, and the data stored at those addresses is output as output data Do.

As described above, by setting the set addition value M and the set addition number N in accordance with the m × n interleaving, the read / write address signal for performing a plurality of types of m × n interleaving is obtained. Since it can be generated by one address generation circuit 12 and the storage means can be realized by a single port RAM,
It is possible to make the entire circuit considerably smaller than before.

The delay of the address generation circuit 12 is R
Since the access speed is much smaller than the access speed of the AM, the minimum access cycle is determined by the access speed of the RAM, so that operation at a high speed cycle that satisfies the access cycle of the RAM becomes possible.

[0060]

As described above, according to the interleave circuit of the present invention, there is an effect that a plurality of types of interleaves can be performed on a small scale.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an interleave circuit according to one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a conventional interleave circuit.

FIG. 5 is a diagram for describing 3 × 4 interleaving.

FIG. 6 is a diagram for describing 2 × 6 interleaving.

FIG. 7 is a diagram for describing 4 × 3 interleaving.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Storage means 12 Address generation means 13 1st setting means 14 2nd setting means

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04B 14/00 H04L 1/00

Claims (1)

(57) [Claims] 1. An array having a number of rows m × a number of columns n, and a numerical value increasing by “1” from the first row of the first column to the m-th row of the n-th column by proceeding from top to bottom in each column. Numerical values in the calculated matrix are traced in the direction from the first column to the n-th column, and the traces are shifted from the first row to the m-th row by one row. By writing data in the storage means, tracing the numerical values in the matrix in the direction from the first row to the m- th row, and shifting the trace by one column from the first column to the n-th column. In an interleave circuit for performing interleaving such as reading out data written in the storage means using the read address signal as a read address signal , the write address signal and the write address signal are connected to the storage means.
An address signal line for outputting the read address signal, and in the case of writing, the number m of rows is set, and
In this case, setting means for setting '1', and the value set in the setting means and the value on the address signal line
An adder for adding the address value indicated by the address signal ; (the number of columns n-1) is loaded, and the counter value becomes zero.
Then, a down counter that asserts the carry signal, and a count operation when the carry signal is asserted.
In the case of an up counter and writing, the carry signal
Signal is not asserted, the output signal of the adder
When the carry signal is asserted,
Select the output of the counter, and in the case of reading, the adder
Output signal, and outputs the address signal.
Interleave circuit characterized by comprising a selector, a.