JPH0290631A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0290631A
JPH0290631A JP24350488A JP24350488A JPH0290631A JP H0290631 A JPH0290631 A JP H0290631A JP 24350488 A JP24350488 A JP 24350488A JP 24350488 A JP24350488 A JP 24350488A JP H0290631 A JPH0290631 A JP H0290631A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
gate
heat
air vent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24350488A
Other languages
Japanese (ja)
Inventor
Kimio Okamoto
公男 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP24350488A priority Critical patent/JPH0290631A/en
Publication of JPH0290631A publication Critical patent/JPH0290631A/en
Pending legal-status Critical Current

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent unnecessary resin from remaining on the side of a semiconductor device by allowing the resin to adhere on heat-proof sheets by a method wherein the heat-proof sheets, having almost same shape as cavities, are inserted between the dies, on which a gate and an air vent are formed, and the semiconductor device side. CONSTITUTION:Heat-proof sheets 6 and 7, having the holes 6a and 7a formed almost in the same shape as the cavities 4a and 5a formed on the upper die 4 and the lower die 5, are arranged in such a manner that their holes 6a and 7a are located on the same position as the cavities 4a and 5a. Besides, a gate 8 is provided on the surface of the side of the lower metal mold 5, namely, on the surface of the side of a TAB substrate 3, and an air vent 9 is provided on the side of the TAB substrate 3 of the upper die 4 respectively. Then, epoxy resin 10 is implanted into the cavities 4a and 5a from the gate 8. The upper die 4 and the lower die 5 are removed, and when the heat-proof sheets 6 and 7 on the upper and the lower surfaces are removed, and as the resin pieces 10a and 10b left on the gate 8 and the air vent 9 are adhered to the heat-proof sheets 6 and 7 respectively, the resin can be removed easily. Accordingly, the removal of unnecessary resin from the TAB substrate is unnecessary.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.

従来の技術 近年、Icカード、メモリーカード用、あるいは補@器
用などの、超薄型、超小型の半導体装置が要求され、ま
九外部引出リード数が200ピン程度の超多ビンは、ワ
イヤーボンディングが困難であるなどのため、TAB方
式によ・る半導体装置の必要が強まって来た。
Conventional technology In recent years, there has been a demand for ultra-thin and ultra-small semiconductor devices for IC cards, memory cards, and auxiliary devices, and wire bonding is used to manufacture extremely large numbers of external drawer leads of about 200 pins. Due to the difficulty of the TAB method, the need for semiconductor devices based on the TAB method has increased.

TAB方式による半導体装置の製造方法は、ウェハー上
に形成された個々の半導体素子の外部引出電極であるポ
ンディングパッド上に、TiあるいはCrなどのバリヤ
ー金属層を介して、メツキ方法によシAuバンブを設け
1個40半導体素子に分割する一方、中35111II
、厚み125 prnで所定の穴を有するポリイミドフ
イμム上に貼り付けられた厚み35絢のCu箔をエツチ
ングして、回路を形成し、このCu回路にSnあるいは
九などのメツキを施してなる謔基板のCu回路の所定の
位置と、前記半導体素子のムパンプとを対向配置し、加
圧、加熱することに↓リボンディングをおこなった後、
半導体素子の表面部分をエポキシ樹脂を滴下して覆う封
止工程、電気的特性検査工程などを経て、完成されるの
が従来の製造方法であり7t、 t、かし、前記し几エ
ボキ¥樹脂を滴下する対土方法では、滴下された工ポキ
ン樹脂は粘度のわずかの差によって広がり具合が異なり
、硬化し友際の形状が一定とはならず。
The method for manufacturing semiconductor devices using the TAB method is to deposit Au onto the bonding pads, which are external lead electrodes of individual semiconductor elements formed on a wafer, through a barrier metal layer such as Ti or Cr, using a plating method. While providing bumps and dividing each into 40 semiconductor elements, the middle 35111II
A circuit is formed by etching a 35-thick Cu foil pasted on a polyimide film with a thickness of 125 prn and having predetermined holes, and plating the Cu circuit with Sn or 9. After performing rebonding, the predetermined position of the Cu circuit on the substrate and the pump of the semiconductor element are placed facing each other, and pressure and heat are applied.
In the conventional manufacturing method, the semiconductor element is completed through a sealing process of dropping epoxy resin onto the surface of the semiconductor element, an electrical characteristic testing process, etc. In the soil method, where the resin is dropped, the degree of spreading varies depending on the slight difference in viscosity, and the shape of the resin does not remain constant when it hardens.

また半導体素子の周辺部には充分な樹脂がコーティング
されないため、半導体素子上に形成されtAuパンヅと
、TAB基板のCu回路との接合部と、滴下されたエポ
キシ樹脂の外部に露出したCu回路との距離がいちじる
しく短いなどのために、完成され九半導体装置の耐温性
を主とした信頼性に劣り、し友がって安定した封止形状
と、高い信頼性を得ルタめに、トフンスファー成型によ
る封止方法が検討されており、第2図(a)およびTb
) t−参照して従来の方法によるトフンスファー封止
方法を説明する。
In addition, since the peripheral area of the semiconductor element is not coated with sufficient resin, the junction between the tAu pans formed on the semiconductor element and the Cu circuit on the TAB substrate, and the Cu circuit exposed to the outside of the dropped epoxy resin. Due to the extremely short distance between the two semiconductor devices, the temperature resistance and other reliability of the completed semiconductor device was poor, and the semiconductor device that was completed had a stable sealing shape and high reliability. A sealing method by molding is being considered, and Fig. 2(a) and Tb
) A conventional method of sealing Tofunsfer will be described with reference to T-T.

第2図(alは封止用金型内にエポキシ樹脂が充填され
、トランスファー成形が完了した状態ヲ示す。
FIG. 2 (Al shows the state in which the sealing mold is filled with epoxy resin and transfer molding is completed.

すなわち、半導体素子21を、ポリイミドフィルム22
上のCu回路23に、 Auバンプ24t−介してポン
ディングし7’j TAB基板25ヲ、上金型26と、
下金型27とで挟んで加圧、加熱し、下金型27に形成
されたゲート28を通じてキャビティ29内に溶融し之
樹脂30を圧送し、樹脂封止を行う方法である。ところ
で。
That is, the semiconductor element 21 is made of polyimide film 22.
The upper Cu circuit 23 is bonded via the Au bump 24t, and the TAB substrate 25 and the upper mold 26 are bonded.
In this method, the resin 30 is sandwiched between the lower mold 27 and pressurized and heated, and the melted resin 30 is pumped into the cavity 29 through the gate 28 formed in the lower mold 27, thereby performing resin sealing. by the way.

下金型26に形成されたエヤーベンF31は、樹脂の圧
送に際して、前記キャビティ9内の空気などを排出させ
る九めのものであり、すきまは略0.03mであり、通
常ごくわずかの樹脂が漏れるようになっている。また、
第2図Tblは、前記第2図(atでトランスファー成
形が完了し、上金型26と、下金型27とを開き、半導
体装置を取り出し定状態を示す図である。すなわち、T
AB基板25の下面にはゲート28に充填された樹脂3
0aがそのまま付着しており、またエヤーベント31に
漏れたごくわずかの樹脂30bは、 TAB基板25の
上面に付着しており、これらの不要な樹脂を除去する必
要がある。
The air vent F31 formed in the lower mold 26 is the ninth one that discharges the air inside the cavity 9 when the resin is pumped.The gap is approximately 0.03 m, and a very small amount of resin usually leaks. It looks like this. Also,
FIG. 2 Tbl is a diagram showing the normal state after transfer molding is completed in FIG. 2 (at), the upper mold 26 and the lower mold 27 are opened, and the semiconductor device is removed.
The bottom surface of the AB substrate 25 has a resin 3 filled in the gate 28.
0a is still attached, and a very small amount of resin 30b that leaked into the air vent 31 is attached to the upper surface of the TAB board 25, and it is necessary to remove these unnecessary resins.

発明が解決しようとする課題 従来のTAB方式による半導体装置の製造方法では、開
目したようにゲートあの樹脂30aと、エヤーベント3
1にごくわずか漏れた樹脂30bとがTAB基板25に
付着しており、その除去が必要となるが。
Problems to be Solved by the Invention In the conventional TAB method for manufacturing semiconductor devices, the gate resin 30a and the air vent 3
However, a very small amount of the resin 30b leaked from the TAB substrate 25 adheres to the TAB substrate 25, and it is necessary to remove it.

TAB基板25は前記したように薄いシートであり、不
要の樹脂の除去に際して、 TAB基板25が変形。
As mentioned above, the TAB substrate 25 is a thin sheet, and when unnecessary resin is removed, the TAB substrate 25 is deformed.

破損などを起し、半導体装置を不良にしてしまうという
課題があった。
This poses a problem in that it may cause damage, resulting in a defective semiconductor device.

そこで、本発明は上記課題を解消し得る半導体装置の製
造方法を提供することを目的とする。
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above problems.

課題を解決するための手段 上記課題を解決する究め、本発明の半導体装置の製造方
法は、上金型と下金型のキャビティ内に半導体素子を格
納させt後、前記上金型または下金型のいずれかに形成
されたゲートから、前記キャビティ内に溶融樹脂を圧入
しつつ、前記上金型または下金型のいずれかに形成され
たエヤーベントからキャビティ内のエヤーを抜いて半導
体素子の樹脂封止上行なう際に、前記ゲートおよびエヤ
ーベントが形成された金型と、半導体装置側との間に前
記キャビティと略同形状の穴を有する耐熱性シートを挿
入する製造方法である。
Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention provides a semiconductor device manufacturing method according to the present invention, in which a semiconductor device is housed in a cavity of an upper mold and a lower mold, and then Molten resin is press-fitted into the cavity through a gate formed in one of the molds, and air in the cavity is extracted from an air vent formed in either the upper mold or the lower mold to release the resin of the semiconductor element. In this manufacturing method, when performing sealing, a heat-resistant sheet having a hole approximately the same shape as the cavity is inserted between the mold in which the gate and air vent are formed and the semiconductor device side.

作用 上記の半導体装置の製造方法によれば、エヤーベントお
よびゲートに伐る不要な樹脂は、耐熱性シートに付着す
る定め、半導体装置側に伐ることはない。
Effect: According to the method for manufacturing a semiconductor device described above, unnecessary resin that is removed from the air vent and gate is attached to the heat-resistant sheet, and is not removed from the semiconductor device side.

実施例 以下、本発明の一実施例における製造方法を、第1図(
al〜(clに基づき説明する。
EXAMPLE Below, a manufacturing method in an example of the present invention will be explained as shown in Fig. 1 (
al~(Explain based on cl.

まず、第1図(alに示すように、半導体素子1が荊バ
ンプ2より取付けられ7t TAB基板3の上下面に、
封止体の投影形状と同一形状、すなわち上金型および下
金型(第1図(b)参照)4.5に形成されtキャビテ
ィ4a+5aと同一形状の穴6a*7aをそれぞれ有す
る耐熱性シー)6.7t、その穴6a、7aがキャビテ
ィ4a、5aと同一位置となるように配置する。なお、
下金型5の半導体装置側すなわち謔基板3側表面にゲー
ト8が、また上金型4のTAB基板3側表面にエヤーベ
ント9がそれぞれ設けられている。また、前記耐熱性シ
ート6.7については、厚さが略0.05w程度で、材
質がTAB基板3と同一のものがよい。
First, as shown in FIG.
A heat-resistant sheet having the same shape as the projected shape of the sealing body, that is, holes 6a*7a formed in the upper and lower molds (see FIG. 1(b)) and having the same shape as the T cavities 4a+5a, respectively. ) 6.7t, arranged so that the holes 6a and 7a are in the same position as the cavities 4a and 5a. In addition,
A gate 8 is provided on the surface of the lower mold 5 facing the semiconductor device, that is, the surface facing the substrate 3, and an air vent 9 is provided on the surface of the upper mold 4 facing the TAB substrate 3. The heat-resistant sheet 6.7 preferably has a thickness of about 0.05w and is made of the same material as the TAB substrate 3.

次に、第1図(b)に示すように、温度170’C〜1
80℃に加熱し1、上金型4および下金型5により、 
TAB基板3t−上下から挟み込む。勿論、TAB基板
3に取付けられ九半導体素子lはキャビティ4a、5a
の中に格納されt状態となっている。そして、次にゲー
ト8からキャビデイ4ae5a内に、エポキシ樹脂10
t−30に〜〜70ρ臼の圧力でもって注入する。
Next, as shown in FIG. 1(b), the temperature is 170'C to 1
Heating to 80°C 1, using upper mold 4 and lower mold 5,
TAB board 3t - sandwich from above and below. Of course, the nine semiconductor elements l mounted on the TAB substrate 3 are placed in cavities 4a and 5a.
It is stored in the t state. Then, from the gate 8 into the cavity 4ae5a, epoxy resin 10
Inject at t-30 with a pressure of ~70μ.

なお、樹脂注入に際して、エヤーベント9からキャビテ
ィ4a、5a内の空気と一緒にごく少量の樹脂10も漏
れ出る。
In addition, when resin is injected, a very small amount of resin 10 also leaks out from the air vent 9 together with the air inside the cavities 4a and 5a.

この後、第1図(C)に示すように、1企′m4および
下金型5を取除き、そしてさらに上下面の耐熱性シート
6.7を除去すれば、ゲート8およびエヤーベント9に
残つt樹脂10a 、 10bはそれぞれ耐熱性シート
6.7に付着しているため、容易に除去することができ
る。したがって、TAB基板3から不要な樹脂を除去す
る必要がない九め、TAB基板3を傷付ける虞れがない
After that, as shown in FIG. 1(C), the first mold 4 and the lower mold 5 are removed, and the heat-resistant sheets 6.7 on the upper and lower surfaces are also removed, remaining on the gate 8 and air vent 9. Since the resins 10a and 10b are attached to the heat-resistant sheet 6.7, they can be easily removed. Therefore, there is no need to remove unnecessary resin from the TAB substrate 3, and there is no risk of damaging the TAB substrate 3.

ところで、上記実施例においては、TAB方式のものに
ついて説明し九がたとえば金属製のり−ドフV−ムを基
板とする半導体装置に適用した場合でも、同様の効果が
得られる。
Incidentally, in the above embodiment, the TAB type is described, but even when applied to a semiconductor device using a metal glue film as a substrate, the same effect can be obtained.

発明の効果 以上のように1本発明の半導体装置の製造方法によれば
、エヤーベントおよびゲートに伐る不要な樹脂は、耐熱
性シートに付着して半導体装置側に伐らないので、従来
のような不要な樹脂の除去による半導体装置側の変形お
よび破損を階無にし得、したがって半導体装置の歩留り
を向上させることができ、まtTABTAB方式場合、
TAB基板に形成されるパターンに影響されることなく
、ゲートやエヤーベントを配置でき、やはり半導体装置
の歩留りの向上につながる。
Effects of the Invention As described above, 1. According to the method for manufacturing a semiconductor device of the present invention, unnecessary resin that is removed from the air vent and gate adheres to the heat-resistant sheet and is not removed from the semiconductor device side, so that unnecessary resin is not removed from the semiconductor device side as in the case of the conventional method. In the case of the TABTAB method, it is possible to eliminate deformation and damage on the semiconductor device side due to the removal of the resin, thereby improving the yield of semiconductor devices.
Gates and air vents can be arranged without being affected by the pattern formed on the TAB substrate, which also leads to an improvement in the yield of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(clは本発明の一実施例に係る半導体
装置の製造工程を示す断面図、第2図(alおよび(b
lは従来例に係る半導体装置の製造工程を示す断面図で
ある。 1・・・半導体素子、2X・・・Auバンプ、3・・・
TAB基板、4・・・上金型、4a・・・キャビティ、
5・・・下金型、5a・・・キャビティ、6.7・・・
耐熱性シー)、6a、7a・・・穴、8・・・ゲー・ト
、9・・・エヤーベント、10・・・樹脂。 代理人     森   木   義   私用1図 第2図 (ンノ Cトン
FIGS. 1(a) to (cl) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (b)
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional example. 1... Semiconductor element, 2X... Au bump, 3...
TAB substrate, 4... upper mold, 4a... cavity,
5... Lower mold, 5a... Cavity, 6.7...
Heat resistant sea), 6a, 7a...hole, 8...gate, 9...air vent, 10...resin. Agent Yoshi Moriki Private use Figure 1 Figure 2 (Nno C ton)

Claims (1)

【特許請求の範囲】[Claims] 1、上金型と下金型のキャビティ内に半導体素子を格納
させた後、前記上金型または下金型のいずれかに形成さ
れたゲートから、前記キャビティ内に溶融樹脂を圧入し
つつ、前記上金型または下金型のいずれかに形成された
エヤーベントからキャビティ内のエアーを抜いて半導体
素子の樹脂封止を行なう際に、前記ゲートおよびエヤー
ベントが形成された金型と、半導体装置側との間に前記
キャビティと略同形状の穴を有する耐熱性シートを挿入
する半導体装置の製造方法。
1. After storing semiconductor elements in the cavities of the upper mold and the lower mold, press-fitting molten resin into the cavities from the gate formed in either the upper mold or the lower mold, When sealing a semiconductor element with resin by removing air from the cavity from an air vent formed in either the upper mold or the lower mold, the mold in which the gate and air vent are formed and the semiconductor device side are removed. A method of manufacturing a semiconductor device, wherein a heat-resistant sheet having a hole having substantially the same shape as the cavity is inserted between the cavity and the cavity.
JP24350488A 1988-09-28 1988-09-28 Manufacture of semiconductor device Pending JPH0290631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24350488A JPH0290631A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24350488A JPH0290631A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0290631A true JPH0290631A (en) 1990-03-30

Family

ID=17104883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24350488A Pending JPH0290631A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0290631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006199527A (en) * 2005-01-19 2006-08-03 Shin Etsu Chem Co Ltd Method of manufacturing porous glass preform and burner for deposition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006199527A (en) * 2005-01-19 2006-08-03 Shin Etsu Chem Co Ltd Method of manufacturing porous glass preform and burner for deposition

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