JPH0289348A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0289348A JPH0289348A JP63241350A JP24135088A JPH0289348A JP H0289348 A JPH0289348 A JP H0289348A JP 63241350 A JP63241350 A JP 63241350A JP 24135088 A JP24135088 A JP 24135088A JP H0289348 A JPH0289348 A JP H0289348A
- Authority
- JP
- Japan
- Prior art keywords
- container
- recessed part
- wiring layer
- conductor wiring
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 15
- 239000000565 sealant Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 239000004593 Epoxy Substances 0.000 abstract description 2
- 238000004382 potting Methods 0.000 abstract description 2
- 230000035515 penetration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はフィルムキャリア方式半導体素子のプリント基
板への実装に用いる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device used for mounting a film carrier type semiconductor element on a printed circuit board.
従来の技術
従来、フィルムキャリア実装方式における半導体素子の
プリント基板上への実装方法としては、フィルム状態で
のアウターリードボンディングが行なわれていた。以下
第３図により従来例を説明する。2. Description of the Related Art Conventionally, as a method for mounting a semiconductor element on a printed circuit board using a film carrier mounting method, outer lead bonding in a film state has been performed. A conventional example will be explained below with reference to FIG.
第３図において、２１は半導体素子、２２はバンブ、２
３はフィルムキャリア、２４はインナーリード、２５は
アウターリード、２６はプリント基板上導体配線層、２
７はプリント基板、２８は封止剤、２９は外被材である
。まず、半導体素子２１をインナーリード２４に接合し
た後、半導体素子２１およびインナーリード２４を封止
剤２８により封止した一連のフィルムキャリアより一素
子分のフィルムキャリアを打ち抜き、プリント基板２７
上の導体配線層２６上に移送する。この後、加熱圧着等
によりフィルムキャリア２３のアウターリード２５とプ
リント基板上導体配線層２６とを接合して、外被材２９
により覆う。In FIG. 3, 21 is a semiconductor element, 22 is a bump, 2
3 is a film carrier, 24 is an inner lead, 25 is an outer lead, 26 is a conductor wiring layer on a printed circuit board, 2
7 is a printed circuit board, 28 is a sealant, and 29 is an outer cover material. First, after bonding the semiconductor element 21 to the inner lead 24, a film carrier for one element is punched out from a series of film carriers in which the semiconductor element 21 and the inner lead 24 are sealed with a sealant 28, and the printed circuit board 24 is
It is transferred onto the upper conductor wiring layer 26. Thereafter, the outer lead 25 of the film carrier 23 and the conductor wiring layer 26 on the printed circuit board are bonded together by heat compression bonding or the like, and the outer cover material 29
covered by.
発明が解決しようとする課組
しかしながら上記の従来の構成では、アウターリードボ
ンディング装置がその工程専用であるため、実施にあた
り、組立設備に経費がかさむという難点を有していた。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, since the outer lead bonding device is dedicated to that process, there is a problem in that the cost of assembly equipment increases when implementing it.
さらに、アウターリードの本数およびピッチが一定せず
、製品によって異なるため、アウターリードボンディン
グ工程は個別対応となり、接合条件等に経験を要し、こ
れもフィルムキャリア実装技術の普及の妨げになってい
た。なお、半導体素子をフィルムキャリアに実装したま
まの状態では、素子としての信頼性を保証することも難
しかった。Furthermore, since the number and pitch of outer leads are not constant and vary depending on the product, the outer lead bonding process has to be handled individually and requires experience in determining bonding conditions, etc., which has also hindered the spread of film carrier mounting technology. . It is also difficult to guarantee the reliability of the semiconductor element while it is still mounted on the film carrier.
本発明は上記従来の問題点を解決するもので、プリント
基板上への実装時の取り扱いが容易であり、実装も従来
の表面実装素子に用いられたのと同様な方法により行な
うことが可能な半導体素子の装置を提供することを目的
とする。The present invention solves the above conventional problems, and is easy to handle when mounted on a printed circuit board, and can be mounted using the same method used for conventional surface mount devices. The object of the present invention is to provide a device for a semiconductor element.
課題を解決するための手段
この目的を達成するために、本発明の半導体装置は、導
体配線層を有し、半導体素子を収納しつる凹部を有する
容器にアウターリードボンディングし、凹部を封止する
ことによって成型する構成を有している。また、このと
き、凹部に貫通孔を設けておけば、容器凹部の反対側か
ら樹脂等を封入することができ、気泡の発生等のない、
より良好な封止が可能である。また、この貫通孔を放熱
板取りつけ孔として用いることもできる。さらに、容器
凹部側壁に傾斜を有するようにすれば、導体配線層と容
器表面との接着状態をより良好とすることができる。こ
の上、容器凹部周辺凸部上の導体配線層相互の間に溝部
を設ければ、パッケージをプリント基板導体配線上に実
装する際にはんだが流れて隣り合う導体配線と短絡する
等のトラブルをなくすことができる。なお、容器や封止
部に凹部または凸部または表示を設けておけば端子番号
の識別に使用したり、パッケージをプリント基板上に実
装する際の目印にできる。Means for Solving the Problems In order to achieve this object, a semiconductor device of the present invention has a conductor wiring layer, outer leads are bonded to a container having a recess for storing a semiconductor element, and the recess is sealed. It has a structure that is molded by molding. In addition, if a through hole is provided in the recess at this time, resin etc. can be filled from the opposite side of the container recess, thereby preventing the generation of air bubbles.
Better sealing is possible. Moreover, this through hole can also be used as a heat sink mounting hole. Furthermore, if the side walls of the recessed portion of the container are sloped, the state of adhesion between the conductor wiring layer and the surface of the container can be improved. In addition, if a groove is provided between the conductor wiring layers on the protrusion around the recess of the container, troubles such as solder flowing and shorting between adjacent conductor wirings can be avoided when the package is mounted on the printed circuit board conductor wiring. It can be eliminated. Note that if a recess or a protrusion or a mark is provided on the container or sealing part, it can be used to identify the terminal number or as a mark when mounting the package on a printed circuit board.
作用
この構成によって、フィルムキャリアに実装された半導
体素子は剛性をもつ基板内に実装され、取り扱いが極め
て容易になる。プリント基板導体配線上・＼の実装もフ
ラットパッケージ等の従来の面実装パッケージと同様に
リフローソルダリング法やペーパーフェイズソルダリン
グ法により行なうことができる。Effect: With this configuration, the semiconductor element mounted on the film carrier is mounted within a rigid substrate, making it extremely easy to handle. Mounting on the printed circuit board conductor wiring can also be carried out by reflow soldering or paper phase soldering, similar to conventional surface mount packages such as flat packages.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図ａは本発明の第１の実施例における半導体装置の
構成を、第１図すは断面図を示すものである。第１図に
おいて、１は半導体素子、２はバンブ、３はフィルムキ
ャリア、４は容器、５は導体配線層、６は封止剤、７は
貫通孔、８は容器４凹部周辺凸部上に設けられた溝部、
９は切り欠き部、１０は容器四部側壁である。FIG. 1a shows the structure of a semiconductor device according to a first embodiment of the present invention, and FIG. 1 is a cross-sectional view. In FIG. 1, 1 is a semiconductor element, 2 is a bump, 3 is a film carrier, 4 is a container, 5 is a conductor wiring layer, 6 is a sealant, 7 is a through hole, and 8 is a convex portion on the periphery of a concave portion of the container 4. groove provided,
9 is a notch, and 10 is a side wall of the four parts of the container.
まず、半導体素子ｌをインナーリードボンディングした
フィルムキャリア３を容器４の四部導体配線層５にアウ
ターリードボンディングする。この容器４の材質は剛性
を有し、はんだ付は温度に数秒間さらされても反り・ひ
ずみ等を生じない耐熱性をもつものであればよ（、たと
えばエポキシ系樹脂やセラミックスでよい。また凹部側
壁を第１図に示すように傾斜を有するようにしておけば
、容器と導体配線層の接着を良好にできる。この後封止
剤６により凹部の封止を行なう。封止剤６はたとえばエ
ポキシ系ボッティング樹脂でよい。なお、封止の際、凹
部に設けた貫通孔７からも封止剤６を封入することによ
り、封止剤のまわりを良くし、気泡の発生等の無いより
良好な封止を行なうことが可能である。また容器４の凹
部周辺凸部表面の導体配線層５相互の間に溝部８を設け
ておけば、本半導体パッケージをプリント基板面、導体
配線層上に実装するときに隣り合う導体配線層同志が短
絡するといったトラブルを回避できる。また切り欠き部
９を設けることにより端子番号の識別が行なえる。さら
に容器凹部側壁１０に傾斜を有するようにすることによ
り、容器４と導体配線層５との隅部における接着を良好
にすることができる。First, the film carrier 3 on which the semiconductor element 1 is inner lead bonded is outer lead bonded to the four-part conductor wiring layer 5 of the container 4. The material of this container 4 has rigidity, and the material for soldering may be heat resistant so that it does not warp or distort even when exposed to temperature for several seconds (for example, epoxy resin or ceramics may be used. If the side walls of the recess are sloped as shown in Fig. 1, good adhesion between the container and the conductor wiring layer can be achieved.After this, the recess is sealed with a sealant 6.The sealant 6 is For example, epoxy-based potting resin may be used.In addition, when sealing, by filling the sealing agent 6 also through the through hole 7 provided in the recess, the surroundings of the sealing agent are improved and bubbles are not generated. It is possible to perform better sealing.Furthermore, if grooves 8 are provided between the conductor wiring layers 5 on the surface of the convex parts around the concave portions of the container 4, this semiconductor package can be attached to the printed circuit board surface and the conductor wiring layer. It is possible to avoid troubles such as short-circuiting between adjacent conductor wiring layers when mounting on top of each other.In addition, by providing the notch 9, terminal numbers can be identified.Furthermore, the side wall 10 of the recessed portion of the container is provided with an inclination. This makes it possible to improve the adhesion between the container 4 and the conductor wiring layer 5 at the corners.
以下本発明の第２の実施例について図面を参照しながら
説明する。A second embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の第２の実施例における半導体装置の構
成を示すものである。第２図において、１１は容器、１
２は放熱板、１３は容器１１側面に設けられた凹部、１
４はプリント基板、１５はプリント基板１４上に形成さ
れた導体配線層、１６は切り欠き部である。FIG. 2 shows the structure of a semiconductor device in a second embodiment of the invention. In Fig. 2, 11 is a container, 1
2 is a heat sink, 13 is a recess provided on the side surface of the container 11, 1
4 is a printed circuit board, 15 is a conductive wiring layer formed on the printed circuit board 14, and 16 is a notch.
まず、第１の実施例と同様な方法によって容器１１に半
導体素子を接合し、凹部を封止した後、凹部貫通孔より
封止する際に放熱板１２を取りつけたものである。この
放熱板上に表示を施し、半導体素子の識別に用いてもよ
い。また、容器１１の側面に凹部１３を設けることによ
り、プリント基板１４上の導体配線層１５上に本半導体
パッケージを実装する際の位置あわせの目印に用いるこ
とができる。切り欠き部１６は第１の実施例と同様に、
端子番号を識別するために用いている。First, a semiconductor element is bonded to a container 11 by the same method as in the first embodiment, and after the recess is sealed, a heat dissipation plate 12 is attached when sealing is performed from the recess through-hole. A mark may be placed on this heat sink and used to identify the semiconductor element. Further, by providing the recess 13 on the side surface of the container 11, it can be used as a mark for positioning when the present semiconductor package is mounted on the conductor wiring layer 15 on the printed circuit board 14. The cutout portion 16 is similar to the first embodiment,
It is used to identify the terminal number.
なお、実施例においては、双方とも導体配線層を容器凹
部面上のみに形成したが、両面に形成した構成であって
もよい。また半導体素子と容器凹部導体配線層との接合
方法はフィルムキャリア方式でな（でもよく、たとえば
ワイヤボンディングによってもよい。In addition, in both examples, the conductor wiring layer was formed only on the surface of the recessed part of the container, but the structure may be such that it is formed on both surfaces. Further, the method of bonding the semiconductor element and the conductor wiring layer in the recessed part of the container may be a film carrier method (or may be, for example, wire bonding).
発明の効果
以上のように本発明は凹部を有する容器表面上に導体配
線層を形成し、半導体素子を実装したフィルムキャリア
を接合した後凹部を封止して成型した半導体パッケージ
とすることにより、取扱いが容易で、他の表面実装パッ
ケージと同様な方法でプリント基板上への実装を行なう
ことができるものとするものである。Effects of the Invention As described above, the present invention forms a conductive wiring layer on the surface of a container having a recessed part, and after bonding a film carrier on which a semiconductor element is mounted, seals the recessed part to form a semiconductor package. It is easy to handle and can be mounted on a printed circuit board in the same manner as other surface mount packages.
この際、容器凹部に貫通孔を設けることにより封止剤の
まわりを良くし、より良好な封止を行なえる。また、容
器凹部側壁に傾斜を持たせることにより、容器表面とそ
の上に形成された導体配線層との接着を良好にすること
ができる。さらに、プリント基板上導体配線層と接着す
る側の容器上導体配線層の相互間に溝部を設けることに
より、はんだづけ時の短絡をなくすことができる。そし
て、容器または封止部に凹部または凸部または切り欠き
部または表示を設けることにより端子番号の識別の目印
またはプリント基板上実装時の位置あわせの目印とする
ことができる。At this time, by providing a through hole in the recessed portion of the container, the sealing agent can be spread around the container better, and better sealing can be achieved. Furthermore, by providing a slope to the side wall of the container recess, it is possible to improve the adhesion between the container surface and the conductor wiring layer formed thereon. Further, by providing a groove between the conductive wiring layer on the printed circuit board and the conductive wiring layer on the container on the side to be bonded, short circuits during soldering can be eliminated. By providing a concave portion, a convex portion, a notch, or a display on the container or the sealing portion, it can be used as a mark for identifying a terminal number or as a mark for positioning when mounted on a printed circuit board.
第１図は本発明の第１の実施例における半導体装置の構
成図、第２図は本発明の第２の実施例における半導体装
置の構成図、第３図は従来のアウターリードボンディン
グの＋ｔｌ成図である。
ｌ・・・・・・半導体素子、２・・・・・・バンプ、３
・・・・・・フィルムキャリア、４・・・・・・容器、
５・・・・・・導体配線層、６・・・・・・封止剤、７
・・・・・・貫通孔、８・・・・・・溝部、９・・・・
・・切り欠き部、１０・・・・・・容器凹部側壁、１３
・・・・・・容器側面凹部。
代理人の氏名 弁理士 粟野重孝 はか１名第３図FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a +tl configuration of conventional outer lead bonding. It is a diagram. l... Semiconductor element, 2... Bump, 3
...Film carrier, 4...Container,
5... Conductor wiring layer, 6... Sealant, 7
...Through hole, 8...Groove, 9...
... Notch, 10 ... Container recess side wall, 13
...Concave part on the side of the container. Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 3
Claims (5)
ら周辺の凸部にわたる導体配線層を表面上に形成した剛
性容器により、上記凹部に上記半導体素子を配し、その
電極と上記導体配線層とを接続し、上記凹部を封止剤で
埋めたことを特徴とする半導体装置。(1) A rigid container is provided with a recess capable of accommodating a semiconductor element, and has a conductor wiring layer formed on the surface extending from the recess to a surrounding protrusion, and the semiconductor element is arranged in the recess, and the electrode and the conductor wiring are arranged in the recess. A semiconductor device characterized in that the recessed portion is filled with a sealant.
半導体装置。(2) The semiconductor device according to claim 1, wherein a through hole is provided in the concave portion of the rigid container.
１記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the side wall of the concave portion of the rigid container has a slope.
互いに隣接した導体配線層相互の間に溝部を有する請求
項１記載の半導体装置。(4) A conductive wiring layer formed on the surface of the convex part around the concave part,
2. The semiconductor device according to claim 1, further comprising a groove between adjacent conductor wiring layers.
切り欠き部または表示を備えた請求項１記載の半導体装
置。(5) The semiconductor device according to claim 1, wherein the container or the sealing portion is provided with a recess, a protrusion, a notch, or a display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241350A JP2553665B2 (en) | 1988-09-27 | 1988-09-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241350A JP2553665B2 (en) | 1988-09-27 | 1988-09-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0289348A true JPH0289348A (en) | 1990-03-29 |
| JP2553665B2 JP2553665B2 (en) | 1996-11-13 |
Family
ID=17072990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63241350A Expired - Lifetime JP2553665B2 (en) | 1988-09-27 | 1988-09-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2553665B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08306721A (en) * | 1995-04-27 | 1996-11-22 | Nec Corp | Semiconductor device and its manufacture |
| KR100447226B1 (en) * | 2001-10-24 | 2004-09-04 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package contained chip |
| US6861737B1 (en) * | 1996-12-30 | 2005-03-01 | Samsung Electronics Co., Ltd. | Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5481454U (en) * | 1977-11-19 | 1979-06-09 | ||
| JPS57178449U (en) * | 1981-05-06 | 1982-11-11 | ||
| JPS60216571A (en) * | 1984-04-11 | 1985-10-30 | Mitsubishi Electric Corp | Semiconductor device |
| JPS619849U (en) * | 1984-06-25 | 1986-01-21 | カシオ計算機株式会社 | circuit board |
-
1988
- 1988-09-27 JP JP63241350A patent/JP2553665B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5481454U (en) * | 1977-11-19 | 1979-06-09 | ||
| JPS57178449U (en) * | 1981-05-06 | 1982-11-11 | ||
| JPS60216571A (en) * | 1984-04-11 | 1985-10-30 | Mitsubishi Electric Corp | Semiconductor device |
| JPS619849U (en) * | 1984-06-25 | 1986-01-21 | カシオ計算機株式会社 | circuit board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08306721A (en) * | 1995-04-27 | 1996-11-22 | Nec Corp | Semiconductor device and its manufacture |
| US6861737B1 (en) * | 1996-12-30 | 2005-03-01 | Samsung Electronics Co., Ltd. | Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same |
| KR100447226B1 (en) * | 2001-10-24 | 2004-09-04 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package contained chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2553665B2 (en) | 1996-11-13 |
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