JPH0287718A - Logic circuit - Google Patents

Abstract

PURPOSE:To constitute a logic circuit for a dynamic circuit receiving a clock pulse as a control signal with a few component number by connecting 1st complementary transistor(TR) circuit and 2nd and 3rd complementary TR circuits whose gate receives an input signal and the clock signal respectively in a specific way. CONSTITUTION:A gate of complementary TRs Tp1, Tn1 in series connection between a power supply Vcc and ground is controlled by an input signal I0 and the signal I0 is fed to the 2nd and 3rd complementary TR circuits comprising TR Tp0, Tn0 and TR Tp2, Tn2 connecting to the power supply Vcc whose gate is controlled by a clock pulse phi. When the pulse phi is at an L level, outputs O0, O'0 of the common drain of the 2nd and 3rd circuits go to H, while the pulse phi is at n, the outputs O0,O'0 go to H or L in response to the signal I0. The logic circuit for the dynamic circuit using the clock pulse as the control signal is constituted with fewer component number in the use of the circuit in comparison with employing an inverter or a NAND gate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit, and particularly to a logic circuit used in a dynamic circuit using a clock pulse as a control signal.

[Conventional technology]

Next, a conventional logic circuit will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing an example of a conventional logic circuit.

In the logic circuit shown in FIG. 3, when the clock pulse φ is at a low level, all output signals Ooo to 050 are at a high level, and when the clock pulse φ is at a high level, output signals 000 to 05o are input signals. . This corresponds to the logical operation result of ~I2o.

FIG. 4 is a detailed circuit diagram of the inverter circuit a, NAND circuits S and C shown in FIG.

When the clock pulse φ is at low level, the P-channel transistors Tp2o and Tp4o are turned on, and the N
Since the channel transistors Tn2(1, Tn40 are in the off state), the output signals Ooo, O+.

are transistors Tp2o, Tp4 . It is pulled up to the power supply potential and becomes high level.

When clock pulse φ is at high level, transistor T
p2o, Tp4. turns off and transistor 'f
' n 20 and T n 4o are turned on.

Here, when the input signal I00 is at a low level, the transistor T p ,o is in an on state and the transistor Tn,0 is in an off state, so that the output signal 010 is at a high level. Furthermore, since the input signal I00 is at a low level, the transistor T p oo is turned on, and the transistor T noo
is in the off state, so the point A is the transistor T p o
It is pulled up to the power supply potential through o and becomes high level. As a result, the transistor Tp whose gate input is the point A,
o is in the off state, and transistor T n 1 (, is in the on state, so the output signal 000 is the transistor Tnl O
Since it is pulled to the ground potential through +Tn 20, it becomes low level.

Next, when the input signal I00 is at low level, the transistors T p g□ to T p 4o, T n H-T n
4. ), the output signal O
60 is pulled up to the power supply potential through the transistor TPto and becomes high level, while the output signal 010 is output from the transistor Tn3. ) to T n 40 and is grounded to a low level.

[Problem to be solved by the invention]

The conventional logic circuit described above has a drawback of having a large number of elements.

[Means to solve the problem]

In the logic circuit of the present invention, an input signal is supplied to a common gate, the source of one conductivity type MOS transistor is connected to the first power supply bus, and the other conductivity type MOS transistor is connected to the second power supply bus. (B) the input signal is supplied to the source of the MOS transistor of the other conductivity type, the clock pulse signal is supplied to the common gate, and the source of the MOS transistor of the first conductivity type is connected to the first complementary circuit; a second complementary circuit to which the sources of the transistors are connected and the first output signal is taken out from the common drain; (C) the sources of MOS transistors of other conductivity types are connected to the common drain of the first complementary circuit; a third complementary circuit in which a clock pulse signal is supplied to a common gate, a source of a one-conductivity type MOS transistor is connected to a first power supply bus, and a second output signal is taken out from a common drain; be done.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The logic circuit shown in Fig. 1 is as follows: (^) Input signal ■. is supplied to the common gate, the source of the P-channel MOS transistor is connected to the first power supply bus (Vcc), and the source of the N-channel MOS transistor is connected to the second power supply bus (GND). circuit, <8) Input signal Io is N-channel MOS
A second transistor is supplied to the source of the transistor, a clock pulse signal φ is supplied to the common gate, the source of the P-channel MOS transistor is connected to the power supply bus (Vcc), and the first output signal Oo is extracted from the common drain. (C) a source of a transistor of a different conductivity type is connected to the common train of the first complementary circuit;
The clock pulse signal φ is supplied to the common gate, the source of the P-channel MOS transistor is connected to the power supply bus (Vcc), and the second output signal O-o is supplied from the common drain.
A third complementary circuit from which is extracted.

When clock pulse φ is low level, transistor T
PO, TP2 are turned on, transistors TnO,
Since Tn2 is turned off, the output signals 0o, 0-, become high level (1).

When clock pulse φ is at high level, transistor T
Po, Tp2 are turned off, and transistor Tn(
,, Tn2 is turned on. At this time, input signal 1.
If is at a low level, the output signal Oo is also at a low level, and the output signal O-8 is at a high level (21).

When the clock pulse φ is at a high level, the input signal I is input.

If is at a high level, the output signal 0° also becomes a high level (2), and the output signal o-o becomes a low level.

However, when the input signal 1. is transmitted to the output side via the transistors Tn(1, Tn2), that is, the high level (2) is lowered by the N-channel MOS transistor gate threshold voltage, but due to logic operation. is not a problem.

FIG. 2 is a circuit diagram showing an example of the use of the present invention, in which input signals Io to Io are used. This shows a decoder that can support this.

The number of elements used is 60% of the conventional number.

〔Effect of the invention〕

The logic circuit of the present invention has the advantage that the number of required elements can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a circuit diagram showing an example of the conventional logic circuit, and FIG. 4 is a detailed circuit diagram of each functional element shown in FIG. 3. T po ~ T P 4...P channel MOS
Transistor, TnO to Tn4...N-channel MOS transistor, 1. ...Input signal, O
o~0-0...Output signal, φ...Clock pulse signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] (A) An input signal is supplied to a common gate, a source of a one-conductivity type MOS transistor is connected to a first power supply bus,
a first complementary circuit in which sources of MOS transistors of other conductivity types are connected to a second power supply bus; (B) the input signal is supplied to the sources of MOS transistors of other conductivity types, and a clock pulse signal is supplied to a common gate; a second complementary circuit in which the source of the one-conductivity type MOS transistor is connected to the first power supply bus, and the first output signal is taken out from the common drain; (C) a common drain of the first complementary circuit; The sources of the MOS transistors of the other conductivity type are connected to the common gate, the clock pulse signal is supplied to the common gate, the sources of the MOS transistors of the one conductivity type are connected to the first power supply bus, and a second output signal is taken out from the common drain. A logic circuit comprising: a third complementary circuit.