JPH0287673A - Insulating gate type semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine gate without being restricted by photolithography and realize making of a MOS transistor having high current gain and then, improve a resistance to hot electrons by forming gate electrodes at both sidewall parts of an insulating coat which is formed on a gate region, thereby making up a structure wherein a semiconductor layer directly below the coat has the same conductivity type as those of source and drain regions, and the other semiconductor layer directly below the gate electrodes has the conductivity type contrary to those of the source and drain regions. CONSTITUTION:After forming a field insulating film 2 and a gate insulating film 3 on a P-type silicon substrate 1, an insulating film 7 is formed on a gate region. Gate electrodes 4 are formed on both side walls of the insulating film 7 and source and drain regions 8 and 9 are formed in terms of a self-alignment system to the gate region. Although a channel region directly below the gate electrodes of the sidewall parts has a P-type semiconductor layer, an N-type layer 6 is formed on the channel region between source and drain regions that is other than the above channel region below the gate electrodes.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an insulated gate semiconductor device.

[Conventional technology]

Conventionally, an enhancement type MOS transistor used in an insulated gate type semiconductor device has a field insulating film 2, a gate insulating film 3, and a gate electrode 4 formed on the surface of a P-type silicon substrate l, as shown in FIG. , N-type source/drain regions 8 and 9 are formed in self-alignment with the gate electrode 4.

[Problem to be solved by the invention]

However, with the miniaturization of element dimensions, the following problems arise in the conventional structure and manufacturing method described above. First, regarding patterning of gate electrodes, photolithography is capable of forming patterns of sub-micron size or smaller with high accuracy.

Furthermore, in the conventional structure, the channel through which the drain current flows is formed only on the solid surface of the semiconductor v plate under the gate insulating film 3, so that the channel resistance when the transistor is turned on cannot be made very large.

Therefore, it is only possible to obtain a large drain current.

Furthermore, as the internal electric field increases due to miniaturization, deterioration of device characteristics due to hot electrons becomes a problem.

[Means to solve the problem]

The present invention provides an insulated gate type semiconductor device having a gate electrode formed in a predetermined region on the surface of a semiconductor substrate via a gate insulating film, and a source/drain region formed in a self-aligned manner with respect to the gate electrode. υ, the gate electrode is formed on both side walls of a film formed in the gate region and whose surface is at least an insulator, and the semiconductor layer directly under the film is of the same conductivity type as the source/drain region, and the gate electrode is of the same conductivity type as the source/drain region. The semiconductor layer directly under the electrode is configured to be a semiconductor layer of a conductivity type opposite to that of the source/drain regions.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

After forming a field insulating film 2 and a gate insulating film 3 on a P-type silicon substrate 1, an insulating film 7 is formed on the gate region. Gate electrodes 4 are formed on both side walls of this insulating film 7, and source/drain regions 8,
form 9. The channel region directly under the gate electrode 4 on this side wall portion is a P-type semiconductor I-, but an N-type layer 6 is formed in the channel region between the source and drain other than this region.

Next, the manufacturing method of this embodiment will be explained.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 2(a), a P-type silicon substrate l
A field insulating film 2 is formed on the element isolation chain acid by a normal selective oxidation method, and a gate insulating film 3 is grown on the active region.
is deposited by vapor phase growth. Using photolithography technology, a pattern of the resist film 5 is formed that covers the area other than the area where the gate electrode is to be formed. Although not shown, arbitrary impurities may be introduced into the silicon substrate surface of the active region by ion implantation in order to adjust the threshold voltage of the transistor. Furthermore, a heavily doped diffusion layer having the same conductivity type as the substrate may be placed directly under the field insulating film 2 in order to suppress parasitic channels.

Next, as shown in FIG. 2(b), the polycrystalline silicon film 4a is selectively etched by reactive ion etching using the resist + film 5 as a mask, and the recesses 12 formed are self-aligned. For example, the N-type layer 6 is formed by ion-implanting arsenic at a dose of about ilocm to lQcm. Next, the insulating film 7 is deposited by low pressure CVD or the like so as to fill the inside of the recess 12.

Next, as shown in FIG. 2C, the insulating film 7 on the substrate is selectively etched so that the insulating film remains only in the recess 12.

Next, as shown in FIG. 2(d), the polycrystalline silicon film 4a sprayed on the silicon substrate is selectively anisotropically etched so that it remains only on the sidewalls of the insulating film 7, and this is etched at the gate. It is assumed to be electrode 4.

Finally, arsenic is ion-implanted into the gate region and the field insulating film in a self-aligned manner at a degree of, for example, 1Q cm.
By forming the source/drain regions 8 and 9, the first
Obtain the structure shown in the figure. Thereafter, wiring and the like are formed according to normal steps to construct an insulated gate semiconductor device.

FIG. 3 is a cross-sectional view of a second embodiment of the present invention. are formed, and source/drain regions 8.9 are formed in self-alignment with the gate region. Although the gate electrode 4 is made of silicide in this embodiment, it can also be made of polycrystalline silicon as in the first embodiment.

Next, the manufacturing method of this example will be explained.

FIGS. 4(a) to 4(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

First, as shown in FIG. 4(a), a P-type silicon substrate l
After forming a field insulating film 2 thereon, a gate insulating film 3 is formed in the active region and, for example, phosphorus is dosed [10 cm
Ion implantation is performed at −10 cm to form an N-type layer 6. Then, polycrystalline silicon film 4a is deposited to a thickness of about 200 to 800 nm by vapor phase epitaxy, and a pattern of resist film 5 covering the gate region is formed using photolithography.

Next, as shown in FIG. 4(b), the polycrystalline silicon film 4a is anisotropically etched using the resist film 5 as a mask, and the formed polycrystalline silicon film 4b and field insulating film 2 are
For example, the dose of boron is 1011012C in a self-aligned manner.
Ion implantation is performed at about 10<14 >cm<-2> to convert the surface of the substrate other than directly under the polycrystalline silicon 714b into a P-type semiconductor layer.

Next, as shown in FIG. 4C, an insulating film 10 is formed on the surface of the polycrystalline silicon film 4b by thermal oxidation, and then a silicide 11 such as tungsten silicide is deposited.

Next, as shown in FIG. 4(d), the silicide film 11 is selectively anisotropically etched so that the silicide film 11 remains only on the side walls of the polycrystalline silicon layer 4b to form the gate electrode 4.

Finally, for example, arsenic is dosed to25 in a self-aligned manner with respect to the formed gate region and field insulating film.
Ion implantation is performed at approximately Cm-2 to form source/drain regions 8.
, 9 to obtain the structure shown in FIG.

Although the embodiments of the present invention have been described above with respect to N-channel MOS transistors, it goes without saying that they can be similarly implemented in the case of P-channel MUS transistors as well.

〔Effect of the invention〕

As explained above, the present invention enables the formation of fine gates without the constraints of 7-to-trine graphs by forming gate electrodes on the sidewalls of the film formed in the gate region.
In addition, by arranging a semiconductor layer of the same conductivity type as the substrate in the channel region in a self-aligned manner, the channel resistance is low.
That is, a MOS transistor with high IT current gain can be realized.

Furthermore, by providing a diffusion layer of the same conductivity type as the source and drain between the drain and the source, the voltage between the source and drain is distributed between the channels on the drain side and the source side, the electric field is relaxed, and hot electrons are This has the effect of improving resistance to

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
-(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention, FIG. 3 is a cross-sectional view of the second embodiment of the present invention, and FIG. (a)-(d)
5 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention, and FIG.
FIG. 2 is a cross-sectional view of an OS transistor. 1... Pi silicon J-con board, 2... Field insulating film, 3... Gate insulating film, 4, 4
a, 4b...polycrystalline silicon film, 6...
・N layer, 7...Insulating film, 8゛°°°゛N type source region, 9...N type drain region, 10...
... Insulating film, 11... Silicide film. Agent: Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In an insulated gate type semiconductor device having a gate electrode formed in a predetermined region on the surface of a semiconductor substrate via a gate insulating film, and a source/drain region formed in self-alignment with the gate electrode, the gate The electrodes are formed on both side walls of a film formed in the gate region and whose surface is at least an insulator, the semiconductor layer directly under the film is of the same conductivity type as the source/drain region, and the semiconductor layer directly under the gate electrode is of the same conductivity type as the source/drain region. An insulated gate semiconductor device characterized in that the source/drain region is a semiconductor layer of a conductivity type opposite to that of the source/drain region.