JPH0287211A - Constant voltage circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption and to exactly design an arbitrary voltage by providing a means to set a resistance load in the output side of a current mirror circuit smaller than a resistance load in an input side, and to switch the bias voltage of the current mirror circuit. CONSTITUTION:Means S1-S4 are provided to set a resistance load R1 in a current source side smaller than a resistance load R2 in a bias circuit side and to switch the bias of the current mirror circuit. At the time of normal operation, the switches S1 and S2 are turned on and the S3 and S4 are tuned off. At the time saving power not to need a constant voltage output, the S1 and S2 are turned off and the S3 and S4 are turned on. Thus, M1 and M2 are biases in an interruption area and a normal current does not flow. Thus, the energy consumption can be reduced and further, when the gm of a transistor in the current mirror is enlarged, the arbitrary constant voltage output can be designed by the value of R2/R1(R1>>R2).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage circuit, and particularly to a constant voltage circuit built in a MOS-LSI.

[Conventional technology]

Conventionally, when creating a constant voltage using a resistor divider circuit inside an IC, from the point of view of power consumption, if a resistance value of IOK to 100I (Ω) is used, the steady current can be kept low, but the transient current of the power supply voltage Since the resistor is easily affected by fluctuations and the internal area of the chip is large, a resistor of IKΩ to 10Ω is often used.

In this case, when there is no need to obtain a reference voltage, it is desirable to cut off the steady current flowing through this resistor in order to save power. FIG. 4 shows an example of a circuit with a cutoff function.

Transistor TI in the same figure.

T2 is an N channel with the same on-resistance.

It is a P-channel transistor, and a bias is applied to turn it on during normal use, but as mentioned above, if the transistor's on-resistance is high, it becomes vulnerable to transient fluctuations in the power supply voltage, so the on-resistance is designed to be as small as possible. It was used as

[Problem to be solved by the invention]

The resistor divider constant voltage circuit with the current cutoff function described above is
The on-resistance values of the two transistors are equal, and the resistance R,
= R2, V
A midpoint voltage between c c and GND is generated, but if any voltage other than the midpoint is desired, including the on-resistance value,
need to be designed.

In the MOS process, the value of on-resistance varies because it depends on VT, and has the drawback that accurate design cannot be performed.

[Means to solve the problem]

The constant voltage circuit of the present invention has an equal mutual conductance M
In a constant voltage circuit that includes a current mirror circuit using an OS transistor and outputs a voltage drop across a resistive load on the current source side, the resistive load on the current source side is set smaller than the resistive load on the bias circuit side, and the It is constructed by providing means for switching the bias of the current mirror circuit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a constant voltage circuit for explaining one embodiment of the present invention. In the figure, the transistor Ml.

M2 operates in the saturation region, and the same current ■ in load resistors R1 and R2. When R2 flows, the voltage output corresponding to the voltage drop due to R2 is as shown in the following equation.

(However, VD!1 is the drain-source voltage of M1.) In the above equation, vast changes due to variations in vT due to process factors, but by setting R,:>R2, the influence of variations in VA can be reduced.

During normal operation, this circuit turns on the switch 31.82 and performs S3. Turn off S4. During power saving when constant voltage output is not required, SL and 82 are turned off, and S3 and 8 are turned off.
4 is turned on, Ml and M2 are biased to the cutoff region, and no steady current flows.

FIG. 2 shows switches S1 and S2 in FIG.
O8) This is an embodiment in which transistors S3 and S4 are constructed of P-MOS transistors. During normal operation, this circuit operates as follows: Sl, S2, 33 . A high voltage of Va (> VD31 + VT) is applied to each MOS transfer gate of S4 to turn on Sl and S2 and turn off S3 and S4. In this state, the Karen mirror circuit operates and outputs a constant voltage VR, as shown in equation (1). However, each MO
The gate voltage of S transistors S1 to S4 is V. <Vo
In the state of s++VT, these are biased to the saturation region and the transmitted output increases only to Vo-V, so it is necessary to apply the gate voltage to the vicinity of the power supply voltage. Conversely, transistors Sl and S2 are turned off, S3 . S4
By turning on the power save mode, no current flows through the current mirror circuit.

Also, the resistance values of R1 and R2 are determined by considering the internal area of the chip.
It is necessary to set K to l0I (Ω), but in that case, the gm (mutual conductance) of the transistors M1 and M2 may be designed to be large to increase the current flow rate and ensure the voltage drop due to R2.

According to this embodiment, transistors S1 and 82 are turned off,
By turning on S3 and 84, it becomes a power mold, reducing power consumption and further increasing R2/R+ (R+
> R2) allows the constant voltage output to be set.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The difference in configuration from the first embodiment is that the current mirror circuit has a cascode configuration in which transistors M3 and M4 are added. When the drain voltage of a MOS transistor is increased beyond the pinch-off voltage, the effective channel length decreases and the MOS transistor no longer exhibits clear saturation characteristics. In this case, the drain current depends on the drain voltage, so the two currents in the mirror circuit no longer match.

Therefore, the current mirror circuit was configured in a cascode configuration as in this embodiment to reduce the influence of the channel length modulation effect, and a configuration suitable for setting a more accurate constant voltage value was adopted.

〔Effect of the invention〕

As explained above, in the present invention, the bias voltage of the current mirror circuit of the resistive load is switched by the switch circuit,
By cutting off the steady current flowing through the current mirror circuit during standby mode, power consumption can be reduced.Furthermore, by increasing the gm of the current mirror transistor, any value can be achieved depending on the value of R2/R1 (R+ > R2). This has the effect of allowing constant voltage output to be designed.

[Brief explanation of drawings]

Figure 1 is a reference voltage circuit diagram for explaining the present invention, Figure 2 is a reference voltage circuit diagram for explaining the present invention.
The figure is a circuit diagram for explaining the first embodiment of the present invention, FIG. 3 is a circuit diagram for explaining the second embodiment of the present invention,
FIG. 4 is a configuration diagram in which a current cutoff switch is attached to a conventional reference voltage source. Sl to S4...MOS) transistor, Ml to M4...MOS) transistor, R1, R2...
·····resistance. Agent: Susumu Uchihara, patent attorney Figure 4

Claims (1)

[Claims] In a constant voltage circuit including a current mirror circuit using MOS transistors having equal mutual conductance, a means for setting a resistive load on the output side of the current mirror circuit to be smaller than a resistive load on the input side and switching a bias voltage of the current mirror circuit. A constant voltage circuit characterized by the following.