JPH07170158A - Voltage controlled oscillation circuit device - Google Patents
Voltage controlled oscillation circuit deviceInfo
- Publication number
- JPH07170158A JPH07170158A JP31481493A JP31481493A JPH07170158A JP H07170158 A JPH07170158 A JP H07170158A JP 31481493 A JP31481493 A JP 31481493A JP 31481493 A JP31481493 A JP 31481493A JP H07170158 A JPH07170158 A JP H07170158A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate
- pmosfet
- nmosfet
- series connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、奇数個のインバータが
リング状に接続された発振回路に係り、特に、これらの
インバータの電流を制御する電流制御回路を備えた電圧
制御型発振回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit in which an odd number of inverters are connected in a ring shape, and more particularly to a voltage control type oscillator circuit device having a current control circuit for controlling the current of these inverters. .
【０００２】[0002]
【従来の技術】図３はこの種の従来の電圧制御型発振回
路装置の構成を示す回路図であり、発振回路１及び電流
制御回路２を備えている。このうち、発振回路１は、構
成が同一の奇数個のインバータ10がリング状に接続され
たものであり、インバータ10は、ＰＭＯＳＦＥＴ11，12
及びＮＭＯＳＦＥＴ13，14の直列接続回路で構成されて
いる。すなわち、ＰＭＯＳＦＥＴ11とＮＭＯＳＦＥＴ13
とは、ドレインどうしが接続されると共にゲートどうし
も接続され、かつ、ＰＭＯＳＦＥＴ11のソースが電流制
御用のＰＭＯＳＦＥＴ12を介して高電位電源Ｖddに接続
され、ＮＭＯＳＦＥＴ13のソースが電流制御用のＮＭＯ
ＳＦＥＴ14を介して接地電位にある低電位電源Ｖssに接
続されている。そして、ＰＭＯＳＦＥＴ11及びＮＭＯＳ
ＦＥＴ13のゲートどうしの接続点がインバータの入力端
となり、ドレインどうしの接続点がインバータの出力端
となっている。2. Description of the Related Art FIG. 3 is a circuit diagram showing the configuration of a conventional voltage-controlled oscillation circuit device of this type, which includes an oscillation circuit 1 and a current control circuit 2. Of these, the oscillator circuit 1 is configured by connecting an odd number of inverters 10 having the same configuration in a ring shape, and the inverter 10 includes PMOSFETs 11 and 12
And NMOSFETs 13 and 14 are connected in series. That is, PMOSFET 11 and NMOSFET 13
Means that the drains are connected to each other and the gates are connected to each other, the source of the PMOSFET 11 is connected to the high potential power supply V dd via the PMOSFET 12 for current control, and the source of the NMOSFET 13 is NMO for current control.
It is connected to the low potential power source V ss at the ground potential via the SFET 14. And PMOSFET 11 and NMOS
The connection point between the gates of the FET 13 is the input end of the inverter, and the connection point between the drains is the output end of the inverter.
【０００３】一方、電流制御回路２は、ＰＭＯＳＦＥＴ
21及びＮＭＯＳＦＥＴ22を直列接続してなる第１の直列
接続回路と、ＰＭＯＳＦＥＴ23及びＮＭＯＳＦＥＴ24を
直列接続してなる第２の直列接続回路とで構成されてい
る。この場合、ＰＭＯＳＦＥＴ21のゲートはそのドレイ
ンに接続されると共に、ＮＭＯＳＦＥＴ22とはドレイン
どうしが接続され、かつ、ＰＭＯＳＦＥＴ21のソースが
高電位電源Ｖddに接続され、ＮＭＯＳＦＥＴ22のソース
が低電位電源Ｖssに接続されている。また、ＮＭＯＳＦ
ＥＴ24のゲートはそのドレインに接続されると共に、Ｐ
ＭＯＳＦＥＴ23とはドレインどうしが接続され、かつ、
ＮＭＯＳＦＥＴ24のソースが低電位電源Ｖssに接続さ
れ、ＰＭＯＳＦＥＴ23のソースが高電位電源Ｖddに接続
されている。On the other hand, the current control circuit 2 is a PMOSFET.
The first series connection circuit is formed by connecting 21 and NMOSFET 22 in series, and the second series connection circuit is formed by connecting PMOSFET 23 and NMOSFET 24 in series. In this case, the gate of the PMOSFET 21 is connected to its drain, the drains of the PMOSFET 21 are connected to each other, the source of the PMOSFET 21 is connected to the high potential power supply V dd, and the source of the NMOSFET 22 is connected to the low potential power supply V ss . Has been done. Also, NMOSF
The gate of ET24 is connected to its drain and P
The drains are connected to the MOSFET 23, and
The source of the NMOSFET 24 is connected to the low potential power supply V ss, and the source of the PMOSFET 23 is connected to the high potential power supply V dd .
【０００４】そして、ＰＭＯＳＦＥＴ21のドレイン、Ｐ
ＭＯＳＦＥＴ23のゲート、及び各インバータ10のＰＭＯ
ＳＦＥＴ12のゲートが接続され、かつ、ＮＭＯＳＦＥＴ
24のドレイン及び各インバータ10のＰＭＯＳＦＥＴ12の
ゲートが接続されており、ＮＭＯＳＦＥＴ22のゲートに
制御電圧ＶCNT を印加する構成になっている。The drain of the PMOSFET 21, P,
Gate of MOSFET 23 and PMO of each inverter 10
The gate of SFET12 is connected and NMOSFET
The drain of 24 and the gate of the PMOSFET 12 of each inverter 10 are connected, and the control voltage V CNT is applied to the gate of the NMOSFET 22.
【０００５】図３において、発振回路１を構成するイン
バータ10のＰＭＯＳＦＥＴ12及びＮＭＯＳＦＥＴ14のゲ
ートにそれぞれ電圧信号が印加されたとする。そして、
ＰＭＯＳＦＥＴ11及びＮＭＯＳＦＥＴ13のゲートどうし
の接続点、すなわち、入力端に信号が加えられると、Ｐ
ＭＯＳＦＥＴ11，12を流れる電流ＩP 及びＮＭＯＳＦＥ
Ｔ13，14を流れる電流ＩN に応じた時間だけ遅延した信
号がＰＭＯＳＦＥＴ11及びＮＭＯＳＦＥＴ13のドレイン
どうしの接続点、すなわち、出力端に発生する。リング
状に接続された奇数個のインバータ10に順次これらの信
号遅延動作を行わしめることによって発振回路１は発振
する。ここで、ＰＭＯＳＦＥＴ12のゲート及びＮＭＯＳ
ＦＥＴ14のゲートには、増減傾向が互いに逆の対電圧が
印加され、例えば、ＰＭＯＳＦＥＴ12のゲート電圧を増
大させると共にＮＭＯＳＦＥＴ14のゲート電圧を減少さ
せたとすると、各インバータの遅延時間は大きくなり、
発振周波数は低下する。反対に、ＰＭＯＳＦＥＴ12のゲ
ート電圧を減少させると共にＮＭＯＳＦＥＴ14のゲート
電圧を増大させたとすると、各インバータの遅延時間は
小さくなり、発振周波数は上昇する。In FIG. 3, it is assumed that voltage signals are respectively applied to the gates of the PMOSFET 12 and the NMOSFET 14 of the inverter 10 which constitutes the oscillation circuit 1. And
When a signal is applied to the connection point between the gates of PMOSFET 11 and NMOSFET 13, that is, the input end, P
Current I P flowing through MOSFETs 11 and 12 and NMOS FE
A signal delayed by a time corresponding to the current I N flowing through T13, 14 is generated at the connection point between the drains of the PMOSFET 11 and the NMOSFET 13, that is, the output end. The oscillator circuit 1 oscillates by sequentially performing these signal delay operations on the odd number of inverters 10 connected in a ring shape. Here, the gate of the PMOSFET 12 and the NMOS
To the gate of the FET 14, counter voltages whose increasing and decreasing tendencies are opposite to each other are applied. For example, if the gate voltage of the PMOSFET 12 is increased and the gate voltage of the NMOSFET 14 is decreased, the delay time of each inverter increases,
The oscillation frequency decreases. On the contrary, if the gate voltage of the PMOSFET 12 is decreased and the gate voltage of the NMOSFET 14 is increased, the delay time of each inverter becomes small and the oscillation frequency rises.
【０００６】電流制御回路２はこれらの対電圧を供給す
るもので、ＰＭＯＳＦＥＴ21及びＮＭＯＳＦＥＴ22でな
る第１の直列接続回路と、ＰＭＯＳＦＥＴ23及びＮＭＯ
ＳＦＥＴ24でなる第２の直列接続回路とは周知のカレン
トミラー回路を構成している。そこで、ＮＭＯＳＦＥＴ
22のゲートに制御電圧ＶCNT を印加すると、その大きさ
に応じた電流がＰＭＯＳＦＥＴ21及びＮＭＯＳＦＥＴ22
の直列接続回路に流れると共に、これらのＭＯＳＦＥＴ
のドレインどうしの接続点電圧がＰＭＯＳＦＥＴ23のゲ
ートに印加され、その大きさに応じた電流がＰＭＯＳＦ
ＥＴ23及びＮＭＯＳＦＥＴ24の直列接続回路に流れる。The current control circuit 2 supplies these counter voltages, and includes a first series connection circuit composed of PMOSFET 21 and NMOSFET 22, and PMOSFET 23 and NMO.
The second series connection circuit composed of SFET24 constitutes a well-known current mirror circuit. Therefore, NMOSFET
When the control voltage V CNT is applied to the gate of 22, the current corresponding to the magnitude of the control voltage V CNT is generated in the PMOSFET 21 and the NMOSFET 22.
These MOSFETs flow in the series connection circuit of
The voltage at the connection point between the drains of the PMOSFET 23 is applied to the gate of the PMOSFET 23, and a current corresponding to the magnitude is applied to the PMOSF.
It flows in the series connection circuit of ET23 and NMOSFET24.
【０００７】従って、制御電圧ＶCNT を増大させたとす
ればインバータ10を構成するＰＭＯＳＦＥＴ12のゲート
電圧は下降すると共に、ＮＭＯＳＦＥＴ14のゲート電圧
は上昇し、発振回路１の発振周波数は高くなる。反対
に、制御電圧ＶCNT を減少させたとすればインバータ10
を構成するＰＭＯＳＦＥＴ12のゲート電圧は上昇すると
共に、ＮＭＯＳＦＥＴ14のゲート電圧は下降し、発振回
路１の発振周波数は低くなる。Therefore, if the control voltage V CNT is increased, the gate voltage of the PMOSFET 12 constituting the inverter 10 is lowered, the gate voltage of the NMOSFET 14 is raised, and the oscillation frequency of the oscillation circuit 1 is increased. On the contrary, if the control voltage V CNT is reduced, the inverter 10
, The gate voltage of the NMOSFET 14 decreases, and the oscillation frequency of the oscillation circuit 1 decreases.
【０００８】[0008]
【発明が解決しようとする課題】上述した従来の電圧制
御型発振回路装置にあっては、電流制御回路２を構成す
るＮＭＯＳＦＥＴ22のゲートに一定の制御電圧ＶCNT を
印加したとしても、インバータ10の電流を制御する対電
圧が、例えば、温度の変化、ＭＯＳＦＥＴを接続するチ
ャネル長のバラツキ、閾値電圧ＶTHのバラツキ、及び高
電位電源Ｖddの電圧のバラツキによって異なり、発振回
路１のゲイン特性に違いがでてしまう。このため、製品
毎に発振周波数が違ったり、温度や電源電圧の変動によ
って発振周波数が変化するという問題があった。In the above-mentioned conventional voltage control type oscillation circuit device, even if a constant control voltage V CNT is applied to the gate of the NMOSFET 22 constituting the current control circuit 2, the inverter 10 of the inverter 10 is controlled. The voltage for controlling the current varies depending on, for example, a change in temperature, a variation in channel length for connecting MOSFETs, a variation in threshold voltage V TH , and a variation in voltage of the high-potential power supply V dd. The difference will come out. For this reason, there are problems that the oscillation frequency differs for each product and that the oscillation frequency changes due to changes in temperature and power supply voltage.
【０００９】また、電流制御回路２の各直列接続回路に
流れる電流は、制御電圧ＶCNT の約２乗に比例するた
め、制御電圧ＶCNT と発振回路１の発振周波数とが非線
形になる。このため、この電圧制御型発振回路装置をＰ
ＬＬ(PHASE-locked loop) に適用した場合、発振回路１
の動作点によってそのゲイン特性が異なってしまい、Ｐ
ＬＬのループ特性が不安定になるという問題もあった。Further, the current flowing in each of the series connection circuit of the current control circuit 2 is proportional to approximately the square of the control voltage V CNT, the control voltage V CNT and the oscillation frequency of the oscillation circuit 1 is non-linear. For this reason, this voltage control type oscillation circuit device is
When applied to LL (PHASE-locked loop), oscillation circuit 1
The gain characteristic varies depending on the operating point of
There is also a problem that the loop characteristic of LL becomes unstable.
【００１０】本発明は上記の問題点を解決するためにな
されたもので、製造上のバラツキ、温度変化、及び電源
電圧変動等があっても、発振周波数のバラツキを抑え、
かつ、発振回路のゲイン特性を線形にすることによって
これを利用したＰＬＬを安定に動作させることのできる
電圧制御型発振回路装置を得ることを目的とする。The present invention has been made to solve the above problems, and suppresses variations in oscillation frequency even if there are variations in manufacturing, temperature changes, power supply voltage variations, etc.
Moreover, it is an object of the present invention to obtain a voltage control type oscillation circuit device capable of stably operating a PLL using the gain characteristic of the oscillation circuit by making it linear.
【００１１】[0011]
【課題を解決するための手段】請求項１に記載の電圧制
御型発振回路装置は、リング状に接続された奇数個のイ
ンバータを構成する電流制御用のＰＭＯＳＦＥＴ及びＮ
ＭＯＳＦＥＴの各ゲートに加える電圧を得るために、演
算増幅器と、ソースが高電位電源に接続され、ドレイン
が抵抗器を介して低電位電源に接続された第１の直列接
続回路と、ソースが高電位電源に接続されたＰＭＯＳＦ
ＥＴ及びソースが低電位電源に接続されたＮＭＯＳＦＥ
Ｔを含み、このうち、ＰＭＯＳＦＥＴのドレインがＮＭ
ＯＳＦＥＴのドレイン及びゲートに接続された第２の直
列接続回路とを有し、演算増幅器の出力端が第１及び第
２の直列接続回路の各ＰＭＯＳＦＥＴのゲート、並びに
各インバータの電流制御用ＰＭＯＳＦＥＴのゲートに接
続され、演算増幅器の非反転入力端子が第１の直列接続
回路のＰＭＯＳＦＥＴのドレインに接続され、第２の直
列接続回路のＮＭＯＳＦＥＴのドレインが各インバータ
の電流制御用ＮＭＯＳＦＥＴのゲートに接続された電流
制御回路を備える。According to a first aspect of the present invention, there is provided a voltage controlled oscillator circuit device, wherein a current control PMOSFET and N constituting an odd number of inverters connected in a ring shape.
To obtain a voltage to be applied to each gate of the MOSFET, an operational amplifier, a first series circuit in which the source is connected to the high potential power source and the drain is connected to the low potential power source through a resistor, and the source are high PMOSF connected to a potential power supply
NMOS FE with ET and source connected to low potential power supply
Including T, of which the drain of the PMOSFET is NM
A second series connection circuit connected to the drain and gate of the OSFET, and the output terminal of the operational amplifier is the gate of each PMOSFET of the first and second series connection circuits, and the current control PMOSFET of each inverter. Connected to the gate, the non-inverting input terminal of the operational amplifier is connected to the drain of the PMOSFET of the first series connection circuit, and the drain of the NMOSFET of the second series connection circuit is connected to the gate of the current control NMOSFET of each inverter. And a current control circuit.
【００１２】請求項２に記載の電圧制御型発振回路装置
は、リング状に接続された奇数個のインバータを構成す
る電流制御用のＰＭＯＳＦＥＴ及びＮＭＯＳＦＥＴの各
ゲートに加える電圧を得るために、演算増幅器と、ソー
スが低電位電源に接続され、ドレインが抵抗器を介して
高電位電源に接続された第１の直列接続回路と、ソース
が高電位電源に接続されたＰＭＯＳＦＥＴ及びソースが
低電位電源に接続されたＮＭＯＳＦＥＴを含み、これら
のＭＯＳＦＥＴのドレインどうしが接続された第２の直
列接続回路とを有し、演算増幅器の出力端が第１及び第
２の直列接続回路の各ＮＭＯＳＦＥＴのゲート、並びに
各インバータの電流制御用ＮＭＯＳＦＥＴのゲートに接
続され、演算増幅器の非反転入力端子が第１の直列接続
回路のＮＭＯＳＦＥＴのドレインに接続され、第２の直
列接続回路のＰＭＯＳＦＥＴのゲートが該ＰＭＯＳＦＥ
Ｔのゲート、及び各インバータの電流制御用ＰＭＯＳＦ
ＥＴのゲートに接続された電流制御回路を備える。According to another aspect of the voltage controlled oscillator circuit device of the present invention, an operational amplifier is provided in order to obtain a voltage to be applied to each gate of current controlling PMOSFETs and NMOSFETs constituting an odd number of inverters connected in a ring. And a first series connection circuit in which the source is connected to the low potential power source and the drain is connected to the high potential power source via a resistor, and the PMOSFET and the source in which the source is connected to the high potential power source are the low potential power source. A second series connection circuit including connected NMOSFETs, the drains of these MOSFETs being connected to each other, and the output terminal of the operational amplifier being the gate of each NMOSFET of the first and second series connection circuits, and The non-inverting input terminal of the operational amplifier connected to the gate of the current control NMOSFET of each inverter has the NMOSF of the first series connection circuit. Is connected to the drain of T, PMOSFET gate of the second series circuit is the PMOSFE
Gate of T and PMOSF for current control of each inverter
A current control circuit connected to the gate of ET is provided.
【００１３】[0013]
【作用】請求項１及び２に記載の電圧制御型発振回路装
置においては、電流制御回路を構成する第１及び第２の
直列接続回路の抵抗値をＲ、演算増幅器に加える制御電
圧をＶCNT とすると、各直列接続回路に流れる電流Ｉは
次式 Ｉ＝ＶCNT ／Ｒ …(1) によって決定され、製造上のバラツキ、温度変化、及び
電源電圧変動等に依存しない電流が流れると共に、各イ
ンバータにはこれに比例した電流が流れるため、発振周
波数のバラツキを抑えることができる。In the voltage controlled oscillator circuit device according to the present invention, the resistance value of the first and second series connection circuits constituting the current control circuit is R, and the control voltage applied to the operational amplifier is V CNT. Then, the current I flowing in each series connection circuit is determined by the following formula I = V CNT / R (1), and a current that does not depend on manufacturing variations, temperature changes, power supply voltage fluctuations, and the like flows, and Since a current proportional to this flows in the inverter, variations in oscillation frequency can be suppressed.
【００１４】また、各インバータに流れる電流は制御電
圧ＶCNT に比例するため、制御電圧ＶCNT に対する発振
周波数の線形化が可能となり、これを利用したＰＬＬを
安定に動作させることができる。Further, since currents flowing through the inverter is proportional to the control voltage V CNT, it is possible to linearize the oscillation frequency with respect to the control voltage V CNT, a PLL using the same can be operated stably.
【００１５】[0015]
【実施例】以下、本発明を図面に示す実施例によって詳
細に説明する。図１はこの発明の一実施例の構成を示す
回路図であり、電流制御回路２に代えて電流制御回路2A
を設けた点が従来装置と異なっている。電流制御回路2A
は、演算増幅器20、ＰＭＯＳＦＥＴ21、抵抗器25、ＰＭ
ＯＳＦＥＴ23及びＮＭＯＳＦＥＴ24によって構成されて
いる。このうち、ＰＭＯＳＦＥＴ21のソースは高電位電
源Ｖddに接続され、このＰＭＯＳＦＥＴ21のドレインに
は抵抗器25の一端が接続され、この抵抗器25の他端が低
電位電源Ｖssに接続されおり、これらが本発明の第１の
直列接続回路を形成している。また、ＰＭＯＳＦＥＴ23
のソースが高電位電源Ｖddに接続され、このＰＭＯＳＦ
ＥＴ23のドレインにＮＭＯＳＦＥＴ24のドレインとゲー
トとに接続され、このＮＭＯＳＦＥＴ24のソースが低電
位電源Ｖssに接続されており、これらが本発明の第２の
直列接続回路を形成している。そして、演算増幅器20の
出力端がＰＭＯＳＦＥＴ21及びＰＭＯＳＦＥＴ23の各ゲ
ートと、インバータ10を構成する電流制御用のＰＭＯＳ
ＦＥＴの各ゲートに接続され、演算増幅器20の非反転入
力端子（＋）がＰＭＯＳＦＥＴ21と抵抗器25との相互接
合点、すなわち、ＰＭＯＳＦＥＴ21のドレインに接続さ
れている。さらに、ＮＭＯＳＦＥＴ24のドレインがイン
バータ10を構成する電流制御用のＮＭＯＳＦＥＴ14の各
ゲートに接続されている。そして、演算増幅器20の反転
入力端子（−）に制御電圧ＶCNT を印加するようになっ
ている。The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. Instead of the current control circuit 2, a current control circuit 2A
Is different from the conventional device. Current control circuit 2A
Is an operational amplifier 20, PMOSFET 21, resistor 25, PM
It is composed of an OSFET 23 and an NMOSFET 24. Of these, the source of the PMOSFET 21 is connected to the high potential power supply V dd , one end of the resistor 25 is connected to the drain of the PMOSFET 21, and the other end of the resistor 25 is connected to the low potential power supply V ss. Form the first series connection circuit of the present invention. In addition, PMOSFET23
The source of is connected to the high potential power supply V dd ,
The drain of the ET23 is connected to the drain and gate of the NMOSFET 24, and the source of the NMOSFET 24 is connected to the low-potential power supply V ss , which form the second series connection circuit of the present invention. The output end of the operational amplifier 20 is a PMOS for current control which constitutes the inverter 10 and the gates of the PMOSFET 21 and PMOSFET 23.
The non-inverting input terminal (+) of the operational amplifier 20 is connected to each gate of the FET, and is connected to the mutual junction point of the PMOSFET 21 and the resistor 25, that is, the drain of the PMOSFET 21. Further, the drain of the NMOSFET 24 is connected to each gate of the NMOSFET 14 for current control which constitutes the inverter 10. Then, the control voltage V CNT is applied to the inverting input terminal (−) of the operational amplifier 20.
【００１６】上記のように構成された本実施例の動作に
ついて以下に説明する。演算増幅器20の反転入力端子に
制御電圧ＶCNT を印加したことにより、非反転入力端子
の電圧もＶCNT となり、このＰＭＯＳＦＥＴ21及び抵抗
器25でなる直列接続回路に次式で決まる電流Ｉ1 が流れ
る。The operation of this embodiment configured as described above will be described below. By applying the control voltage V CNT to the inverting input terminal of the operational amplifier 20, the voltage of the non-inverting input terminal also becomes V CNT , and the current I 1 determined by the following equation flows in the series connection circuit including the PMOSFET 21 and the resistor 25. .
【００１７】 Ｉ1 ＝ＶCNT ／Ｒ …(2) ただし Ｒ：抵抗器25の抵抗値 である。I 1 = V CNT / R (2) where R is the resistance value of the resistor 25.
【００１８】また、この直列接続回路に対してカレント
ミラー回路を形成するＰＭＯＳＦＥＴ23及びＮＭＯＳＦ
ＥＴ24でなる直列接続回路には、この電流Ｉ1 に等しい
電流Ｉ2 が流れる。Further, a PMOSFET 23 and an NMOSF which form a current mirror circuit with respect to this series connection circuit.
A current I 2 equal to this current I 1 flows through the series connection circuit composed of ET24.
【００１９】従って、インバータ10を構成するＰＭＯＳ
ＦＥＴ11，12に流れる電流Ｉp と、ＮＭＯＳＦＥＴ13，
14に流れる電流Ｉ2 とはそれぞれＩ1 に等しくなる。こ
のとき、インバータ10の入力容量をＣl 、定数をｋとす
ると、発振回路１は次式で示す周波数ｆで発振する。Therefore, the PMOS which constitutes the inverter 10
The current I p flowing through the FETs 11 and 12 and the NMOSFET 13,
The current I 2 flowing through 14 is equal to I 1 , respectively. At this time, when the input capacitance of the inverter 10 is C l and the constant is k, the oscillation circuit 1 oscillates at the frequency f shown by the following equation.
【００２０】 ｆ＝ｋ・Ｉ1 ／Ｃl …(3) 上述した(2),(3) 式から、発振回路１の発振周波数ｆ
は、製造上のバラツキ、温度変化、及び電源電圧変動等
に依存せず、しかも、制御電圧ＶCNT に比例することが
分かる。F = k · I 1 / C l (3) From the above equations (2) and (3), the oscillation frequency f of the oscillation circuit 1
Is independent of manufacturing variations, temperature changes, power supply voltage fluctuations, and the like, and is proportional to the control voltage V CNT .
【００２１】図２は本発明の他の実施例の構成を示す回
路図であり、図１中の電流制御回路2Aの代わりに電流制
御回路2Bを設けたものである。FIG. 2 is a circuit diagram showing the configuration of another embodiment of the present invention, in which a current control circuit 2B is provided instead of the current control circuit 2A shown in FIG.
【００２２】電流制御回路2Bは、演算増幅器20、ＮＭＯ
ＳＦＥＴ22、抵抗器25、ＰＭＯＳＦＥＴ23及びＮＭＯＳ
ＦＥＴ24によって構成されている。このうち、ＮＭＯＳ
ＦＥＴ22のソースは低電位電源Ｖssに接続され、このＮ
ＭＯＳＦＥＴ22のドレインには抵抗器25の一端が接続さ
れ、この抵抗器25の他端が高電位電源Ｖddに接続されお
り、これらが本発明の第１の直列接続回路を形成してい
る。また、ＰＭＯＳＦＥＴ23のソースが高電位電源Ｖdd
に接続され、このＰＭＯＳＦＥＴ23のドレインにはその
ゲートが接続されると共に、ＮＭＯＳＦＥＴ24のドレイ
ンに接続され、このＮＭＯＳＦＥＴ24のソースが低電位
電源Ｖssに接続されており、これらが本発明の第２の直
列接続回路を形成している。そして、演算増幅器20の出
力端がＮＭＯＳＦＥＴ22及びＮＭＯＳＦＥＴ24の各ゲー
トと、インバータ10を構成する電流制御用のＮＭＯＳＦ
ＥＴ14の各ゲートに接続され、演算増幅器20の非反転入
力端子がＮＭＯＳＦＥＴ22と抵抗器25との相互接合点、
すなわち、ＮＭＯＳＦＥＴ22のドレインに接続されてい
る。さらに、ＰＭＯＳＦＥＴ23のドレインがインバータ
10を構成する電流制御用のＰＭＯＳＦＥＴ12の各ゲート
に接続されている。そして、演算増幅器20の反転入力端
子（−）に制御電圧ＶCNT を印加するようになってい
る。The current control circuit 2B includes an operational amplifier 20 and an NMO.
SFET22, resistor 25, PMOSFET23 and NMOS
It is composed of FET24. Of these, NMOS
The source of the FET 22 is connected to the low potential power source V ss , and this N
One end of a resistor 25 is connected to the drain of the MOSFET 22, and the other end of the resistor 25 is connected to the high potential power supply V dd , which form the first series connection circuit of the present invention. Further, the source of the PMOSFET 23 is the high potential power supply V dd.
The drain of the PMOSFET 23 is connected to the gate thereof, and the drain of the NMOSFET 24 is connected to the source of the NMOSFET 24. The source of the NMOSFET 24 is connected to the low potential power supply V ss. It forms a connection circuit. The output terminal of the operational amplifier 20 has the gates of the NMOSFET 22 and the NMOSFET 24 and the current control NMOSF that constitutes the inverter 10.
The non-inverting input terminal of the operational amplifier 20 connected to each gate of the ET14 is a mutual junction point between the NMOSFET 22 and the resistor 25,
That is, it is connected to the drain of the NMOSFET 22. Furthermore, the drain of PMOSFET 23 is an inverter
It is connected to each gate of a PMOSFET 12 for current control, which constitutes 10. Then, the control voltage V CNT is applied to the inverting input terminal (−) of the operational amplifier 20.
【００２３】この実施例において、演算増幅器20の非反
転入力端子の電圧は制御電圧ＶCNTとなり、このＮＭＯ
ＳＦＥＴ22及び抵抗器25でなる直列接続回路に次式で決
まる電流Ｉ1 が流れる。In this embodiment, the voltage at the non-inverting input terminal of the operational amplifier 20 becomes the control voltage V CNT , and this NMO
A current I 1 determined by the following equation flows through the series connection circuit including the SFET 22 and the resistor 25.
【００２４】 Ｉ1 ＝（Ｖdd−ＶCNT ）／Ｒ …(4) また、この直列接続回路に対してカレントミラー回路を
形成するＰＭＯＳＦＥＴ23及びＮＭＯＳＦＥＴ24でなる
直列接続回路には、この電流Ｉ1 に等しい電流Ｉ2 が流
れる。I 1 = (V dd −V CNT ) / R (4) Further, the current I 1 is supplied to the series connection circuit including the PMOSFET 23 and the NMOSFET 24 forming a current mirror circuit for the series connection circuit. An equal current I 2 flows.
【００２５】しかして、(3),(4) 式から、発振回路１の
発振周波数ｆは、上述したと同様に、製造上のバラツ
キ、温度変化、及び電源電圧変動等に依存せず、しか
も、制御電圧ＶCNT に比例することが分かる。However, from the equations (3) and (4), the oscillation frequency f of the oscillation circuit 1 does not depend on manufacturing variations, temperature changes, power supply voltage changes, etc., as described above, and , Which is proportional to the control voltage V CNT .
【００２６】なお、上記各実施例にあっては、インバー
タ10として、ゲートどうしを接続して入力端子とし、ド
レインどうしを接続して出力端子とするＰＭＯＳＦＥＴ
11のソース側に電流制御用のＰＭＯＳＦＥＴ12を、ＮＭ
ＯＳＦＥＴ13のソース側に電流制御用のＮＭＯＳＦＥＴ
14を接続したが、この代わりに、ＰＭＯＳＦＥＴ11のド
レイン側に電流制御用のＰＭＯＳＦＥＴ12を、ＮＭＯＳ
ＦＥＴ13のドレイン側に電流制御用のＮＭＯＳＦＥＴ14
を接続した構成であっても上述した同様な動作を行なわ
せることができる。In each of the above embodiments, as the inverter 10, the PMOSFET having gates connected to each other as an input terminal and drains connected to each other as an output terminal.
A PMOSFET 12 for current control on the source side of 11
NFET for current control on the source side of OSFET13
14 is connected, but instead of this, a PMOSFET 12 for current control is provided on the drain side of the PMOSFET 11, and an NMOS is provided.
NMOSFET 14 for current control on the drain side of FET 13
Even with the configuration in which is connected, the same operation as described above can be performed.
【００２７】[0027]
【発明の効果】以上の説明によって明らかなように本発
明によれば、製造上のバラツキ、温度変化、及び電源電
圧変動等があっても、発振周波数のバラツキを抑え、か
つ、発振回路のゲイン特性を線形にすることによってこ
れを利用したＰＬＬを安定に動作させることができる。As is apparent from the above description, according to the present invention, even if there are manufacturing variations, temperature changes, power supply voltage variations, etc., variations in the oscillation frequency are suppressed and the gain of the oscillation circuit is reduced. By making the characteristic linear, the PLL using this can be operated stably.
【図１】本発明の一実施例の構成を示す回路図。FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.
【図２】本発明の他の実施例の構成を示す回路図。FIG. 2 is a circuit diagram showing the configuration of another embodiment of the present invention.
【図３】従来の電圧制御型発振回路装置の構成を示す回
路図。FIG. 3 is a circuit diagram showing a configuration of a conventional voltage controlled oscillation circuit device.
１ 発振回路 ２Ａ，２ｂ 電流制御回路 １１，１２，２１，２３ ＰＭＯＳＦＥＴ １３，１４，２２，２４ ＮＭＯＳＦＥＴ ２０ 演算増幅器 ２５ 抵抗器 1 Oscillation circuit 2A, 2b Current control circuit 11, 12, 21, 23 PMOSFET 13, 14, 22, 24 NMOSFET 20 Operational amplifier 25 Resistor
Claims (2)
のＰＭＯＳＦＥＴ及びＮＭＯＳＦＥＴを含んでなる奇数
個のインバータを含み、自己の出力端が他の入力端とな
るように前記インバータがリング状に接続され、前記Ｐ
ＭＯＳＦＥＴ及びＮＭＯＳＦＥＴの各ゲートに加える電
圧に応じた発振周波数を得る電圧制御型発振回路装置に
おいて、 演算増幅器と、ソースが高電位電源に接続され、ドレイ
ンが抵抗器を介して低電位電源に接続された第１の直列
接続回路と、ソースが高電位電源に接続されたＰＭＯＳ
ＦＥＴ及びソースが低電位電源に接続されたＮＭＯＳＦ
ＥＴを含み、このうち、ＰＭＯＳＦＥＴのドレインがＮ
ＭＯＳＦＥＴのドレイン及びゲートに接続された第２の
直列接続回路とを有し、 前記演算増幅器の出力端が前記第１及び第２の直列接続
回路の各ＰＭＯＳＦＥＴのゲート、並びに前記各インバ
ータの電流制御用ＰＭＯＳＦＥＴのゲートに接続され、
前記演算増幅器の非反転入力端子が前記第１の直列接続
回路のＰＭＯＳＦＥＴのドレインに接続され、前記第２
の直列接続回路のＮＭＯＳＦＥＴのドレインが前記各イ
ンバータの電流制御用ＮＭＯＳＦＥＴのゲートに接続さ
れた電流制御回路を備えたことを特徴とする電圧制御型
発振回路装置。1. An odd number of inverters including PMOSFETs and NMOSFETs for current control, which are connected in series to a power source, are included, and the inverters are ring-shaped so that their own output terminals become other input terminals. Connected to the P
In a voltage controlled oscillator circuit device that obtains an oscillation frequency according to a voltage applied to each gate of a MOSFET and an NMOSFET, an operational amplifier and a source are connected to a high potential power source, and a drain is connected to a low potential power source via a resistor. A first series connection circuit and a PMOS whose source is connected to a high potential power supply
NMOSF with FET and source connected to low potential power supply
Including ET, of which the drain of the PMOSFET is N
A second series connection circuit connected to the drain and the gate of the MOSFET, wherein the output terminal of the operational amplifier is the gate of each PMOSFET of the first and second series connection circuits, and the current control of each inverter. Connected to the gate of the PMOSFET for
The non-inverting input terminal of the operational amplifier is connected to the drain of the PMOSFET of the first series connection circuit,
2. A voltage control type oscillation circuit device comprising a current control circuit in which the drain of the NMOSFET of the serial connection circuit is connected to the gate of the current control NMOSFET of each of the inverters.
のＰＭＯＳＦＥＴ及びＮＭＯＳＦＥＴを含んでなる奇数
個のインバータを含み、自己の出力端が他の入力端とな
るように前記インバータがリング状に接続され、前記Ｐ
ＭＯＳＦＥＴ及びＮＭＯＳＦＥＴの各ゲートに加える電
圧に応じた発振周波数を得る電圧制御型発振回路装置に
おいて、 演算増幅器と、ソースが低電位電源に接続され、ドレイ
ンが抵抗器を介して高電位電源に接続された第１の直列
接続回路と、ソースが高電位電源に接続されたＰＭＯＳ
ＦＥＴ及びソースが低電位電源に接続されたＮＭＯＳＦ
ＥＴを含み、これらのＭＯＳＦＥＴのドレインどうしが
接続された第２の直列接続回路とを有し、 前記演算増幅器の出力端が前記第１及び第２の直列接続
回路の各ＮＭＯＳＦＥＴのゲート、並びに前記各インバ
ータの電流制御用ＮＭＯＳＦＥＴのゲートに接続され、
前記演算増幅器の非反転入力端子が前記第１の直列接続
回路のＮＭＯＳＦＥＴのドレインに接続され、前記第２
の直列接続回路のＰＭＯＳＦＥＴのゲートが該ＰＭＯＳ
ＦＥＴのゲート、及び前記各インバータの電流制御用Ｐ
ＭＯＳＦＥＴのゲートに接続された電流制御回路を備え
たことを特徴とする電圧制御型発振回路装置。2. A ring-shaped inverter including an odd number of inverters including PMOSFETs and NMOSFETs for current control, which are connected in series to a power supply, and whose output end is another input end. Connected to the P
In a voltage control type oscillation circuit device for obtaining an oscillation frequency according to a voltage applied to each gate of MOSFET and NMOSFET, an operational amplifier and a source are connected to a low potential power source, and a drain is connected to a high potential power source via a resistor. A first series connection circuit and a PMOS whose source is connected to a high potential power supply
NMOSF with FET and source connected to low potential power supply
And a second series connection circuit including drains of these MOSFETs connected to each other, wherein the output terminal of the operational amplifier is a gate of each NMOSFET of the first and second series connection circuits, and Connected to the gate of the current control NMOSFET of each inverter,
The non-inverting input terminal of the operational amplifier is connected to the drain of the NMOSFET of the first series connection circuit,
The gate of the PMOSFET of the serial connection circuit of
FET gate and current control P of each inverter
A voltage-controlled oscillation circuit device comprising a current control circuit connected to the gate of a MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31481493A JPH07170158A (en) | 1993-12-15 | 1993-12-15 | Voltage controlled oscillation circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31481493A JPH07170158A (en) | 1993-12-15 | 1993-12-15 | Voltage controlled oscillation circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07170158A true JPH07170158A (en) | 1995-07-04 |
Family
ID=18057928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31481493A Pending JPH07170158A (en) | 1993-12-15 | 1993-12-15 | Voltage controlled oscillation circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07170158A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100329793B1 (en) * | 1998-12-30 | 2002-05-09 | 박종섭 | voltage controlled oscilator |
| JP2015089135A (en) * | 2013-10-30 | 2015-05-07 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Temperature-compensated oscillator and electronic device including the same |
-
1993
- 1993-12-15 JP JP31481493A patent/JPH07170158A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100329793B1 (en) * | 1998-12-30 | 2002-05-09 | 박종섭 | voltage controlled oscilator |
| JP2015089135A (en) * | 2013-10-30 | 2015-05-07 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Temperature-compensated oscillator and electronic device including the same |
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