JPH0283650A - Bus response abnormality detection circuit - Google Patents

Abstract

PURPOSE:To detect abnormality in a bus response by providing an error memory circuit which detects and stores bus response abnormality as response signal abnormality in the case of detecting a response signal at a time when an address enable signal becomes inactive. CONSTITUTION:In an address enable inactivation detection circuit 1, the detection of the inactivation of the address enable signal, the inverse of AEN is performed, and in a response signal confirmation detection circuit 2, the activation of the response signal, the inverse of RDY is detected on one side, and the inactivation is detected on the other side. And those result are outputted from the IC of an LS74 as output signals RDT. Also, in the error memory circuit 3, the IC of the LS74 is set when the output signal ACP of the address enable inactivation detection circuit is generated in a state where the output signal RDT of the response signal confirmation detection circuit 2 is set. In such a way, it is possible to detect the abnormality of bus access also considering the timing regulation of the bus access.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for detecting an abnormality when the response signal of a device accessed via a bus such as a microphone The present invention relates to a bus response abnormality detection circuit that detects an abnormality, and particularly relates to a bus response abnormality detection circuit that detects an abnormality by taking bus access timing regulations into consideration.

[Technology from JX] In general, a microbuffer is an address bus signal line (ADH) and a data bus signal line ([)ΔT).
, an address enable signal line (AEN) indicating that the value of the address bus signal line has been determined, and a response signal line (RDY) from a device coupled to the bus. Then, the memory and IO connected to this bus,
Processing is proceeding by accessing the channel device.

Further, in such a case, the accessed device returns a ready signal (response signal) to the bus in order to complete the pass cycle.

Therefore, conventionally, when detecting an abnormality in bus response,
The presence or absence of this ready signal was monitored.

[Problems to be solved] In the conventional bus response abnormality detection described above, the microprocessor only monitored the presence or absence of a response signal sent back from the device accessed via the bus, so in reality, the bus access timing regulations If this is not satisfied and the response signal is driven for a time width longer than the specified value, it may appear that normal bus access is being performed even though normal bus access has not been completed. There was an issue that there was.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a bus response abnormality detection circuit that can detect abnormalities in bus responses by also monitoring bus access timing.

[Means for Solving the Problems] In order to achieve the above object, the bus response abnormality detection circuit of the present invention includes an address enable deactivation detection circuit that detects when the address enable signal becomes inactive, and an address enable deactivation detection circuit that detects when the response signal becomes inactive. If a response signal is detected by the response signal confirmation detection circuit at the time when the address enable signal becomes inactive by the response signal confirmation detection circuit and the address enable deactivation detection circuit, the response signal is detected by the response signal confirmation detection circuit. The configuration includes an error storage circuit that detects and stores bus response abnormalities as signal abnormalities.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a circuit diagram of a bus response abnormality detection circuit according to an embodiment of the present invention.

In the figure, 1 is an address enable deactivation detection circuit, 2 is a response signal confirmation detection circuit, and 3 is an error storage circuit.

First, in the address enable deactivation detection circuit l, the address enable signal AEN (active low) indicating that the address signal has been determined is
It is received by B's IC. Then, the 20ns delay output and the output of the inversion circuit by the LSO4 IC are transferred to the LSOO IC.
manually input the address enable signal A to the NAND circuit
EN deactivation detection is performed. That is, the rise of the address enable signal is detected, and the result is the output signal ACP.

On the other hand, within the response signal confirmation detection circuit 2, the response signal RDY, (active low) from the device coupled to the bus
is received by the L9368 IC.

Then, with a delay of 20 ns and the ICs of LSO4 and LSoo, activation of the response signal RDY is detected on the one hand, and deactivation of the response signal RDY is detected on the other hand. At this time, when activation is detected, the IC of the LS 74 provided at the next stage is set, and conversely, when deactivation is detected, it is reset.

These results are then output as an output signal R from the LS74 IC.
It is output as DT.

In addition, the error storage circuit 3 is connected to the response signal confirmation detection circuit 2.
When the output signal ACP of the address enable deactivation detection circuit is generated when the output signal RDT of the address enable deactivation detection circuit is in the set state, the IC of LS74 is set. Therefore, if this output signal ERR is set, it means that there is an abnormal response.

Now, FIG. 2 is a timing chart of normal bus access timing.

As shown in the figure, when the output signal ACP of the response signal confirmation detection circuit 2 is generated, the output signal RDT of the response signal confirmation detection circuit 2 has already been reset, so the output signal ERR of the error storage circuit 3 is It is not set and there is no abnormal response.

On the other hand, FIG. 3 is a timing chart of abnormal bus access timing.

As shown in the figure, if the accessed device drives the response signal RDY for a long time longer than the specified value, the second bus cycle will be shortened. Therefore, if a write operation is performed in such a case, there is no guarantee that the data will be written accurately, and conversely, if a read operation is performed, there is no guarantee that the data will be accurately read.

Therefore, address enable deactivation detection @ path
The output signal RDT of the response + S confirmation detection circuit 2 is sampled by the output signal ACP of the output signal ACP, and the output signal ERR is set in the error storage circuit 3 at the point in time when the output signal Ima DT is in the set state. As a result, a response abnormality is detected.

It should be noted that the present invention is not limited to the above embodiments, but includes various modifications within the scope of the gist. For example, in the embodiment described above, the confidence return line is set to active low, but it may also be set to active high.

[Effects of the Invention] As explained below, the present invention has the effect of providing a bus response H constant detection circuit that can detect the permanence of bus access while also taking bus access timing regulations into consideration. be.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a bus response abnormality detection circuit according to an embodiment of the present invention, Fig. 2 is a timing chart of normal bus access timing, and Fig. 2 is a timing chart of abnormal bus access timing. l Near trace enable 4 (near activation detection circuit 2
:Response signal confirmation detection circuit 3: Error-3 self-defense! circuit

Claims (1)

[Claims] The address enable deactivation detection circuit detects that the address enable signal becomes inactive, the response signal confirmation detection circuit detects that the response signal is active, and the address enable deactivation detection circuit described above. If the response signal is detected by the response signal confirmation detection circuit at the time when the signal becomes inactive, the device is characterized by comprising an error storage circuit that detects and stores the bus response abnormality as a response signal abnormality. Bus response abnormality detection circuit.