JPH0281587A - Picture signal processor - Google Patents

Abstract

PURPOSE:To prepare a frame signal without a double speed conversion by alternately selecting field picture signal data delayed by one scanning line period and the other interpolated field picture signal data. CONSTITUTION:A signal (d) outputted from a mean value arithmetic circuit 16 is sent through a signal line 110 to a switch 18, a signal (b) outputted from a one-H delay circuit 12 is sent to the switch 18 as well, and the switch 18 is changed-over at every time for one line, and a signal (e) is outputted from the output terminal of the switch 18. At a time t3, the data on an (L+1)-th line is outputted by the signal (d) outputted from the mean value arithmetic circuit 16. In the same way, by changing over the switch 18, the signal (e) obtained by interpolating the other field line between the respective lines of a signal (a) is outputted. In such a way, by supplying the field signal (a) having an interval to an input terminal 10, the frame signal (e) is outputted to an output terminal 20. Thus, the frame picture signal can be prepared from the field picture signal without executing a double-speed conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device, and particularly to an image signal processing device that processes a field image signal to create a frame image signal.

BACKGROUND ART In a video reproducing apparatus, it is sometimes required to process a supplied field image signal into a frame image signal, and display an image on a video monitor using the obtained frame image signal.

As described above, as a method of creating a frame image signal from a field image signal, for example, Japanese Patent Application Laid-Open No. 83-50183
The method disclosed in the above publication creates a non-interlaced frame image signal from a field image signal by double speed conversion. That is, each scanning line data is delayed by delaying each scanning line data constituting the field image signal, and by setting the frequency at which the pixels constituting the scanning line data are read out to twice the frequency of the pixels in the original field image signal. The data read time is set to 1/2 of each scanning line data of the original field image signal, and an interval is generated between each scanning line data. A non-interlaced frame signal is obtained by inserting and arranging other field image signal data created by average value interpolation or the like between the interhales.

In such a frame image signal generation device, it is necessary to perform the double speed conversion as described above, which requires system clocks with two different frequencies, making the system complicated, and furthermore, beats are generated due to two different frequencies. There were drawbacks.

OBJECTS It is an object of the present invention to provide an image signal processing device that can eliminate the drawbacks of the prior art and can create a frame image signal from a field image signal without performing double speed conversion.

DISCLOSURE OF THE INVENTION According to the present invention, an image signal processing bag for processing a field image signal to create a frame image signal provides an interval of one scanning line period between each scanning line data constituting the field image signal. an input means for inputting a field image signal using the input means; a first delay means for delaying the field image signal data inputted from the input means by one scanning line period; a second delay means for delaying by one scan line period;
a signal interpolation means for creating other field image signal data by calculating the average value of the field image signal data delayed by the second delay means and the field image signal data inputted from the input means; a signal selection means for selecting the interpolated other field image signal data and the field image signal data delayed by one scanning line period by the first delay means;
The signal selection means alternately selects the other field image signal data interpolated by the signal interpolation means and the field image signal data delayed by one scanning line period by the first delay means, thereby producing a non-interlaced signal. It creates a frame signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the image signal processing device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of an image signal processing device according to the present invention.

This framing circuit 30 has an input terminal 10 supplied with a field image signal. As will be described later, the field image signal supplied to the input terminal 1O has an interval, and although not shown, it can be obtained by, for example, reading out a field signal stored in a RAM with an interval of one line for each scanning line. It will be done.

The signal input to the input terminal 10 is also sent to the IH delay circuit 12 through the signal line 102. The LH delay circuit 12 is
This is a delay circuit that delays an input signal by one scanning line (IH). The signal input from input terminal IO is also. The signal is sent to the average value calculation circuit 16 through the signal line 10B.

The output from the IH delay circuit 12 is transmitted through the signal line 104.
The signal is sent to the H delay circuit 14 and also to the switch 18 through the signal line 112. The IH delay circuit 14
Similarly to the delay circuit 12, the input signal is transferred to one scanning line (IH
) is a delay circuit.

The output from the IH delay circuit 14 is sent to the average value calculation circuit 16 through a signal line 1013.

The average value calculation circuit 16 connects the input terminal 10 to the signal line +08
This is an arithmetic circuit that calculates the average value of the image signal data sent through the IH delay circuit 14 and the image signal data sent from the IH delay circuit 14 through the signal line 10B. The output from the average value calculation circuit 16 is sent to the switch 18 through a signal line 110. The switch 18 is controlled by a control signal sent from the control circuit 40 through the control line 120, and selects either the image signal data sent through the signal line 110 or the image signal data sent through the signal line +12. +4 and output to output terminal 20.

The control circuit 40 is a control section that not only controls the switch 18 as described above but also sends a control signal to each functional section of the apparatus (not shown) to control each functional section.

The operation of this device will be explained with reference to the timing chart shown in FIG.

The signal a shown in FIG. 3 is input from the input terminal 10.

As shown in FIG. 3, the signal a is a field signal having image data for every two lines, and as shown in the same figure, the image data for each line is input with an interval of one line in between. This signal a is passed through the signal line 102 to I
The b signal is input to the H delay circuit 12, is delayed by l lines in the IH delay circuit 12, and is outputted from the IH delay circuit 12.6 As shown in FIG. The data is output from time t2 and is delayed by one line from time t1 of the C signal.

The b signal is input to the LH delay circuit 14 through the signal line +04, similarly delayed by one line, and then sent to the IH delay circuit 14.
A C signal is output from. As for the C signal, data on line L of the C signal is output from time t3, and is delayed by two lines from time t1 of the C signal.

The C signal is sent to the average value calculation circuit 16 through the signal line 106. The C signal is also input to the average value calculation circuit 16 from the input terminal 10 through the signal line 108. The average value calculation circuit 16 averages these C signals and the data of the C signals to create a d signal corresponding to image data of other fields. That is, for example, at time t3, C
Data on the L+2th line of the signal and data on the Lth line of the C signal are averaged to create data on the L+1th line.

The d signal output from the average value calculation circuit 18 is connected to the signal line 11.
0 to switch 18. The b signal output from the IH delay circuit 12 is also sent to the switch 18 . The switch 18 is switched at intervals of one line, and the output terminal of the switch 18 outputs a C signal. That is, the switch 18 is connected to the state shown in the figure at time t2, and the data of the Lth line is output by the b signal output from the IH delay circuit 12. At the next time t3, the data of the L+1th line is output by the d signal output from the average value calculation circuit 16. Similarly, by switching the switch 18, lines of other fields are interpolated between each line of the a° multiplied signal, and a C signal is output. The C signal is a frame signal. Such a C signal is output to the output terminal 20 through the signal line 114.

According to the present device, as described above, by supplying the field signal a having an interval to the input terminal lO,
A frame signal e is output to the output terminal 20.

Conventionally, as shown in FIG. 5, field image signal data A is converted at double speed to obtain frame image signal data E.)
Ta. That is, the data at the beginning of the L line is delayed by 1/2 line, and the time T corresponding to each pixel data is converted to T/2. Similarly, the data on the L+2nd line is 1/
It is delayed by two lines and converted so that the time T corresponding to each pixel data is T/2. A non-interlaced frame signal E is created by interpolating the data on line L+1 between the double-speed converted data on line L and the data on line L+2 by means of average value interpolation or the like. In such a device, it is necessary to perform troublesome double speed conversion, which may cause beats to occur.

On the other hand, in this device, a field signal is converted into a frame signal without performing double speed conversion. Therefore, since it can be operated with only a single system clock and does not use clocks of multiple frequencies unlike conventional devices using double speed conversion, there is no risk of beats occurring.

FIG. 2 shows another embodiment of the image signal processing device according to the present invention.

The device shown in the figure has a digital filter 22, and after the field signal inputted from the input terminal 10 is processed by the digital filter 22, the frame signal is converted into a frame signal by a framing circuit 30, similar to the device shown in FIG. It is something to create.

The field signal X input from the input terminal 10 is
As shown in the figure, it is a field signal having image data for every two lines, and as shown in the figure, the image data for each line is input with an interval of one line in between. The signal X has a predetermined frequency cut by a digital filter, and is outputted to the framing circuit 30 as a signal y shown in FIG. Here, the signal y is expressed as y(m, n)=ΣC(i)x(m, n+i).

The signal y is delayed by passing the signal X through a digital filter 22, as shown in the figure. In other words, 1. For example, data on the Lth line is generated from time tl in signal X, but occurs at time t2 in signal y.
It is occurring from. This is because the data of the Lth line of the signal X is processed by the digital filter 22.
This is because the period from time t1 to t4 is required.

The signal y corresponds to the signal a in FIG.
A frame signal is created as in the case of the apparatus shown in FIG. The generated signal 2 corresponds to the signal e in FIG. 1 and is output to the output terminal 20. Here, signal 2 is z
(m, n) = y (m, n) and f (y(m
−1, n), y(m+1, n)).

According to this device, after a field signal having image data for every two lines has a predetermined frequency selected by the digital filter 22, it is converted into a frame signal by the framing circuit 30. Therefore, similarly to the apparatus shown in FIG. 1, frame signal data can be created from field signal data.

Further, the signal X is delayed by passing through the digital filter 22, but since the signal X is a signal having an interval, the delayed portion is absorbed by the interval, and the data on each line is free from the influence of other data. I don't accept it. That is, for example, the last part of the data on the L line is at time t3 in signal X, but is delayed to time t4 in signal y by passing through the digital filter 22.

However, at time t4, the Lth line data of signal X and L+
Since it is located between the second data, it is not affected by the L+2nd data. In the case of a signal without an interval, since the signals of each line are adjacent to each other, that is, there is no time interval between the data of the next line and the data of the next line, the processing of the digital filter 22 causes This has the disadvantage that the edges of the data on each line are affected and noise occurs.

In contrast, according to the present embodiment, since there is an interval between adjacent line data, the ends of each line data are not affected by other line data.

Effects According to the present invention, a frame signal can be created without performing 1x speed conversion, so the device can have a simple configuration. Furthermore, there is no risk of beats occurring due to multiple frequencies, which is seen in devices that perform double speed conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the image signal processing device according to the present invention, FIG. 2 is a block diagram showing another embodiment of the image signal processing device according to the present invention, and FIG. 3 is the device shown in FIG. 1. FIG. 4 is a timing chart showing part of the signal processing performed by the device shown in FIG. 2; FIG. 5 is a timing chart showing signal processing performed by a conventional frame forming circuit. Explanation of symbols for important parts 10° input terminal 12.14 H delay circuit 16. Average value calculation circuit 18°, swift 20° output terminal 22°, digital filter

Claims (1)

[Scope of Claims] 1. In an image signal processing device that processes a field image signal to create a frame image signal, the device comprises: one scanning line period between each scanning line data constituting the field image signal; input means for inputting the field image signal at intervals; a first delay means for delaying the field image signal data input from the input means by one scanning line period; a second delay means for further delaying the field image signal data by one scanning line period; and the field image signal data delayed by the second delay means and the field image signal data input from the input means. a signal interpolation means for creating other field image signal data by calculating the average value of the other field image signal data interpolated by the signal interpolation means and delayed by one scanning line period by the first delay means; and signal selection means for selecting the field image signal data interpolated by the signal interpolation means and the field image signal data interpolated by the signal interpolation means and the field image signal data interpolated by the first delay means. An image signal processing apparatus characterized in that a non-interlaced frame signal is created by alternately selecting the field image signal data delayed by a period of time. 2. The device according to claim 1, further comprising:
An image signal processing device characterized by comprising a digital filter that processes the field image signal inputted from the input means and provided with a predetermined interval.