JPH0281440A - Field effect transistor - Google Patents

Abstract

PURPOSE:To widen the spacing between a gate and a source to the extent that the variation caused by an alignment accuracy has no influence and reduce the variation of the resistance between the gate and the source by providing the impurity concentration of a conductive layer between the gate and the source higher than the impurity concentration between the gate and a drain. CONSTITUTION:An insulating gallium arsenite substrate 11, an N-type conductive layer 12, a source electrode 13, a gate electrode 14 and a drain electrode 15 are provided. By providing the impurity concentration (N2) of the conductive layer 12b between the gate and source higher than the impurity concentration (N1) of the conductive layer 12a between the gate and drain and making the spacing (L2) between the gate and source approximately equal to the spacing (L1) between the gate and drain, the variation of the resistance between the gate and source can be reduced and the variation of a noise index can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) The present invention relates to the structure of a field effect transistor used in high frequency fields such as microwave communications.

] The cross section of the operating part of a field effect transistor is generally the third
It has a structure as shown in the figure. In FIG. 3(a), 1 is an insulating substrate, 2 is an N-type conductive layer, 3 is a source electrode,
4 is a gate electrode, and 5 is a drain electrode.

In order to improve high frequency characteristics such as output characteristics in this field effect transistor, it is important to lower the resistance between the gate and the source and to increase the withstand voltage between the gate and the drain.

Conventionally, in order to lower the resistance between the gate and source and increase the withstand voltage between the gate and drain, the distance between the gate and source (L2) was changed to the distance between the gate and drain (L2), as shown in FIG. 3(b). A structure commonly called an offset gate has been adopted in which the gate width is narrower than Ll).

When designing an actual device using the conventional method, the gate-source distance is approximately 0.4 μm, and the gate-drain distance is 1 μm.
．． It will be about 5 μm. On the other hand, with current exposure technology, the alignment accuracy is limited to ±0.1 μm, so gate
The source spacing is 0.4 ± 0.1 μm, expressed as a percentage ±
There is a large variation of 25%, resulting in noise figure and output characteristics.

Variations in high frequency characteristics such as gain occur.

In particular, for high-output field effect transistors, Figure 4 (
As shown in a), source electrodes and drain electrodes are arranged alternately with the gate in between. In such a structure, if the alignment is 0.1 μm apart, unit transistors with a gate-source spacing of 0.3 μm and unit transistors with a gate-source spacing of 0.5 μm are alternately used, as shown in Figure 4(b). They start lining up. As a result, the synthesis of each unit transistor is not efficient, and the high-frequency characteristics such as the output characteristics and gain of the high-output field effect transistor as a whole are deteriorated.

In conventional field effect transistors, the resistance between the gate and source was reduced by shortening the distance between the gate and source, whereas in the field effect transistor according to the present invention, the distance between the gate and source was reduced. is the gate
The resistance between the gate and source is lowered by making the distance approximately the same as that between the drain and by making the degree of impurity in the conductive layer between the gate and source higher than that between the gate and drain.

By adopting a structure such as one or more plates, the distance between the gate and source required to obtain the desired resistance between the gate and source is set to a length such that the variation in the distance due to alignment is sufficiently small in proportion. , and it is possible to reduce the variation in resistance between the gate and source of the field effect transistor. As a result, variations in high frequency characteristics such as noise figure, output characteristics, and gain can be reduced.

In addition, in high-power field-effect transistors, the variation between unit transistors is reduced, which improves the synthesis efficiency of each unit transistor and improves the high-frequency characteristics of the high-power field-effect transistor as a whole. .

Real example - Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining an embodiment in which the present invention is applied to a low-noise gallium arsenide field effect transistor.

In FIG. 1, 11 is an insulating gallium arsenide substrate;
2 is an N-type conductive layer, 13 is a source electrode, 14 is a gate electrode, and 15 is a drain electrode.

In order to obtain good high-frequency characteristics as a low-noise gallium arsenide field effect transistor, the resistance between the gate and source must be at least 1Ω per 1mm of gate width, and the withstand voltage between the gate and drain must be at least 6V. The impurity concentration (N1) of the conductive layer 12a between the gate and drain is 2×101
7C11-3, the impurity concentration (N2) of the conductive layer 12b between the gate and source is 5 x 1017 cm-3, and the gate
Drain and gate-source distance (Ll, , L2
) are each 1.5 μm, this value can be achieved.

As a result, as shown by line A in Figure 5(a), the variation in resistance between the gate and source can be reduced, and as shown by line A in Figure 5(b), low noise can be achieved. It has become possible to reduce the variation in the noise figure, which is important for the high-frequency characteristics of gallium arsenide field-effect transistors for use in industrial applications. Note that, for comparison, FIGS. 5(a) and 5(b) each show a conventional example as a B line. As is clear from the figure, the variation in this embodiment is reduced to 1/2 or less compared to the conventional one.

Next, another embodiment in which the present invention is applied to a high-output gallium arsenide field effect transistor will be described with reference to FIG.

In FIG. 2, 11 to 15 are the same as in FIG. However, in order to further improve the ohmic contact between the drain and source electrodes and the crystal, the impurity concentration (N3) in the conductive layers 12c and 12d under each electrode 13.15 is made high. At this time, the effective drain and source electrodes are
As shown in FIG. 2, it extends to the ends of the conductive layers 12c and 12d with high impurity concentration (N3).

In order to obtain good high-frequency characteristics as a high-power gallium arsenide field-effect transistor, the resistance between the gate and source must be 2 Ω or less per gate width [■], and the withstand voltage between the gate and drain must be 20 V or more.・The impurity level (N+) of the conductive layer 12a between the drains is 1×1017c.
lI-3, impurity 1 in conductive layer 12b between gate and source
The degree (N2) is 3X 1017 cm-3, and the gate-drain and gate-source distances (Ll, L2) are each 1.
This value can be achieved by setting the thickness to 5 μm.

In FIG. 6, the distribution of output characteristics, which are important as high-frequency characteristics of a high-output field effect transistor, is shown in line A for this embodiment and line B for a conventional example for comparison.

As is clear from the figure, this example shows that the variation in variation is smaller than that of the conventional example, and the output characteristics are improved (larger).

As explained above, the present invention makes the impurity degree of the conductive layer between the gate and source higher than the impurity degree of impurity between the gate and drain, thereby eliminating variations in the gate-source spacing due to alignment accuracy. It is possible to widen the width to such an extent that it does not affect the resistance, and it is possible to reduce the variation in resistance between the gate and the source. As a result, variations in high-frequency characteristics such as noise figure and gain that are affected between the gate and source are reduced, and in devices such as high-output field-effect transistors whose characteristics are obtained by synthesizing unit transistors, each Variations in unit transistors are reduced,
By improving the synthesis effect, the overall output characteristics,
This has the effect of improving high frequency characteristics such as gain.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining an embodiment in which the present invention is applied to a low-noise gallium arsenide field effect transistor;
FIG. 2 is a cross-sectional view for explaining an embodiment in which the present invention is applied to a high-power gallium arsenide field effect transistor;
The figures are cross-sectional views explaining conventional field-effect transistors. (a) is a normal type, (b) is a gate offset type, and Figure 4 shows a high-power gallium arsenide field-effect transistor due to misalignment. The distance between the gate and source of adjacent unit elements is alternately 0.3 μm and 0.5 μm.
These are cross-sectional views illustrating what happens, where (a) shows a case where the misalignment in alignment is 0 μm, and (b) shows a case where the misalignment is 0.1 μm. 1 to 4, 1.11 is an insulating substrate, 2,
12 is an N-type conductive layer, 3 and 13 are source electrodes, 4.14
is a gate electrode, and 5 and 15 are drain electrodes. 5 and 6 are diagrams for explaining the effects of the present invention. FIG. 5(a) is a diagram showing the distribution of resistance between the gate and source, and FIG. 5(b) is a diagram showing the distribution of resistance between the gate and source. A diagram showing the distribution, FIG. 6 is a diagram showing the distribution of output. Figure 1 (a) ] (b) Figure +, 2 ,,,, Gametzos Kaimura Saisai 1t (cL) 1.4 1.6 1.8 2, ○ ball"h self 4
TFs number (I meeting - Memi L basis) B (b)! 15 Figure

Claims (1)

[Claims] In a field-effect transistor in which a source electrode, a gate electrode, and a drain electrode are formed at predetermined intervals on a conductive layer, the impurity concentration of the conductive layer between the case and the source increases the conductivity between the gate and the drain. A field effect transistor characterized by a higher impurity concentration than the layer.