JPH0277839A - Data processor - Google Patents

Abstract

PURPOSE:To increase the instruction read speed and to shorten the startup time by providing a 2nd instruction buffer (Controlable Instruction buffer, C buffer) which can control the contents of an instruction buffer with an instruction. CONSTITUTION:A request on a path 50 is sent to a comparing circuit 6, which compares the entry address of the instruction buffer 3 with an instruction address. A signal which is sent onto a path 51 is sent to a comparator 7, which compares the entry address of a C buffer 2 with the instruction address. When a target instruction is not on the instruction buffer 3, but on the C buffer 2, a requester 8 reads the data out of the C buffer 2 through a path 57 and transfers the data to the instruction buffer 3 through a path 58 and a selector 9. When a main storage and C buffer transfer instruction is sent from an instruction execution control part 4 directly to the requester 8, the requester 8 sends a main storage reference request to a main storage 1 through a path 60. Data which is read out at this request is written on the C buffer 2 and the head address of mXn instructions stored on the C buffer 2 are stored in the entry part of the comparing circuit 7 at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more particularly to a data processing device such as a supercomputer that achieves high-speed instruction reading.

[Conventional technology]

In recent years, there has been an increasing demand for speeding up the reading of instructions in supercomputers.

This is because (1) reading instructions tends to become a bottleneck when trying to perform faster calculations, and (2) if the machine cycle is extremely shortened, the performance of the memory element cannot keep up with it, and reading instructions becomes more difficult. This is to deal with the fact that a long cycle time is required for vector processing, which appears to increase the start-up time of vector processing.

Recently, research has been progressing in the direction of substantially shortening the instruction read time through some kind of architectural innovation.

A supercomputer is a specialized computer created to perform high-speed calculations for scientific and technical calculations. Therefore, among some functions of a general-purpose computer, functions that are unlikely to be used and that pose an obstacle to high-speed calculation may be omitted. Among these functions is a function that allows instructions in a program to be rewritten. In general, when a large computer supports this function, it becomes difficult to speed up processing with deep advance control, and it also becomes an obstacle when executing instructions in parallel.

For this reason, some vector processing devices avoid the above-mentioned problem by not guaranteeing the result when a store instruction on the vector processing side rewrites an instruction on the scalar processing unit side.

As this kind of conventional technology, for example, the technology described in HiTAC3-820 Processing Equipment Manual 6020-2-00IP, P, 42, etc. is known.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology still has the problem that it requires a lot of time to read instructions, which is a bottleneck for high-speed data processing devices such as supercomputers that are dedicated to scientific and technical calculations.

An object of the present invention is to solve the above-mentioned problems of the prior art, extend the specification that does not guarantee results when rewriting instructions in a program to not only the vector processing section but also the scalar processing section, and thereby improve the architecture of the data processing device. Another object of the present invention is to provide a data processing device whose hardware configuration is changed to be suitable for supercomputers, thereby making it possible to improve instruction reading speed and shorten startup time.

[Means to solve the problem]

According to the present invention, the above object is achieved by providing an instruction buffer having the following structure and a logic mechanism for controlling the instruction buffer.

(1) An instruction buffer that can be referenced without address conversion when an instruction address is a logical address.

(2) A second instruction buffer (hereinafter referred to as Controllable I) that can control the contents of the instruction buffer by instructions.
n-5 traction buffer (abbreviated as C buffer).

(1) A logic circuit that checks whether an instruction address exists in the instruction buffer or C buffer when an instruction read request is issued from an instruction requester.

(2) If the instruction address has not been entered in the instruction buffer or C buffer at the time the instruction read request is issued from the instruction requester, a request to read n instructions (n≧1) from the instruction address to the main memory is made. Logic circuit to issue.

(3) A logic circuit that cancels the contents of the instruction buffer and C buffer.

(4) A logic circuit that transfers data by the word length specified by the instruction from the main memory to the C buffer.

(5) When an instruction read request is issued from the instruction requester, if the instruction address has not been entered in the instruction buffer but has been entered in the C buffer, transfer n instructions from the C buffer to the instruction buffer. logic circuit.

(6) An instruction decoding/execution logic circuit that starts the process of transferring data from the main memory to the C buffer, and executes the subsequent instruction in the next cycle without waiting for the completion of the transfer.

(7) If a subsequent instruction is included in the data transfer range while data is being transferred from main memory to the C buffer, the execution of the subsequent instruction is interrupted and the transferred data is transferred to the C buffer and the instruction buffer. Logic circuitry for writing and resuming execution of the subsequent instruction.

(8) A logic circuit that suspends instruction execution when no instruction read request is entered in the instruction buffer.

(9) A logic circuit that resumes instruction execution when the read instruction is written to the instruction buffer.

(10) Divide the C buffer into a plurality of parts, provide a flip-flop corresponding to each part, and set the flip-flop to "1" when the C buffer is read.
A logic unit that resets the flip-flop to "0°" for each signal output by an interval timer at a certain timing.

(11) When transferring data from main memory to C buffer,
A logic circuit having a storage unit that determines a write column of a C buffer and holds the first logical address of an instruction set in the column.

(12) A logic circuit that determines in which column of the instruction buffer the instruction string is stored when transferring the instruction string from the main memory to the instruction buffer.

[Operation] In a data processing device equipped with a buffer memory, a replacement algorithm on the buffer memory is devised so that the buffer memory can be used as effectively as possible.

The data processing device of the present invention, which includes an instruction buffer and a C buffer exclusively for reading instructions, can perform efficient buffering by utilizing the characteristics of the instruction read request to control the two buffers.

Analyzing program execution, we find that (1) instructions are read from main memory in order according to the order in which the program statements are written, (2) the same instruction sequence represented by a loop is repeatedly executed with different data, and ( 3) A case in which a request for successive instruction is made to a completely different instruction address represented by a branch.

In the above case (1), n (n≧1) instructions are read out once.
) is read from the main memory and held in the instruction buffer, it is possible to speed up instruction reading. Furthermore, the instruction buffer replacement algorithm can also be simplified by utilizing the order of instruction reading.

In case (2), a C buffer is used instead of an instruction buffer, and instructions are read from the C buffer when repeatedly executing a sequence of instructions. That is, it is possible to process faster than reading instructions from the main memory. Since the C buffer is written into the buffer by an instruction, the C buffer holds the instruction string previously entered on the buffer unless the instruction is issued frequently. Therefore, the C buffer works effectively even in some cases (3) where there is a loop or branch history. Furthermore, by making functions, subroutines, etc. that are frequently used throughout the program resident in the C buffer, it is possible to reduce the frequency of access to the main memory and speed up processing.

When a program is executed, the logic unit controlling the instruction buffer described above operates as follows.

When an instruction read request occurs within the processing device, it is checked whether an instruction address has been entered in the instruction buffer and the C buffer. If an instruction address is not entered in both buffers, an instruction read request is issued to the main memory and instruction execution is interrupted. When the instruction sequence is read from the main memory and written into the instruction buffer, an operation to take out the instruction from the instruction buffer is started, and instruction execution is resumed. If no instruction address is entered in the instruction buffer but an instruction address is entered in the C buffer, instruction execution is resumed after the instruction sequence is transferred from the C buffer to the instruction buffer.

The above is a general instruction execution method.

When an instruction that requests data transfer to the C buffer is issued in a program, the operation of transferring data from main memory to the C buffer is started, and instructions other than the data transfer instruction are executed in the next machine cycle. Ru. When data transfer instructions to the C buffer are issued consecutively, the instruction execution operation is serialized. However, if logical measures are taken such as providing a plurality of data transfer paths from the main memory to the C buffer and making the C buffer interleaved or multifaceted, instruction execution operations can be processed in parallel. However, in the present invention, this part will not be described in more detail. When data is being transferred from main memory to C buffer,
If a read request for an instruction that does not exist in the instruction buffer is issued, and the instruction for this instruction read request is included in the data transfer to the C buffer, the data is written to the C buffer and also written to the instruction buffer at the same time. It is controlled to write this data.

Instructions stored in the instruction buffer and the C buffer cannot be rewritten by store instructions because there is no path for writing to both buffers. Therefore, in order to prevent the program from being completely unable to cope with rewriting instructions in the program, a means for canceling the contents of the instruction buffer and the C buffer is provided. As a result, the instruction sequence that has been rewritten on the main memory is read out to the buffer again and executed.

In the present invention, performance can be improved if the C buffer is used wisely, but the program will operate normally even if it is not used. Therefore, no compatibility problem will occur even when old object programs are executed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data processing apparatus according to the present invention will be described in detail below with reference to the drawings.

Simplify the explanation and make it easier to understand the essential points of the invention
Therefore, the explanation will be given with the following constraints.

(1) The logical relationship among the instruction buffer, C buffer, and main memory is that they are closest to the instruction processing unit in this order.

The instruction buffer and the C buffer may be configured to be placed at logically equivalent positions to the instruction processing section. Alternatively, the instruction buffer and the C buffer may be implemented as part of the same buffer storage, and an identification flag may be provided to distinguish between the two. However, the latter method is effective as a remedy when branches occur frequently, but if you want to reduce main memory reference operations by importing functions, subroutines, etc. into the C buffer, the C The buffer needs to have a significantly larger capacity than the instruction buffer. Further, it is not desirable to place the instruction buffer and the C buffer, which have different properties, at a logically equivalent distance because the method for controlling both becomes complicated.

(2) One type of instruction word length! Bi l-CB).

(3) The instruction buffer is configured with a plurality of columns, and the number of instructions stored in one column is n.

(4) The C buffer is configured with a plurality of columns, and the number of instructions stored in one column is m−n.

(5) Let It-m-n (B) be the unit of data transferred from the main memory to the C buffer.

(6) Let ff1-n(B) be the unit of data transferred from the C buffer to the instruction buffer.

FIG. 1 is a block diagram schematically showing an embodiment of a data processing apparatus according to the present invention. In FIG. 1, 1 is a main memory, 2 is a C buffer, 3 is an instruction buffer, 4 is an instruction execution control section, 5 is an instruction execution section, 6.7 is a comparison circuit, and 8 is a requester.

First, the instruction execution control unit 4 issues an instruction read request and address on the path 50.51. The request on path 50 is sent to comparison circuit 6, where the entry address of instruction buffer 3 and the instruction address are compared. Comparison circuit 6
If, as a result of the comparison, the target instruction exists in the instruction buffer 3, the instruction is sent from the instruction buffer 3 to the instruction execution control unit 4 via the path 52. If the target instruction does not exist in the instruction buffer 3, a main memory reference request is issued to the requester 8 via the path 53.

Further, the signal sent on the path 51 is sent to the comparison circuit 7, and the entry address of the C buffer 2 and the instruction address are compared. The results of the comparison are issued to the requester 8 via path 54.

Requester 8 performs the following operations based on the signals on paths 53 and 54.

(1) If there is no target instruction in either the instruction buffer 3 or the C buffer 2, a main memory reference (hereinafter abbreviated as BT) request is issued via the path 55. The BT request is sent to the main memory 1, and the read data is sent to the path 56 and the selector 9.
The command is written to the instruction buffer 3 through the . The comparison circuit 6 also stores the start addresses of n instructions stored in the instruction buffer 3.

(2) If the target instruction is not in the instruction buffer 3 but exists in the C buffer 2, the requester 8 sends it to the C buffer via the path 57.
The data on the buffer 2 is read and transferred to the instruction buffer 3 through the path 58° selector 9.

Directly from the instruction execution control unit 4 to the requester 8, the main memory,
When the C buffer transfer command is issued, the requester 8 issues a main memory reference request (hereinafter referred to as a BT2 request) to the main memory 1 through the path 60.

All of the above-mentioned main memory reference requests are issued to the main memory after undergoing logical-to-real address conversion. Since this address conversion process is not directly related to the gist of the present invention, a description thereof will be omitted.

Data read from the main memory in response to the BT2 request is written to the C buffer 2 via the data buffer 10. At the same time, the start addresses of m'n instructions stored in the C buffer 2 are stored in the entry section of the comparison circuit 7. The data buffer 10 receives data that is serially read out from the main memory in groups of n pieces to the C buffer 20.
An operation is performed to set m−n instructions in the column storing them.

FIG. 2 is a block diagram showing the configuration of the instruction buffer 3 and comparison circuit 6 shown in FIG. 1. The example in FIG. 2 shows the configuration of an n-3, 2-column instruction buffer. In Figure 2, logic parts that are the same as in Figure 1 are given the same numbers, and paths that are shown as a single path in Figure 1 can be used for different purposes (for example, for command and address signals). ), the subscripts a, b, and c are added. In addition, to simplify the drawing, an east line representation is used, and this is indicated by a thick solid line. The same applies to FIG. 3 and subsequent figures.

In FIG. 2, an instruction read request (address) from the instruction execution control unit 4 is set in the register 100 through a path 50a. Address on register 100 is 100a
Assume that the section 100b indicates the column address of the instruction buffer, and the section 100b indicates the intra-column address. A flip-flop 101 is a flip-flop that indicates whether an instruction in a column can be used (valid or not), and a value of "1" indicates validity. Register 102 holds the address of the instruction stored at the beginning of the column. The register column 103 consists of three consecutive instruction addresses in the register 102.
holds instructions. The flip-flop 101 and registers 102 and 103 are called columns. The logic circuit 104 is
It is a cyclic counter, and when it exceeds the number of columns minus 1, it wraps around to 0°.The output of the cyclic counter 104 is input to the switching circuits 105 to 107 through a path 150. .

Paths 151 to 154 are signals sent from the selector 9 shown in FIG. 1, and are advance, write enable, address, and data signals, respectively. In FIG. 1, these signal lines are abbreviated to one signal line. Each of these signals is transmitted to switching circuits 105 to 107.
distributed to each column by

The instruction address set in register 100 is checked by comparison circuit 110 to see if it matches the instruction address on register 102, and the result is sent to AND circuit 111. The output of flip-flop 101 is also sent to the same circuit 111, invalidating comparison with addresses in unset columns.

When the output of the AND circuit 111 is "°1", it indicates that an instruction corresponding to the instruction address on the register 100 exists in the corresponding column.

The output of AND circuit 111 is encoded by encoder 112 and sent onto path 156. pass 156
When the above signal is "0", it indicates that there is no instruction corresponding to the instruction address in the instruction buffer 3. The code signal on path 156 acts on selector 113 to select data from the column containing the instruction and send it on paths 157-159.

The 100b field in register 100 holds the intra-column address. The address acts on the selector 114 via the path 160, selects one of the paths 157-159, and sends the data to the register 116. The output of register 116 is sent to instruction execution control unit 4 in FIG. 1 through path 52.

When the signal value on the path 156 becomes "0°", indicating that there is no instruction in the instruction buffer 3, the comparison circuit 117 outputs "1" on the path 53a. pass 53
This signal on a indicates a BT request and is sent to NoriQuesta 8 in FIG. Data in field 100a of register 100 is similarly sent to requester 8 via path 53b.

The instruction buffer shown in FIG. 2 allows instructions to be read out after the same delay time no matter how branched within the range of instructions included in the number of columns implemented.

When a signal to clear the contents of the instruction buffer 3 is sent on the path 50b, the contents of the flip-flop 101 are
It is reset to "0°" and all entry addresses are invalidated.

A block diagram showing the configuration of the C buffer 2 is shown in FIGS. 3-4. Since it is desirable that the C buffer 2 has a larger capacity than the instruction buffer 3, an example is shown in which it is realized using a memory element. Since the write operation and read operation of the C buffer 2 are performed in parallel, when using a memory element, it is necessary to make the buffer logic two-sided or to operate it in 1/2 machine cycle. Here, a case where the machine cycle is reduced to 1/2 will be explained as an example.

■The machine cycle is divided into two, the W/R cycle, and the logic section that operates in the W cycle is indicated by [stock], the logic section that operates in the R cycle is indicated by ■, and the section that operates in both cycles is indicated by ◎.

The write operation to the C buffer 2 will be explained using FIG.

Here, m=3.

Write data to the C buffer 2 is sent from the main memory 1 to the path 260 in n instructions in units of one machine cycle. The advance signal for path 260 is
It is 1. The logic circuit 210 is a cyclic counter, and the 7 advance signal on the path 261 causes O→1→2→
The value changes like 3 → 0 →. The output of the counter is
It is output on path 255. cyclic counter 21
0 sends a pulse on path 256 when the value changes from 3 to 0. The entry address of the C buffer on path 260 is set in register 211. pass 256
The data on the register 211 is transferred to the register 212 and sent to the switching circuit 213 by the above pulse signal. A signal on path 254 indicates which register 202 to write this entry address into. As a result, the entry address sent on path 260 is written to one of the registers 202.

On the path 262, n instructions to be written to the C buffer are sent from the main memory 1. The data on the path 262 is stored in the register 214 and then sent to the switching circuit 215, and the output of the cyclic counter 210 on the path 255 causes the data on the three RAM elements 201 mounted corresponding to m-3 to be sent to the switching circuit 215. sent somewhere.

The advance signal on path 261 is input to AND circuit 217 via register 216.

The signal on path 253 is a signal indicating the W/R cycle. Here, the W cycle is represented by the value "1".

Therefore, data is written to the RAM element 201 during the W cycle of one machine cycle.

Flip-flop 21B indicates whether the instruction sequence in the column of the C buffer was used while the interval timer 230 was outputting.

Here, the value “0” indicates that the value “°1°” was used.
Let us indicate that was not used.

The flip-flop 218 is an interval timer 230
When output is output, "o" is cleared all at once. Also,
This flip-flop 21B is set to 1.degree. when a signal is sent on path 250 from the C buffer read logic section (FIG. 4) indicating that data has been read.

The output of flip-flop 218 is encoded by encoder 219 and sent on path 263. 22
0 is a random number generator whose output is sent out on path 264. When the outputs of the encoder 219 are all "0", that is, when any column of the C buffer is used, the output of the comparison circuit 222 is "1", and the selector 221 connects the paths 264 and 251. Therefore, when data on a column of the C buffer is replaced by a signal on path 251, performance improvement cannot be expected even if too much data is written to the C buffer.Management of the C buffer is the responsibility of the user. must be issued.

Data on path 251 is subjected to W/R cycle selection on read address data bus 252 and selector 200 from FIG.
address information. Data on path 254 is also sent to FIG.

FIG. 4 shows a block diagram of the read portion of the C buffer. An address for reading the C buffer is sent on the path 57, and this address is sent to the register 230.
is set to The a field of register 230 is C
It corresponds to (can be compared with) the start address of the instruction string in the column in which the instruction string to be read from the buffer is stored.

The b field indicates which block of the m divided C buffers should be read.

The C field is not used in the logic of FIG.

The address of the a field of register 230 is path 280
The data is sent to the comparison circuit 232 and compared with the column address on the register 202. flip flop 231
is whether the column address of the C buffer is valid or not,
In other words, it shows whether the instruction string in the column can be used or not. Here, it is assumed that it is valid when the value of the flip-flop is "1". Sent out.

The signal on path 250 is encoded by encoder 234 and sent to selector 200 via path 252. The selector 200 outputs the address of the RAM 201. This logic has already been explained in FIG. R
The data (instruction string) read from the AM 201 is selected by the selector 235 based on the information in the b field of the register 230 and sent onto the path 288.

The signal on path 261 is selected by switching circuit 237 and sent to flip-flop 23 corresponding to the write column.
Perform set 1.

Path 285 is a C buffer purge path from instruction execution control circuit 4 in FIG.

When the output of the encoder 234 is “0°”, that is, the instruction sequence to be read out is not set in the C buffer, the output of the comparison circuit 236 is “1°”, and the BT2 request is sent onto the path 54. .

FIG. 5 is a block diagram of the transfer processing section to the C buffer of NoriQuesta 8 of FIG. 1.

In FIG. 5, an instruction to transfer data from instruction execution control circuit 4 to C buffer is issued by sending a signal on path 59a. This instruction signal is the register 3
Stacked at 00. The flip-flop 301 is [
It holds the value "l"' when the "data transfer instruction to C buffer" is being executed. At this time, subsequent data transfer commands on register 300 are not accepted. The data transfer instruction is completed and a completion signal is sent on path 256 (
(see FIG. 3) and the flip-flop 301 are reset, and the subsequent data transfer command is set in the register 302 and executed. On the other hand, the address of the transfer instruction is sent to the requester via path 59b. pass 59
Signals on c and d indicate the number of transfers (value of m) and order, respectively, and are held in registers 330 and 331. The register 303 stores the value of one data transfer amount (n (B)). When the signal value on the path 354 reaches “1”, the counter 310 is reset and the selector 30
4 sets the data in the register 306 to the register 312 through the adder 311.

Also, the data on registers 330 and 331 are also stored in register 33.
Moved to 2,333. In the next cycle, register 31
The data (address) on 2 is returned to adder 311 through path 351. In the next two frames, the signal on the path 354 becomes "0", and the selector 304 transfers the data in the register 303 to the adder 311.
Send to. The AND circuit 313 receives the pulse "TB" from the timing base from the path 352 and sends out a set signal to the register 312 every machine cycle. An address for accessing main memory 1 is generated.

This address is transferred to register 33 by comparison circuit 310.
2, and if they match, the comparison circuit 310 sends out an output value “1”.Register 332
How many times to C buffer?・Information on whether to transfer data n (B) is stored. The output of comparison circuit 310 is inverted by inverter 315 and input to AND circuit 313 through path 353. Thereby, control is performed so that no addresses are generated after the number of addresses required for data transfer has been generated.

The output of flip-flop 302 is sent to main memory 1 through path 60a. When this output is "0", data on paths 60b and 60c is treated as invalid data.

The outputs of registers 312 and 333 are respectively connected to path 60b.
, c to the main memory 1. This path 60b,c
The above data indicates an address and an order, respectively.

FIG. 6 is a diagram showing a portion of the logic section of the Quester 8 of FIG. 1, which is related to data transfer between the C buffer and the instruction buffer when an instruction buffer read request occurs during data transfer to the C buffer.

In FIG. 6, when an address is sent out on path 60b, that address is transferred onto registers 400-402 every machine cycle. At this time, it is assumed that the BT request request address is output from the comparison circuit 6 on the instruction buffer side to the path 53b. The addresses are stacked in a register 403, a comparison circuit 404 checks whether the addresses match, and the result is sent to an encoder 405. The result encoded by the encoder 405 is stacked in the register 406 and held until the data to be written to the C buffer is read from the main memory l.

The process of writing to the C buffer is as explained in FIG. 3, but it is necessary to transfer the write data to the instruction buffer side at the same time as writing to the C buffer. For this reason, the third
The output path 268 of the switching circuit 215 shown in the figure is connected to the registers 407 to 409 so that m pieces of write data are sequentially set in the registers 407, 408, . . . .

The output of the register 406 acts on the selector 411, and among the data on the registers 407 to 409, the comparison circuit 40
4, only data corresponding to the matched address is sent to the register 410. On the other hand, when the outputs of the two comparison circuits 6 and 7 on the instruction buffer side and the C buffer side both indicate that "the address on the register 403 has not been entered,""1" appears on the paths 53a and 54. Since this is outputted, an AND circuit 412 performs a logical product on this and the result is held in a register 413. The output of register 413 is used as a register 4100 set signal. The signal value on the path 53a of the comparator circuit 6 on the instruction buffer side is “1”.
"", when the signal value on the path 54 of the comparison circuit 7 on the C buffer side is "0", that is, when there is no target instruction sequence in the instruction buffer and there is a target instruction sequence on the C buffer. , is detected by an AND circuit 414, and is encoded by an encoder 415 together with the output of the AND circuit 412.

From the comparison circuit 7, the output of the AND circuit 414 is ``1''.
In this case, the instruction sequence read from the C buffer is sent out on path 288. Therefore, the selector 416 selects the C buffer write instruction sequence on the main memory side and the read instruction sequence from the C buffer on the path 288, and one of them is sent to the instruction buffer via the path 58.

FIG. 7 is a block diagram of the instruction execution control section 7 of FIG. 1.

In FIG. 7, instructions are sent from the instruction buffer over path 52. It is assumed that commands and data are propagated on the paths 52a and 52b, respectively.

The data on path 52b is set to 501 in the register. The data in the register 501, that is, the command, is sent to the decoder 5.
03, and a logic circuit 504 generates orders necessary for executing the instruction. Here, as information necessary for instruction execution, we consider the busy state of resources such as arithmetic units that execute instructions and registers for writing instruction results.

Arithmetic unit.

The registers are collectively called resources, and a flip-flop 507 is provided to manage the busy state of these resources. That is, the flip-flop 507 is
When it is 1°, it indicates that the corresponding resource is busy.

In FIG. 7, information for executing an instruction in a logic circuit 504 (one piece is used for simplicity) is created, and a path 550
When the information is sent to the top, this information is sent to the selector 5.
Flip-flop 507 that acts on 08 and is necessary for instruction execution
information is sent out on path 551. The information is inverted by an inverter 509 and input to an AND circuit 510. On the other hand, an instruction signal indicating that the instruction on the register 501 set in the register 500 is valid is sent to the AND circuit 5.
02, is set in register 505, and passes through path 55.
2 to the AND circuit 510. That is, AND
When the output of the circuit 510 is "I II", it indicates that the instruction is executable. When the output of the ANI (ANI) circuit 510 is "0", that is, the instruction cannot be executed, no instruction successive request is generated on the path 50, and the register 501 is not set. Further, the output of the AND circuit 502 is always "0" and instruction execution is inhibited.

When an instruction execution instruction is issued on the path 50, the flip-flop 507 corresponding to the resource necessary for executing the instruction is set to "1" via the switching circuit 506.

This flip-flop 507 receives a free signal outputted from the resource side when the instruction processing is completed through a path 560.
It is not reset to “0” until it is sent via the .

When the instruction execution control method shown in Fig. 7 is used, when the processing of one instruction requires multiple stages, it is possible to execute the following instruction while the preceding instruction is being executed unless the resources are busy. can be executed. That is, even if data transfer from the main memory 1 to the C buffer requires a long machine cycle, since instructions can be executed in parallel, there is almost no effect on instruction execution.

The embodiment of the present invention described above is logically contrived so that the transfer of an instruction sequence from the main memory to the C buffer does not prevent normal instruction fetching, so that the introduction of the C buffer does not have any adverse effects.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to speed up instruction reading by using two buffers with different properties, the instruction buffer and the C buffer.

In addition, by reading multiple instructions from the main memory onto the buffer at a time using the instruction buffer, the efficiency of data transfer between main memory buffers is improved, and the efficiency of the buffer with respect to the continuity of addresses of instruction read requests is improved. By adopting a logical configuration that enables reactions and allows access to instructions in an instruction buffer in any order, it is possible to significantly speed up intra-buffer branch processing.

Furthermore, the C buffer allows frequently used routines to reside in the buffer, and speeds up branch processing within a program that does not fit in the instruction buffer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a data processing device according to the present invention, FIG. 2 is a block diagram showing the configuration of an instruction buffer section, and FIGS. 3 and 4 show the configuration of a C buffer section. Block Diagrams FIGS. 5 and 6 are block diagrams showing the structure of the Questa section, and FIG. 7 is a block diagram showing the structure of the instruction execution control section. 1・・・・・・・・・Main memory, 2・・・・・・・・・C
Buffer, 3...Instruction buffer, 4...
......Instruction execution control section, 5...
Instruction execution unit, 6.7... Comparison circuit, 8.
......Requester, 9...Selector, 10...Data buffer.

Claims (1)

[Scope of Claims] 1. In a data processing device equipped with an instruction buffer, a logic unit that uses an instruction read operation as a trigger to transfer a plurality of instructions to the buffer in one main memory access, and reads the next instruction from the buffer; When a request is made to read an instruction that has not been entered in the buffer, a logic section that reads out multiple instructions from main memory at once again, and when the read instruction sequence does not fit into the buffer, automatically reads the instructions beforehand. A first instruction buffer that includes a logic section that erases a part of a read instruction string and writes a new instruction there; and a second instruction buffer that includes a logic section that loads the instruction string from main memory according to the instruction. A data processing device comprising: 2. The data processing device according to claim 1, wherein the data processing device is capable of executing instruction sequence transfer to the second instruction buffer and data processing in parallel. 3. The data processing device according to claim 1 or 2, further comprising a logic unit that invalidates the contents of the first and second instruction buffers. 4. The device further comprises a logic unit that detects, when an instruction read request is issued from the data processing unit, whether or not the instruction of the read request exists in the first and second instruction buffers. A data processing device according to claim 1, 2, or 3. 5. The instruction of the read request is transferred from the second instruction buffer to the first instruction buffer based on the detection result of the logic unit that detects whether or not the instruction of the read request exists in the first and second instruction buffers. 5. The data processing device according to claim 4, further comprising a logic unit that transfers a sequence of instructions. 6. Claims further comprising a logic unit that requests transfer of an instruction sequence to the instruction buffer from the main memory based on responses of the first and second instruction buffers to an instruction read request. The data processing device according to one of items 1 to 5. 7. When the instruction sequence transfer request issued by the logic unit that requests the transfer of the instruction sequence to the instruction buffer is incomplete, the data processing unit issues an instruction read request, and the instruction sequence transfer according to the request from the logic unit includes an instruction requested by the data processing unit, the instruction sequence requested by the logic unit is written into the second instruction buffer, and at the same time, the part including the instruction requested by the data processing unit is written to the second instruction buffer. 7. The data processing device according to claim 6, further comprising a logic unit having a function of transferring the instruction to one instruction buffer.