JPH0277138A - Connection structure of electronic component and electronic device using same - Google Patents

Abstract

PURPOSE:To simplify the assembling structure of an electronic device by providing spring properties or free deformation properties in all directions on horizontal and vertical planes, in order to connect electronic components like an LSI chip. CONSTITUTION:By using a wiring board 6 with a microlead, the electrode 10 of an LSI chip 11 is bonded by solder 10 via a microlead 7. In the case where the LSI chip generates heat and the temperature rises as high as about 80 deg.C as the result that the electrically connected wiring board is operated, the board stretches more than the LSI chip. As a result, deformation displacement difference is caused between the LSI chip and the board. As to the board with the microlead, the microlead itself deforms in the X and Y directions or in all directions on a horizontal plane, so that the stress can be released. Further, since the microlead has spring properties or can deform in the vertical Z direction, the chip can be completely brought into close contact with a cooling body 12 arranged on the rear (upper side) of the LSI chip. As a result, cooling effect of the LSI chip can be sufficiently maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and structure for interconnecting electronic components, and an electronic device using the same, and particularly relates to interconnection methods and structures for interconnecting electronic components, and particularly relates to interconnection methods and structures for interconnecting electronic components, and particularly for interconnecting electronic components such as LSI chips having a large number of fine connection terminals. The present invention relates to a method and structure for connecting electronic components suitable for connecting to a flexible structure of a substrate, and a structure of an electronic device using the same.

[Conventional technology]

Conventionally, the electrical connection methods for L8I chips are fi+ wire bonding method, (2) tape carrier bonding method (or TAB method: Tape Automated
(3) flip-chip bonding method (Reference 1: Nihei et al., Semiconductor Handbook, p. 128, Science Holum Co., Ltd., September 25, 1986).

Among the above three connection methods, methods (1) and (2) can only be applied to chips in which the input/output terminals of the L8I chip are located on the periphery of the chip (see Table 3: References). (from l). The reason for this will be explained in detail later.

On the other hand, (3I's 7 lip chip bonding method is L8I
The present invention can also be applied to a chip having a structure in which connection terminals are provided not only at the periphery of the chip but also over the entire surface of the chip including the center (hereinafter referred to as a grid-like terminal arrangement).

In this method, solder bumps with a height of about 100 to 125 μm are provided on the terminal surface of the LSI chip to be connected, the chip is placed on a wiring board, and the solder is reheated and melted to connect. This method is the C-4 method (8o1i
d Logic Technology) or C
CD method (Controlled Co11apse B
onding).

Figure 25 (Reference 2: Honda et al., High Density Mounting Handbook, P2S5, 1986)! A basic schematic diagram of the connection mechanism of the cCOB method is shown. In this CCD method, the connecting medium (solder in this case) does not extend (come out) beyond the width of the LSI chip in the lateral direction (horizontal direction). Further, one connecting medium (solder) does not spread much in the horizontal direction.

Therefore, it is advantageous to successively connect and mount a large number of LSI chips having a grid-like terminal arrangement adjacent to each other.

As an example of application of chip connection and disaster prevention using this CCD method,
Ultra-high-speed electronic computers that require large numbers of high-density implementations,
An example is IBM's TCM (The-rmal C).
(from Figure 24, Reference 2, p. 240).

As in the above example, electronic computers and high-end electronic devices require mounting of L8I chips with a large number of connection terminals. Especially in recent years, as shown in Figure 23 (from Reference 1),
The number of logic L8I terminals has increased significantly, and due to their high-density arrangement and power supply characteristics, they are becoming chip structures with grid-like terminals. Regarding LSI chips, as mentioned at the beginning, wire bonding method or tape carrier bonding method (hereinafter referred to as TAB method) has the following reasons.
cannot be applied.

The wire bonding method is a method in which thin wires of Au or M are drawn out and connected from the terminals of the L8I chip to the external periphery thereof, as shown in FIG. 22 (from Reference 2.P2O3). For this reason, a space is required around the outer periphery of the FI+ chip to draw out and thread the leads (wires), and basically there is no choice but to prepare extra space for connection. (2) Lead connections are made using a device called a wire bonder, but the lead wires (wires) are bare wires without insulation, and when many of them are connected to the terminals in the center of the chip, the wires come into contact with each other. do. For this reason, the wire bonding method is not suitable for connecting chips having a structure of high density and grid-like terminal arrangement, such as the logic LSI chip described above.

In addition, in the TAB method, Fig. 21 (Reference 1, p. 277
As shown in this figure, wiring leads are provided on a film (carrier), and the chips are connected through the leads together with the film.

This TAB method requires an extra lead portion as an adhesive margin for fixing the lead wire to the film, making it difficult to shorten the lead length. That is, in the conventional film carrier, the middle part between the outer lead and the inner lead is made longer, and the film is fixed and supported on the film base at that part.

In addition, the inch IJ IJ- cards are wired inward in a straight line. Therefore, LSI chips that can be connected to this are limited to LSI chips for memory and the like, which have terminals only on the periphery and have a relatively small number of terminals. However, logic LSI chips have an extremely large number of terminals (approximately 10
There are over 500 of them above). Furthermore, as described above, the terminals are not only arranged at the periphery of the L8I chip, but are also arranged in a grid pattern all the way to the center.

For this reason, it is not possible to connect a logic LSI chip with a lattice-like terminal arrangement using a configuration in which the inner leads are linearly wired inward in a plane as in the TAB method.

To summarize the drawbacks of the above two methods, fil L S
Requires extra space beyond the area occupied by the I-chip. (2) It cannot be applied to a chip having a structure in which terminals are arranged in a lattice pattern up to the center of the chip, such as a logic LSI chip.

For the above reasons, the above-mentioned CCB method is a representative example of a method that can connect and mount L8I chips, such as logic Li9I chips, which have terminal structures arranged in a grid pattern with high density, in a high density and compact manner. The only flip-chip bonding method used is

However, in the flip chip bonding method such as the CCB method, a direct connection is made using ball-shaped solder, and it is basically a connection method with a rigid structure.

For this reason, in recent years this method has come to have some inconveniences. The situation will be explained below.

Recently, in the field of high-performance electronic devices such as electronic computers, there has been a demand for the development of flexible structure chip connection technology for mounting LSI chips.

In this field, rigid structure connection methods such as the above-mentioned CCB method can no longer meet the requirements.

The reason why the L8I chip connection method with a flexible structure is required is related to the calculation speed, which is one of the most important performance aspects of an electronic computer, for example. In other words, when looking at the calculation speed from the computer hardware (equipment) side, L8I
It is determined by the performance of the board and the performance of the wiring board used to mount it.

Looking at recent trends in wiring boards, multilayer wiring boards made of ceramics (alumina, mullite, etc.) and using W (tungsten) or Mn (molybdenum) as wiring materials have been developed and put into practical use.

This allows LSI chips to be connected and mounted with high density, and is effective in shortening the increasing total wiring length. However, in terms of electrical signal transmission performance, there are the following unsatisfactory points.

(1) Ceramic substrates generally have a high electrical permittivity (alumina T: 9-10), so parasitic charges are generated at the interface where these seven wirings come into contact, which is a factor that delays the transmission speed of electrical pulse No. 4g. Become.

(2) W, Mo, etc., which are wiring conductor materials, are other metal conductors,
For example, it has higher electrical resistance than Cu (copper).

Therefore, the waveform of the electric pulse signal is deteriorated.

As a result, it is difficult to shorten the time between transmitted pulses,
In turn, this is the cause of impeding Pulse store name's ability to increase transmission capacity and speed.

Therefore, in order to eliminate the above-mentioned drawbacks, recently, wiring boards using Cu as the wiring material and organic materials with low electric permittivity, such as polyimide resin CZ3'), have been developed or are being used as the substrate material. There is a tendency to

However, in the above-mentioned high-performance wiring board, the coefficient of linear thermal expansion is larger than that of ceramics such as alumina, and the difference in coefficient of thermal expansion (hereinafter referred to as α difference) with 8i, which is the main component of the LSI chip, is 100 to 130×10”/ L: It's big.

Therefore, if the LSI chip is directly soldered to the wiring board as in the conventional L8I chip connection method, the following problems occur. In other words, when an LSI chip is fixed to a wiring board using organic matter and C1l, thermal stress is generated in the solder joints due to the large α difference, and the solder joints cannot respond to the strain caused by the thermal stress and are destroyed, causing the joints to break. This results in disconnection.

Therefore, when connecting an LSI chip to a wiring board with a large coefficient of thermal expansion as described above, a method that can absorb or alleviate the thermal stress strain caused by the α difference between the two is required, that is, an L8I chip connection method with a flexible structure is required. .

Furthermore, even if a conventional ceramic wiring board is used,
For example, the coefficient of thermal expansion of an alumina ceramic wiring board (
6O-65xlO-'/°C) does not perfectly match the thermal expansion coefficient of the ISI chip (30xtO-'/°C).

Especially recently, L8I chips have become larger (10m' → 16s).
-o), there is a tendency for the thermal stress strain due to the α difference to increase, and it is already difficult to withstand the thermal stress strain by connecting only with solder. For this reason, even when connecting an LSI chip to a conventional ceramic wiring board, an LSI with a structure that can absorb or alleviate the strain caused by thermal stress is required.
An I-chip connection method is required.

The above situation is summarized in Figure 20. In this Figure 20, the vertical axis represents the size of the LSI chip, the horizontal axis represents the α difference between the wiring board and the LSI chip (principal component 8i), and the diagonal line in the diagram represents the lifespan of the CCB connection method. indicates the limit value. This diagram was created based on the inventors' experimental results using the CCB connection method.

From the above, it is clear that the durability of connecting rigid structures simply by the COB method has reached its limit.

Based on the above, the shortcomings of the conventional and generally well-known L8I chip connection technology can be summarized as follows.

(Rewire bonding method and TAB method cannot be connected and mounted horizontally compactly.

(The 21CCB method cannot connect or mount flexible structures.

For these drawbacks of existing L8I chip connection technology,
In particular, for the purpose of solving the above-mentioned problem (2), a method described in, for example, Japanese Unexamined Patent Publication No. 110441/1983 has been proposed by Mr. Ehrfeld.

However, the method proposed above has the following problems.

The connection portion between the +11LSI chip and the wiring board does not have deformation (freedom) or elastic force (springiness) in the vertical (Z) direction.

This means that after connecting the L8I chip to the wiring board,
An inconvenience occurs at the contact between the back surface (non-electrical connection surface) of the L8I chip and the cooling body. That is, the L8I chips (plurality) connected to the wiring board are usually connected with some unevenness or inclination (rather than completely horizontal). Therefore, a gap (or poor contact) may occur at the contact interface between the chip and the cooling body. To compensate for this poor contact, a rod (heat dissipation stud) equipped with a spring mechanism is usually pressed against the back of the chip from the cooling body side (
(See Figures 19 and 24 from References 1 and 2).

However, this method reduces the cooling effect and complicates the structure of the cooling body.

On the other hand, the L8I chip is applied vertically (elastic force in the Z1 direction)
A connection method having spring properties has good contact properties and can simplify the conventional cooling body described above.

However, the conventional soldering-only connection method using the CCB method and the above-mentioned Ehrfeld connection method have little or sufficient elastic force.

(2) Ehrfeld's connection method requires two connections for each terminal on the chip.

That is, in the above-mentioned Japanese Patent Application Laid-open No. 61-110441, when connecting a chip to a substrate, two connections are required for each terminal of the chip, one at the top and one at the bottom. This increases the number of connection points, which is undesirable from the viewpoint of chip connection work, reliability of electrical connection, and electrical resistance.

This point is also one of the technical problems to be solved by the present invention. That is, in high-density packaging in which a large number of pins are mounted on one board, it is desirable to connect one terminal to a board electrode at one bump.

Fig. 18 shows the configuration of the connecting element when connecting the above-mentioned ale felt at two places [Fig. 18 (at is a perspective view % (b)
Figure 19 shows a top view] and a state in which the electrodes of the chip are connected to the substrate electrodes using this coupling element [Figure 19 (cl is a cross-sectional view]).In other words, the coupling elements are arranged in two parallel to each other. The pins 60a, 60b are connected to each other by a thin plate 60. In FIG. The other pin 60a is electrically connected to the electrode 64 of the chip 61 via the solder 63. Because of this configuration, one terminal 64 of the chip is the pin 60a of the coupling element.

It is connected to the conductor path 65 of the board through two points 60b, and the number of connection points is two.

For the above reasons, although the flexible structure connection method and 1.
It is desirable to complete the connection of the LSI chip by soldering.

In addition, in the Ehrfeld connection method, it takes a lot of energy to create a leaf spring (as described in
The problem was that the entire process was complicated and could not be easily carried out.

On the other hand, an attempt was made to connect the L8I chip to a more or less flexible structure, in addition to the Ehrfeld method, published in Japanese Patent Application Laid-Open No.
A method described in Japanese Patent No. 121255 has been proposed by Mr. Honda.

In this method, as shown in FIG.
Wires M71A, 71B are formed on the electric circuit element), and metal bumps (solder) 72A, 72 are placed at the tips of the wires M71A, 71B.
A method for connecting this L8I chip to the wiring board 74 is described. In addition, in this proposal, a film 73 (Pi
Q: It is written that the black variation strain (from the main text) is absorbed by the wiring film and metal bumps.

However, in this proposal, not only the following (1) to (4) are unclear, but also there is a drawback that there is no stretchability in a specific horizontal direction, as will be described later.

ill Wiring film 71 people, shape and dimensions of 7f#B (2
) Spacing, spacer formation, etching conditions (etching liquid bubbles for 9 hours, etc.) (3) Specific process conditions including the above fll, +21 +41 Quantitative evaluation results of the invention Therefore, (1) How much thermal strain When mechanical expansion/contraction (from the main text) occurs, how much should the dimensions (
width, thickness, length, overall shape, etc.). (2) It is difficult to plan work procedures such as preparation of chemicals, film formation, and etching to implement this proposal.

Furthermore, in this method, the wiring film 71A in FIG.
If the shape of 71B is rectangular, there is a drawback in the connection structure that there is almost no extensibility in the horizontal inner direction in the figure. That is, the solder bumps 72A and 72B in the same figure
However, for example, CCB soldering requires a temperature (approximately 270 to 330
In the CCB connection and cooling process, where the temperature drops from ℃ to room temperature,
The wiring films 71A and 71B have a structural defect in that they are subjected to severe tension (tension) toward the inside in the figure, leading to disconnection or disconnection.

Furthermore, a method different from the above has been proposed by Mr. Ohno (Japanese Patent Application Laid-Open No. 136830/1983). The first method is
It is shown in Figure 6.

However, even in this method, the soldered joints are forced to undergo severe tensile stress in a specific horizontal direction. That is, the conductor layer 80 in FIG. 16 extends horizontally outwardly as the substrate 81 is heated by chip heat generation or the like. However, the L8I chip 83 has a small elongation. For this reason,
The result is that the solder connections 82 are pulled horizontally outward. Therefore, similar to Mr. Honda's method described above, there is a structural drawback in that tension is generated in a specific horizontal direction (although the direction is opposite to that of the Honda method).

As described above, the method of Messrs. Honda and Ohno has a drawback in terms of the connection structure because it does not take tension relaxation into consideration in a specific horizontal direction.

[Problem to be solved by the invention]

As mentioned above, in the industrial field where L8I chips are electrically connected to mount and assemble high-end electronic devices such as ultra-high-speed electronic computers, (1) L8I chips that have a large number of connection terminals like logic LSIs (2) It is necessary to install a large number of chips in a row at a high density, and to connect the connections in a flexible structure in all directions. However, it can be summarized as follows.

1. The wire bonding method and TAB method are as described in (11) above.
- (2) cannot be satisfied.

2. The CCB method cannot meet the above-mentioned 13+ flexible structure connection requirements.

3. Mr. Ehrfeld's proposal (Japanese Unexamined Patent Publication No. 1104-1983)
41) has no freedom or springiness in the vertical direction.

4. Proposal by Mr. Honda and Mr. Ohno (Unexamined Japanese Patent Publication No. 57-121255
and 82-136830>, it does not have sufficient freedom or springiness in a specific horizontal direction.

5. Furthermore, Ehrfeldt's method described above involves many difficulties in its implementation.

Accordingly, the first object of the present invention is to solve problems 1 to 5 above. In other words, with a simplified process,
The object of the present invention is to provide a method for connecting an L8I chip to a flexible structure, a connection structure that has free deformability or springiness in all horizontal and vertical directions, and the technical conditions necessary to implement the method.

A second object of the present invention is to provide L connected by the flexible structure chip connection method achieved by the first object of the present invention.
By using an SI chip mounting board, it is possible to simplify the assembly of electronic computers, etc. and the structure of the cooling unit, and also to ensure that the LSI chip connection part of the electronic device is not subjected to cooling and heating cycles due to the operation of starting and stopping the electronic device. Another object of the present invention is to provide an electronic device in which the solder joints of an LSI chip do not overheat due to thermal stress.

In addition, the flexible structure connection method of the present invention overcomes the inconvenience caused by the difference in thermal expansion coefficient between the L8I chip and the wiring board for mounting LSI chips in high density, including ultra-high-speed large-scale electronic computers. Applicable to all electronic equipment and devices that require

In order to achieve its object, the present invention consists of a plurality of difficult conditions to be overcome as described below and a plurality of inventive technical elements for overcoming the difficulties.

Below, we will summarize the difficult conditions to be overcome, that is, the technical problems to be solved in order to achieve the purpose of the present invention.

〔assignment〕

111 To electrically connect the LSI chips to be mounted.

The space required for wiring connection must not be horizontally expanded by the size of the chip due to the wiring used to connect the chip.

121 By the wiring connection method that satisfies the conditions of 111,
To connect terminals of an L8I chip to be connected to terminals of a wiring board provided almost vertically facing each other while minimizing loss in electrical characteristics.

(3) The above-mentioned conditions of fi+ and (2) are satisfied, and the above-mentioned connection portion or connection structure has flexibility or springiness in all horizontal and vertical directions.

(41 satisfies the conditions (1), (2) and (3) above, L
When connecting the SI chip and the wiring board, the connection must be completed at one connection point for each terminal of the chip.

(5) Above (1), +21, +31 and (4
To develop and establish technical means that satisfy the conditions set forth in item 1 and allow easy implementation of the connection method.

(6) By satisfying each of the above items, it is possible to obtain an electronic device in which the connecting portion of the electronic device is mounted with a board on which an LSI chip is connected and mounted, and can withstand cooling and heating cycles.

(7) When assembling the electronic device, by using the connection method, the assembly structure of the electronic device does not become complicated, but rather has the effect of being simplified.

(8) The electronic device must have an L8I chip connection method and structure that satisfies all of the above items, and a structure of the part suitable for storing or assembling the L8I chip mounting board in the electronic device.

[Means to solve the problem]

In order to solve the above-mentioned problem, the present invention has been implemented based on the following policy. Hereinafter, before describing specific solutions, the development policy that led to the creation of the present invention for each of the above-mentioned problems will be described.

〔policy〕

For problem (1), in order to prevent the connection part from expanding in plane compared to the size of the chip to be connected, the medium for connection (hereinafter, in the present invention, this connection medium is referred to as a micro-lead) is used to horizontally connect the chip. The structure should be located within the size range. The installation position range of this micro lead is different from the lead of the TAB method described above (see FIG. 21, in which the lead is extended and installed outside the range of the chip size in the TAB method).

For problem (2), the microphone Q IJ-de uses a metal with excellent electrical conductivity, and also uses a structure in which it connects three-dimensionally toward the terminals of the wiring board, which are provided almost vertically facing each other. .

For problem (3), the micro-leads are bent or turned in order to have all kinds of flexibility or springiness in the horizontal direction, and the micro-leads are shaped in a space in order to have flexibility or springiness in the vertical direction. The structure is in a floating state.

Regarding Section 1 (4), one end of the microphone OIJ-do must be connected to a through-hole conductor or conductor electrode portion on the wiring board side.

For issue (5), for example, a wiring board with a microphone () and IJ-board having the structure described in (1) to (4) above can be manufactured by ordinary film forming methods, plating methods,
It can be made by combining processes such as etching and ordinary metal materials.

The above is a description of specific means for achieving the above.

[Specific measures]

Figures 12 to 14 show examples of the shapes of the microleads proposed above. Here, the thickness (height) of the lead should be less than or equal to the horizontal direction (lateral direction) so that it has appropriate (just enough) springiness in the vertical direction, and micro leads can be easily formed by etching. (Later discussion)
These are the dimensional conditions for

Now, assuming Cu as the micro lead material, the 12th
Spiral shape as shown in the figure (line width 50 μm).

The effect (life of solder joints) of using micro leads with a space width of 50 μm, a spiral diameter of 300 μmφ, and a thickness of 20 μm will be estimated using the finite element method and a joint solder life estimation formula.

Setting conditions (1) Thermal expansion coefficient of used parts (s= x 10-'
/℃) and dimension missing L8I chip...1==30 (0 to 80℃) Dimensions = ioxto resistance (connection part, L = length x 10) (2) Operating temperature range and cooling/heating cycle time 0℃ ~80℃ (ΔT)
, 1 cycle/1 day The results calculated under the above conditions are shown in FIG. (However, the Young's modulus of solder is 31
7Ke/iw", Young's modulus of Cu is 6000-120
00Kf/- was assumed. ) The resiliency constant of the microlead shown in Fig. 11 is 29 to 571/M in the vertical (z) direction;
There are 100 to 380 # corridors in the horizontal (x, y) direction.

Also, the displacement difference Δy between the chip and the wiring board due to cooling and heating =
+13μm, maximum equivalent strain Δεeq of solder connection part = 0.
3 to 0.5%, the lifespan of solder joints will be 26%.
It was estimated that it was ~49 years ago.

From the above, it can be predicted that the service life is sufficient and that it is effective compared to the case where the micro lead is not used, which would be unsustainable.

Note that the above service life is under the cooling and heating cycle conditions indicated by diagonal lines (11) in FIG. 20, and under normal cooling and heat usage conditions, the above service life is extended 2 to 3 times.

In addition, as a result of analyzing the electrical characteristics separately from the above, the self-inductance was 0.42nH (nanoHenry).
Hereinafter, the resistance is about 12 rnΩ or less, and there is no particular problem in using it as an electrical connection medium.

As described above, by using a highly conductive metal such as Cu as a material, a spiral-shaped (thinly wound or spiral-shaped) microphone □ which is floating in the middle (however, one end may be fixed) By connecting the LSI chip and the wiring board via the IJ-board, the basic structure of the flexible structure connection intended by the present invention can be obtained.

Below, the structure of the microphone OIJ (dimensions and shape) will be explained.

This section outlines how to create a floating state.

First, the micro-lead group (a large number) has the size of an LSI chip, for example, 1 for a 10-o chip.

i.

The material used for the above-mentioned micro-leads may be any ordinary metal with good conductivity, but consideration should be given to the coefficient of thermal expansion, springiness (modulus of elasticity), ability to withstand repeated deformation, and processability such as etching. Then preferably Aj, C
These are metals such as u, Au, Ni, Or, etc.

Next, a method of forming the micro-leads with one end directly bonded to the wiring board and the other end floating in space will be described. This method was clarified by the inventors through various experiments conducted for the purpose of the present invention.

9 and 10 are diagrams of the principle of the above method.

This method involves passing through the contact hole portion of the wiring board 6 shown in FIG. 9 where the through-hole conductor 4 and the micro-lead are bonded, and forming the micro-lead itself via a metal layer 18 that is closely bonded to the through-hole conductor. It is made of a material layer of the lift-off layer 14- which supports this, and is created by removing the material layer 14- which supports it during or after the formation of the microphone OIJ-dead by etching. (C in Figures 9 and 10) That is, the micro-lead having a structure floating in space according to the present invention has a metal (C) used for the micro-lead on the wiring board.
For example, it can be easily produced by applying a void forming film which is easier to dissolve with chemicals than Cu (Cu), and then forming micro leads thereon by plating and etching. Details of this manufacturing method will be described in Examples. In this specification, the film material for forming the void portion is referred to as a lift-off material, and the film thereof is referred to as a lift-off film or a lift-off layer, as described above. Furthermore, in the method for manufacturing a wiring board with micro leads of the present invention, selection of the above-mentioned lift-off material is important. In the present invention, when Cu is used for the micro lead, the following lift-off materials can be used. The lift-off material of the present invention only needs to be more soluble than the material used for microleads.

fil At or AA-st +21 MIO +31 CuO +41 AIN (51B20.S i Om-based glass (6) Organic substances that dissolve in organic solvents It easily dissolves in alkaline chemicals that are difficult to remove, and is soluble in hot water and organic solvents. The lift-off film can be removed with a solvent.

In other words, through this process, the micro-lead is left floating in space with one end connected to the conductor portion of the wiring board. The present invention was made possible by discovering and employing this favorable selective etching process and conditions.

Furthermore, the following metals can be used to bond the micro-leads to the through-hole conductors of the wiring board.

+11 Ni or Ni alloy +21 Au or Au alloy 131 Cr or C alloy The above metals are selected depending on the 9 metals of the micro leads to be joined and the through-hole conductors of the wiring board, but any metal may be used as long as it is compatible with each other. These bonding metals are extremely effective when the through-hole conductor is W or Mo.

Furthermore, the metal used for the micro lead can be used as long as it is a good conductor, but if Cu is used, for example,
Other effects can be obtained by wrapping this in a sandwich-like manner with Cr or the like. This will be described in Examples. Here, I would like to mention just one of its effects: L8 to the micro lead.
It serves as a solder dam when connecting I-chips by soldering. That is, since the Au22 provided as a solder bump is very easily wetted with solder, soldering can be easily performed.

On the other hand, in the Cr19 part other than λU, Or does not wet with the solder, so it serves to prevent solder from adhering to unintended areas.

Note that the above-mentioned bonding metal does not necessarily need to be used when the through-hole conductor is Cu and the microphone Q IJ-board material is Cu, as shown in FIG. In this case, instead of the Cr19 for the solder dam, the surface of the microphone □ IJ-doped Cu other than the Au bump can be covered with a dispersion film 26 to fulfill its role. Details of this method will be described in the Examples.

By using the specific technical means described above, a wiring board with micro leads, which is the first part of the present invention, can be obtained by taking the following steps.

That is, the step of preparing a wiring board consisting of a multilayer wiring structure in which an electrode group is formed on the surface on which at least electronic components are mounted; forming a whole blood lift-off material coating on the wiring board, and bonding the conductors; step of forming a contact hole for the second part: step of providing a conductive layer for forming a microphone Q IJ on the entire surface including the top of the electrode; then a step of forming a conductive layer for forming a micro lead;
A resist film is formed on the electrode, a bent or spiraled micro-lead pattern mask is placed so that one end of a predetermined micro-lead is located on the electrode, and exposed and developed. forming a micro-lead resist pattern; etching the micro-lead forming conductive layer using the resist pattern as a mask; and then dissolving and removing the lift-off film and the resist pattern. A wiring board with micro leads can be created by this method.

By the above method, a wiring board with micro leads can be easily obtained. Next, a method of connecting LSI chips using this will be explained.

The lead end (L8I chip connection part 8 in Figure 12) of the wiring board with microphone Q IJ-do prepared in the above method and the LS
Align the solder balls (see Figure 25) already provided on the connection terminals of the I-chip using a half mirror, and then bond the LS using the normal face-down bonding method.
Connect the I-chip. The connection temperature at this time is 200 to 330 DEG C., which is the melting point of the solder provided on the LSI chip.

With the above steps, the L8I chip can be connected to the microphone OIJ- of the wiring board.
Figure 5 shows the state in which it is connected to the board. The figure shows a cross-sectional view of a part of the same, where 6 is a wiring board, 4 is a through-hole conductor, 7 is a micro lead, 24 is a cavity, 1O is solder, and 11 is an LSI chip.

With the above, the above-mentioned problems (1) to (5) can be achieved.

Next, there is the problem (6) mentioned above, that is, the durability of the connecting portion of the LSI chip against cooling and heating cycles. This can be proven from the stress analysis described above and the results of the thermal cycle test described in future examples.

The first object of the present invention can be achieved by the method described above. The second objective is achieved by completing the first objective, which is a flexible structure connection method.

That is, the heat dissipation stud of the cooling body in FIG. 2(b) can be omitted. In FIG. 2(b), the microphone 017-board 7 has a spring property in the vertical direction.

Therefore, the back surface of the L8I chip 11 can be completely pressed against the wall surface of the cooling body 12 and come into close contact with it. As a result, heat dissipation studs (see FIGS. 19 and 24) can be omitted.

[Effect]

In the above-mentioned wiring board with micro leads, even if the difference in coefficient of thermal expansion between the LSI chip and the wiring board is large, thermal stress generated at the solder joint can be reduced. That is,
Now, as shown in FIG. 2(b), using the wiring board 6 with the microphone OIJ door, connect the L8 through the microphone OIJ door.
Electrodes (not shown) of the I-chip 11 were bonded with solder 10. In this case, the wiring board 6 has a large coefficient of thermal expansion, and the LS
The I-chip 11 is small. Therefore, when a wiring board (hereinafter referred to as a module) on which an LSI chip is mounted and electrically connected operates, the LSI chip generates heat and reaches a high temperature (~80°C), the board side It stretches larger than the tip. As a result, a deformation displacement difference occurs between the Li9I chip and the substrate.

Conventionally, this displacement difference has destroyed some parts of the solder on the LSI chip. However, the microphone Q IJ-
In the wiring board with leads, the micro leads themselves are deformed in the X and Y directions or in all horizontal directions by the amount of the displacement, thereby making it possible to relieve stress. In addition, this micro lead can also be springy or deformable in the vertical (Z) direction, so
The chip can be completely brought into close contact with the cooling body 12 installed on the back (upper side) of the LSI chip. As a result, L8I
A sufficient chip cooling effect can be ensured, the heat dissipation stud with a complicated structure proposed in the past can be omitted, and the cooling body can be simplified.

Furthermore, the present invention has a structure in which one end of the micro lead is generated directly from the conductor part of the wiring board [Fig. 2(b)]
9]. Therefore, the connection of the LSI chip is completed by joining the solder 10 at one location per one terminal of the chip.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 15 and 1 to 2.
This will be explained using a table.

Example 1. Formation of Microphone Q IJ-Do on a Wiring Board: Part 1 FIG. 1 is a sectional view showing the structure of a board main body 6 which is a starting point for forming a wiring board with micro leads. In this example, the base layer 2d is made of alumina ceramics, and the interlayer insulation layers 2a, 2 are made of polyimide heat-resistant resin on top of the base layer 2d.
This figure shows the board main body consisting of a multilayer structure with b and 2c. External terminal pins 5 for signal output, power supply, grounding, etc. are implanted on the back side of the ceramic base layer 2d, and on the surface thereof. A wiring pattern 3c, a through-hole conductor 4 inside, a pin 5, a surface circuit pattern 30, and each circuit pattern 3a of the upper layer 2a, 2b, 2c,
3b, electrically connected to the through-hole conductor 4.

That is, circuit patterns 3a, 3b are provided on the surfaces of these interlayer insulating layers 2b, 2c in the same plane direction, and vertical through-hole conductors 4 are provided inside to interconnect the upper and lower layer circuits. An electrode 41 to which a micro lead is connected is exposed on the surface 1 of the uppermost insulating layer 2a.
are electrically connected to the lower layer circuit patterns 3a, 3b, 3c and the through-hole conductor 4 through the internal through-hole conductor 4, respectively. Note that circuit pattern 3. Through-hole conductor 4. The external electrodes 41 are all made of copper (C
u).

Next, a microphone □ I is placed on the electrode 41 of this wiring board main body 6.
The process of forming the J-door will be explained using the process diagrams shown in FIGS.
An enlarged cross-sectional view of a nearby through-hole conductor 4 is shown. Here, in FIG. 3(a) 4": L, immediately after creating the above wiring board 6, before the Cu surface exposed surface electrode 41 at the upper tip of the through-hole conductor 4 is oxidized, a micro lead is placed on this electrode 41. It is a process diagram in which a dental membrane 13 is formed as a bonding material to a thickness of about 0.3 μm.

This Ni film 13 was formed by sputtering using a mask with holes provided in alignment with the exposed electrodes 41 of the through-hole conductors 4 of the wiring board. The diameter of this through-hole conductor was approximately 100 μm, and the mask diameter was slightly larger than that, 110 μm.

Next, as shown in FIG. 3(b), a dental film 14 was formed as a lift-off material to a thickness of about 5 μm over the entire surface of the wiring board by sputtering.

Next, an alkali-resistant resist (not shown) is coated and dried on the lift-off material 14, and Ni is etched using a photo-etching method.
The resist on the film 13 was removed.

Subsequently, the tooth membrane of the lift-off material 14 was removed from the Ni 1113 with two volumes of NaOH aqueous solution adjusted to 8% (weight percentage), and a contact hole 15 was made, washed with water and dried, and a third A wiring board in the state shown in Figure (cl) was obtained.

Next, as shown in FIG. 3(d), Cr
The film 16 was formed to have a thickness of 1000λ and Cu117 was formed to a thickness of 2 μm over the entire surface by a spun ring method.

Furthermore, the thickness of Cu was increased to 2 by electroplating on this Cu film.
After forming the Cu film layer 18 thickened to 0 μm, Cr
A thick film 19 of 1000λ was formed by sputtering. The state at this time is shown in FIG. 3 (el).

That is, here, Cr-Cu-Cr is in a sandwich state, and is bonded to the Ni film 13 formed on the upper surface of the through-hole conductor, and is formed over the entire surface of the wiring board. This Cr-Cu-C
The thick film r will be used as a conductive layer for forming the microphone QIJ-de itself by etching as will be described later. In addition, it has a three-layer structure that can prevent the micro-lead from curling.

Note that Ni, AM, Cr, Cu formed above
The film formation conditions by the sputtering method were under a pressure of about 0.2 Pa in an Ar air flow, and the Cu plating was performed by electroplating using an aqueous solution of copper pyrophosphate. These equipment and conditions are now common industrial techniques and can be easily reproduced.

Cr-Cu-C on the wiring board prepared according to the above lζ
In order to remove residual stress from the r film, o, sh annealing was performed at 200°C.

Next, when the microphone Q lead is formed by etching the Cr--Cu--Cr film, the process moves to the step of applying an Au layer to the portion corresponding to the position of the chip connection portion (8 in FIGS. 2 and 12). This Au layer improves wettability with the solder for connecting the L8I chip 11, and also prevents surface oxidation of this contact portion in the air. Furthermore, in the Cr-Cu-Cr film, Cr is less wettable by solder than λU.

This prevents solder from flowing out onto the leads outside the connection area during the connection process, and prevents solder from adhering to excess areas (
solder dam). Below, Or-C
The process for providing the Au film only on the LSI chip connection portion 8 on the u-Cr film will be described.

First, a positive resist 20 for Au plating is applied and dried on the Cr film 19 shown in FIG. 3(e).

Next, align the center of the circle of the conductor joint part 9 of the micro lead pattern 7 in FIG. 12 with the center of the circle of the exposed electrode 41 of the through-hole conductor 4 of the wiring board, and At the position and size corresponding to the chip connection part 8 (circle with dotted line partitions: approximately 110μ)
mφ), the part 21 of the resist film 20 shown in FIG. A hole 21 is provided by.

Next, the Or film 19 in the same part was coated with 16fi% Ce(NOs
) + 2NH4NO1 aqueous solution at room temperature for about 2 etchings, and then the usual electroplating method was used to remove the etching process shown in Figure 3 (g
), an Au film 22 is formed, and a resist film 20 is formed.
was removed to obtain a wiring board in the state shown in FIG. 3 (hl).

Next, in order to form the micro lead 7,
A water-soluble negative resist was applied to the entire surfaces of the U film 22 and the Cr film 19 and dried (not shown).

Next, align the chip connection part 8 of the micro lead pattern shown in FIG. Align the centers of the circles, use the microphone □ IJ-dot pattern as a mask, a portion of which is shown in Figure 12, to draw a pattern group by exposure and development. A resist pattern with a pattern drawn thereon was formed.

Next, the Cr exposed by the resist pattern formation
+Cu-Cr film first, 165'Is Ce(N
O3) 42NH4NOB aqueous solution, Cr film with 2-, followed by 3i31 FeC4 (ferric chloride) aqueous solution for 50 s
Further, Cr was removed from the ecCu film by etching with the cerium nitrate aqueous solution to form a micro-lead group, a portion of which is shown in FIG. 12. That is, Cr −
A portion of the Cu--Cr film corresponding to the entire microlead was left, and all other portions were removed by etching. 23 indicates the removed cavity portion.

Next, the used resist pattern for microlead etching resistance (not shown) was removed with an NaOH aqueous solution adjusted to approximately pH 10.5, and then 15.3%
A of the lift-off layer at 55°C, 85-
114 was removed by etching, washed with water, and dried to obtain a wiring board with micro leads shown in Figure 3 (il). In this figure, 4 is a through-hole conductor, 7 is a micro lead, and 24 is a micro lead and a wiring board. It shows a gap between the micro lead and the wiring board, which is formed by removing the MM of the foot-off layer 14.

Microphone 0, which is one of the main parts of the present invention obtained as described above,
The specifications of the wiring board with 1J-cord are as follows.

(1) Dimensions of micro lead Lead band width...Curve...Curve...50an Lead band thickness...Curve...Approx. 2olIm Pitch between leads Curved/450 cotton (2) Number of micro leads: 1 Chip connection roar... 1ooo pieces The horizontal spring constant of the micro lead of this size is 45
The dimensions of the microlead according to the embodiment of the present invention, which is a layer with a vertical resiliency constant of 65φ, are not limited to the above-mentioned example, and are preferably in the following dimension range.

The thickness is 10 to 40 μm, the width is 40 to 70 μm, and the spring constant is 300 to 600 #/n in the horizontal direction, 40 to 90 t/n in the vertical direction, and the density is 600 to 1200 #/n in the vertical direction.

Example 2. Formation of micro leads on wiring board: Part 2 This example is a modified example of application of the present invention. Through-hole conductors 4 are vertically provided on an alumina substrate 42 shown in FIG. This was made by baking a perforated alumina substrate with Cu conductor paste.

The method for forming micro leads in this way is as shown in FIG.
As shown in FIG. 4(b), an M film 14 is applied as a lift-off material to a thickness of about 6 μm over the entire upper surface 1 of the
Form to a thickness of .

Then, an alkali-resistant resist (not shown) is applied to the M film 14.
After coating and drying the upper surface and removing the resist on the M film 14 portion on the through-hole conductor 4 by photoetching, sodium hydroxide (NaOH) adjusted to 8% was applied.
Remove the M film 14 on the through ball conductor 4 with fn liquid,
A contact hole 15 in the state shown in FIG. 4 (cl) is formed by washing with water and drying.
The diameter is approximately 110 μm.

Next, after removing the remaining resist on the M film 14 on the wiring board, it is placed in a pyrophosphate steel plating solution, and the process shown in FIG.
As shown in dl, the copper film 18 is approximately 20 μm thick by electroplating.
It is formed over the entire surface of the M film 14 to a thickness of . At this time, the through-hole conductor 4 in the contact hole 15 and the copper film 18 are directly bonded at the bonding surface 9.

After washing and drying the wiring board 6 on which the copper film 18 has been formed in this way, a positive resist 2o is applied on the copper film 18 while the copper film 18 is not oxidized, and the solder joints 8 of the micro leads 7 are coated with a positive resist 2o. A portion of the resist 20 corresponding to the position is removed in a circular shape with a diameter of about 110 μmφ.

Next, as shown in FIG. 4 (el), a Ni layer 25 is first formed with a thickness of about 0.5 μm on the exposed portion of the copper film 18 after the resist is removed, and then an Au layer 25 is formed on the exposed portion of the copper film 18.
(gold) layer 22 is formed with a thickness of 1 μm.

Next, in order to form the micro leads 7 shown in FIG. 14, the remaining resist film on the Cu film 18 on the wiring board 42 is removed, and a negative resist is newly applied and dried. After exposing a large number of shaped micro lead pattern groups, the resist in other parts is removed. Here, the joint part 9 with one through-hole conductor 4 is made to coincide with the circle center of the through-hole conductor 4, and the other solder joint part 8 is made to coincide with the circle center of the gold layer 22.

Next, the copper film 1 other than that protected by the negative resist
The exposed part of No. 8 was treated with ferric chloride aqueous solution (Fec4・cL-35
Microleads 7 are etched using an etching solution of t/l) as shown in FIG. 4(f).

Next, the M film 14 was dissolved and removed using an aqueous sodium hydroxide solution to form a void 24 between the micro lead 7 and the wiring board 42, as shown in FIG. 3(y), and then washed with water and dried. .

Next, the wiring board 42 is heated in a mixed flow of air and oxygen at about 200° C. for 10 minutes to oxidize all of the surfaces 26 of the micro leads 7 other than the gold layer 22, as shown in FIG. 3 (hl). At this time, the gloss on the surface of the copper film faded and it was found that the surface of the copper film was oxidized, and from this, a wiring board with microleads was produced.

Further, the specifications of the wiring board with micro leads produced in this manner are as follows.

fll Micro lead dimensions Lead band width ・・・・・・・・・・・・ 50μm Lead size ・・・・・・・・・・・・Approx. 20μm Inter-lead pitch・・・・・・・・・ 300μm (2) Number of micro leads per chip connection...1225 Example 3. L.S.
I-chip connection: Example 1 by one or more processes
The lead ends (L) of the wiring board with micro leads prepared in
The SI chip connecting portion 8) and the solder ball IO already provided at the connecting terminal portion of the L8I chip were aligned using a half mirror, and the LSI chip was connected by a normal face-down bonding method. The connection temperature at this time was an instantaneous peak temperature of 300° C. from the melting point of the solder provided on the LSI chip.

As described above, the LSI chip 11 is connected to the microphone (I) on the wiring board.
The one shown connected to the IJ-door! @Figure 5. The figure shows a partial cross-sectional view of the same, where 6 is a wiring board, 4 is a through-hole conductor, 7 is a micro lead, and 24 is a through-hole conductor.
10 indicates a void, 10 indicates solder, and 11 indicates an L8I chip.

Example 4. Connection of LSI chips: The two LSI chips can be connected before removing the lift-off layer.

However, in that case, it is preferable to use an organic substance that dissolves in an organic solvent or a substance that dissolves in water or hot water as the lift-off material. Shijist was used.

Example 5. Thermal cycle test The wiring board with the Li9I chip connected in Examples 3 and 4 above was placed in the thermal attack test chamber (chamber), and -5
A thermal test was conducted at a temperature of 0°C to 150°C at a rate of 1 cycle for 1 hour. The results are shown in Table 1. Table 1 shows the differences between the conventional CCB soldering method and the method using a micro-lead wiring board, which is one of the main parts of the present invention.

This is a summary of the effects.

The results showed that by using a wiring board with micro leads, which is one of the main parts of the present invention, the soldered joints can sufficiently withstand the cold/heat cycle environment even if the α difference is greatly different.

As a result, the first objective of the present invention was achieved.

Table 1 * Coefficient of thermal expansion (X 10-7℃) #-50~+15Ll:, 104 cycles Kirikyu α difference 4
Experimental results at 0 x 10''/°C Example 6. Spring test Regarding the L8I chips connected in Examples 3 and 4 above,
We conducted a test on the springiness of the microlead. As a result, in the vertical (Z) direction per chip, 28
．． 8Kt/W, and the sample of Example 4 was 30.1jk.

As a result of the above, it was found that the second object of the present invention can be achieved, that is, it has springiness in the vertical direction. Therefore, the second object of the present invention, which is the simplification of electronic device assembly using the LSI chip connection board having spring properties in the vertical direction, will be described below.

Example 7. Assembly of electronic device: Part 1 Using the wiring board with micro leads to which the L8I chip was connected prepared in Example 3, a central control unit (CPU) of a large-sized computer was assembled. In this logic operation section, there are many modules (here, L8 in the third embodiment).
One board to which 25 to 100 I chips are connected is called one module).

FIG. 6 is a sectional view of a portion of one of the many modules described above mounted on the board 30. This sixth
In the figure, the back surface of the L8I chip 11 connected to the wiring board 6 with micro-leads could be sufficiently pressed against the wall surface of the cooling body 12 due to the vertical springiness of the micro-leads. For this reason, the heat dissipating stud of the spring mechanism (see FIGS. 19 and 24) as in the conventional cooling body 12 can be omitted. Further, for this purpose, the cooling body 12 can be provided with fins 32 having high heat exchange efficiency for water cooling inside the cooling body 12. This water cooling and fins improved heat exchange efficiency several times more than conventional cooling methods. In this figure, 11 is an LSI chip, 7 is a micro lead, and 6 is a wiring board.

35 is pin 5' electrical connector, 31 is the cooling water channel, 32 is the fin, 36 is the gold soldering material, north is the cooler cover, 34 is the cooling water pipe, 30 is the board, 37 is the module power wire show. Here, instead of using the gold soldering material 36, it is also possible to just contact the L8I chip.

Through the above, the second object of the present invention was achieved. That is, the structure of the electronic device to be assembled, especially the cooling body, has been simplified, and the method of cooling has been improved.

Example 8. Assembly of electronic device: Part 2 Using the wiring board with micro leads prepared in Example 2, this LSI chip was packaged as shown in FIG. In this Figure 7, 6 is a wiring board with a coefficient of thermal expansion α, 7 is a micro lead, 42 is a wiring board with a micro lead, 43
is a solder bump, IO is CCB solder, and 41 is a package cab.

Next, the compactly packaged module was placed in a large case with a water cooler, as shown in Figure 8. In this figure, 11 is the L8I chip, 41 is the LSI chip package cab, and 12 is the cooling body.

32 is a fin, 33 is a cooler cover, 31 is a water channel, 34
is the cooling water pipe.

As described above, once the packaged LSI chip module is mounted, the back surface of the module itself (the top surface of 41) is connected to the cooling body 12 by the microphone QIJ-de provided at the bottom of the packaged LSI chip module.
I was able to press it firmly against the wall. As a result, there is no need to provide a resilient heat dissipation stud on the cooling body, and the creation of the structure 9 of the cooling body can be simplified. In addition, a fin 32 is provided to eliminate static electricity obtained by simplifying the process, and by using this and water cooling, the L8I
We were able to improve the chip cooling effect several times more than before.

Through the above steps, the second objective of the present invention was achieved.

〔Effect of the invention〕

As described above, the present invention enables electronic components such as LSI chips to be electrically connected to each other by having spring properties or free deformability in all horizontal and vertical directions, and to use a module connected thereby. Accordingly, the assembly structure of the electronic device can be simplified. Furthermore, this simplification made it possible to easily adopt a water cooling system that improves the cooling effect. Therefore, the present invention makes it possible to connect and use electronic components with substrates having different linear thermal expansion coefficients, and to extend the service life (improvement of durability), simplify the assembly of electronic devices, improve the cooling effect, It is useful in the electronic device manufacturing industry. A useful quantitative comparison is shown in Table 2.

Table 2 * Conventional method 1: CCB connection method and spring-type heat dissipation stud assembly method Hayashi Conventional method 2: Ehrfelt 2 Honda and Mr. Ohno's connection method Table 3 Three major classifications of conventional LSI chip connection methods and their characteristics

[Brief explanation of the drawing]

Fig. 1 is a partial cross-sectional view of the starting wiring board, Fig. 2 is a cross-sectional view of the principle of mounting the micro-lead shape, bonding, chip connection structure, cooling body, etc. of the present invention, and Figs. 3 and 4 are micro-leads. Manufacturing process diagram of leaded wiring board, Figure 5 is LSI
6.7 and 8 are partial cross-sectional views of the assembled structure of an electronic device according to the present invention, and Figures 9 and 10 are partial cross-sectional views of the principle of the chip connection structure. Figure 11 is a diagram of stress calculation results for micro leads, Figures 12 to 15 are example diagrams of microphone □ IJ-do shape, and Figures 16 to 18 are diagrams of the chip connection method of the conventional proposed method. , Fig. 19 is an explanatory diagram of the conventional method, Fig. 20 is a diagram of the CCB connection life limit test results, and Fig. 21 is a TAB
Fig. 22 is a diagram showing the wire bonding method, No.
The figure shows the number of L8I chip terminals, FIG. 24 shows a conventional electronic device implementation diagram, and FIG. 25 shows a CCB method connection principle diagram. Explanation of symbols 1... Board surface 2... Insulating layer 3... Horizontal wiring 4... Through-hole conductor 5... Pin 6... Wiring board 7... Micro lead 8... Solder Connection part 9...Micro lead joint part 10...Solder 11...L8I chip 12...Cooling body 13...Joint metal 14
...M lift-off layer 15...Contact holes 16-19...Micro lead material 20...Photoresist 21...Resist hole 22...λU bump 23...Space 2
4...Void portion 26...Cu surface oxide film 30...Board 31...Waterway 32...
・Fin 33...Water cooler cover 34...
・Cooling water vibrator 35...Electrical connector 36...
・Adhesive gold soldering material 37...Module 11L source 4
1...Package cab 42...Alumina substrate 4
3...Solder bump Figure 1 1 Board surface 2 Interlayer insulation layer 3 Circuit pattern 4 Through-hole conductor 5 Hφ Kawachoko 1? Figure 2 (a) (b) 4 through hole conductor 6 i edge base 7 micro lead wire 8 chip m pattern BP 9 through hole conductor 1 order l 10 is A/da It LSI
Chip +2 eRpf book 22
Au7 micro lead 13 Nii 148/
)J 16Q-M Mouth C+J! 18 CuJ! L
AW 19 Cr Pa I20 Resist m22'kJ
fA Fig. 6 Fig. 7 Fig. 9 Fig. 10 Fig. 11 Load (total) [Go m kidney ↓ both 2-'Ez・12000 words/-1 to 4 anti-foot] No. 120 (A) (B) No. 130 (8) Fig. 15 (A) (B) Fig. 160 80 Guidance 81 Penetration 83 Chitu 2゜No. 18 (C) Fig. 19 Cooling layer Fig. 20 Thermal expansion 1 unit history left 1 Koyoro CCB Wholesaler Wandu Calendar Product Limit Value Setup Changzhang Coefficient Envy △仄(XIσ7翰report) (1) t['
% When using cold and heat recycling (2) Heat content of common name -
ri'ikurui history F@l) Sou No. 21 Figure 25 Example of film carrier arrangement No. 22 Wagon bonde Expression of CB method) 1. IC chip (3) person CD') (b) stiffness (b) stiffness (b) west link

Claims (1)

[Claims] 1. An electronic component provided with a large number of connection terminals on the same plane is electrically connected to a wiring board via a plurality of electrodes provided on the surface thereof corresponding to the connection terminals. A connection structure for electronic components that can be displaced both horizontally and vertically. 2. In the electronic component connection structure according to claim 1, one end of the micro lead extending into the space by bending or turning is electrically bonded and fixed to the electrode of the wiring board in advance, and then the other end of the micro lead is electrically bonded and fixed to the electrode of the wiring board. A connection structure for an electronic component, characterized in that the electronic component is connected to a flexible structure via the micro lead by electrically connecting and fixing a connecting terminal of the electronic component at an end. 3. In the electronic component connection structure according to claim 1, the shape of the micro-lead is such that the vertical length of the lead cross section is shorter than the horizontal length, and the horizontal length is 30 to 7.
A connection structure for an electronic component, characterized in that the lead is shaped like a band with a width of 0 μm and is bent or turned at least in the horizontal direction. 4. Step of preparing a wiring board consisting of a single layer or multilayer wiring structure with electrode groups formed on the surface to which electronic components are connected; Step of forming a lift-off material coating on the entire surface of the wiring board except for the electrodes; Step of providing a conductive film for forming micro-leads on the entire surface including the top of the electrode; Next, a resist film is formed on the conductive film for forming micro-leads, and a bent or swirled spiral lead pattern mask is predetermined on the electrode. a step of forming a resist pattern of the microleads by arranging the microleads so that one end of the microleads is located, and performing exposure and phenomenon processing; a step of etching the conductive layer for forming the microleads using the resist pattern as a mask; ; a method for manufacturing a connection structure for electronic components, the method further comprising the step of dissolving and removing the lift-off film and the resist pattern. 5. A module for an electronic device, characterized in that the connection structure for electronic components according to any one of claims 1 to 3 is mounted on a wiring board. 6. An electronic device, characterized in that the electronic component connection structure according to any one of claims 1 to 3 is mounted on a wiring board and the electronic component is pressed against a cooling body.