JP2927275B2 - Electronic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having a connection structure between members having a large number of fine connection terminals.

[0002]

2. Description of the Related Art Conventionally, LSI chips are electrically connected by (1) wire bonding, (2) tape carrier bonding (or TAB: Tape Automated B).
onding) and (3) flip-chip bonding method (Literature 1: Two bottles and two others, Semiconductor Handbook, P128, Science Forum, 1986, 9,2)
Five).

[0003] Among the three connection methods, the methods (1) and (2) can be applied only to a chip having an input / output terminal of an LSI chip at a peripheral portion of the chip (see Table 3). : From Reference 1). Details of the reason will be described later.

On the other hand, the flip chip bonding method (3) has a structure in which connection terminals are provided not only at the periphery of the LSI chip but also over the entire surface of the chip including the center (hereinafter, referred to as a lattice-like terminal arrangement). ) Can also be applied to the chip.

In this method, a solder pump having a height of about 100 to 125 μm is provided on the surface of a terminal of an LSI chip to be connected, the chip is placed on a wiring board, and the solder is reheated and welded to connect. This method is a C-4 method (Solid
Logic Technology) or CCB method (Controlled Co
llapse Bonding).

FIG. 25 (Literature 2: Honda and three others, high-density mounting handbook, pp. 238, 1986) shows a principle schematic diagram of the connection mechanism of the CCB method. In this CCB method, L
The connecting medium (solder in this case) does not extend (extrude) beyond the lateral (horizontal) size of the SI chip. In addition, one connection medium (solder) does not spread so much in the horizontal direction. For this reason, the LS having a lattice-like terminal arrangement is used.
This is advantageous for connecting and mounting a large number of I chips adjacently and continuously.

As an application example of the connection and mounting of chips by the CCB method, an ultra-high-speed computer requiring a large number of high-density mountings, for example, a TCM (Thermal Cond.
uction Module) (FIG. 24, Document 2, P240).

[0008] As in the above example, in an electronic computer or a high-end electronic device, mounting of an LSI chip having a large number of connection terminals is required. In particular, in recent years, as can be seen from FIG. 23 (from Document 1), the number of terminals of the logic LSI has increased remarkably, and they are becoming a chip structure having a lattice-like terminal arrangement from the viewpoint of high density arrangement and power supply characteristics.

As described above, with respect to logic LSI chips arranged in a grid-like and high-density manner, the wire bonding method or the tape carrier bonding method (hereinafter referred to as TAB method) has the following reasons. ,
Cannot be applied.

The wire bonding method is shown in FIG.
As shown in P307), this is a method in which a thin Au or Al wire is drawn out from the terminal of the LSI chip to the periphery of the outside and connected. For this reason, (1) a space is required on the outer periphery of the chip for pulling out and connecting leads (wires), and basically an extra space for connecting must be prepared. (2) Leads are connected by a device called a wire bonder, but the lead wires (wires) are bare wires without any insulation coating. Contact. For this reason, the wire bonding method is not suitable for connection of a chip having a structure having a high-density and lattice-like terminal arrangement like the above-described logic LSI chip.

In the TAB method, FIG.
In this method, wiring leads are provided on a film (carrier) and a chip is connected to the film through the leads.

In the TAB method, an extra lead portion is required as a bonding margin for fixing the lead wire to the film, and there is a problem in shortening the lead length. That is, in the conventional film carrier, the middle part between the outer lead and the inner lead is made longer, and the part is fixed and carried on the film base. The inner leads are wired linearly inward. Therefore, an LSI that can be connected to this
Has been limited to LSI chips for memories and the like having a relatively small number of terminals in which terminals are arranged only in the peripheral portion. However, the logic LSI chip has an extremely large number of terminals (approximately
There are 500 or more pieces on 10mm ^□ ). Also, as described above, the terminals are arranged not only in the peripheral portion of the LSI chip but also in a lattice pattern uniformly up to the central portion.

For this reason, a logic LSI chip having a lattice-like terminal arrangement cannot be connected in a shape in which the inner leads are linearly wired inward in a plane as in the TAB method.

To summarize the disadvantages of the above two methods,
(1) An extra space larger than the area occupied by the LSI chip is required. (2) It cannot be applied to a chip having a structure having terminals in a grid pattern up to the center of the chip, such as a logic LSI chip.

For the above reasons, a method for connecting and mounting LSI chips having a terminal structure arranged in a grid-like and high-density manner such as a logic LSI chip in a high-density and compact manner is based on the CCB method described above. Only the representative flip chip bonding method is used.

However, in the flip chip bonding method such as the CCB method, a direct connection is made with a ball-shaped solder, and is basically a connection method having a rigid (hard) structure. Therefore, in recent years, inconvenience has occurred in this method. The situation will be described below.

In recent years, in the field of high-performance electronic equipment such as electronic computers, there has been a demand for the development of a flexible chip connection technology for mounting LSI chips.

In this field, a connection method of a rigid structure such as the CCB method described above cannot satisfy the demand any longer.

The reason why the flexible LSI chip connection method is required is that it is related to the operation speed which is one of the most important performances in an electronic computer, for example. That is, the operation speed is determined by the performance of the LSI and the performance of the wiring board for mounting and mounting the LSI when viewed from the hardware (device) side of the computer.

Looking at recent trends in this wiring board, multilayer wiring boards made of ceramics (alumina, mullite, etc.) using W (tungsten) or Mo (molybdenum) as a wiring material have been developed and put into practical use.

This is effective in connecting and mounting the LSI chips at a high density and shortening the total wiring length of the increasing wiring. However, there are the following unsatisfactory points in the transmission performance of electric signals.

(1) Since the ceramic substrate generally has a large electric permittivity (alumina: 9 to 10), a parasitic charge is generated at an interface where the ceramic substrate and the wiring are in contact with each other, which causes a delay in the transmission speed of the electric pulse signal. Become.

(2) W, Mo, etc., which are wiring conductor materials, have a higher electric resistance than other metal conductors, for example, Cu (copper). Therefore, the waveform of the electric pulse signal is deteriorated. As a result, it is difficult to reduce the time between transmitted pulses, which is a factor that hinders the transmission capacity and speed of the pulse signal.

Therefore, in order to eliminate the above-mentioned disadvantages, recently, Cu or the like is used as a wiring material, and an organic substance having a small electric permittivity, for example, a polyimide resin ( ⁴⁾ is used as a substrate material.
There is a tendency to develop or use a wiring board using 3) or the like.

However, in the above-mentioned high-performance wiring board, the coefficient of linear thermal expansion is larger than that of ceramics such as alumina, and the difference in coefficient of thermal expansion (hereinafter referred to as α difference) with Si, which is the main component of the LSI chip, is 100 to 100%. It is as large as 130 × 10 ^-7 / ° C.

Therefore, when the LSI chip is directly soldered to the wiring board as in the conventional LSI chip connection method, the following inconvenience occurs. That is, organic matter and Cu
When an LSI chip is fixed to a wiring board using
Because of the large difference, a thermal stress is generated in the solder joint, and the solder joint is broken due to the distortion due to the thermal stress, resulting in disconnection of the joint.

Therefore, when an LSI chip is connected to a wiring board having a large coefficient of thermal expansion as described above, a method capable of absorbing or mitigating a thermal stress distortion caused by an α difference between the two.
That is, an LSI chip connection method having a flexible structure is required.

Even when a ceramic wiring board as in the prior art is used, for example, the thermal expansion coefficient of an alumina ceramic wiring board (60 to 65 × 10 ⁻⁷ / ° C.) is the same as that of an LSI chip (30 × 10 ^−7). / ° C). In particular, with the recent increase in size of LSI chips (10 mm ^□ → 16 mm ^□ ), thermal stress distortion due to α difference tends to increase, and it is already in a situation where connection using only solder cannot withstand thermal stress distortion. . For this reason, the conventional ceramic wiring board is
When connecting chips, an LSI chip connecting method is required which has a structure capable of absorbing or relaxing strain caused by thermal stress.

The above situation is summarized in FIG. 20, the vertical axis represents the size (size) of the LSI chip, and the horizontal axis represents the wiring board and the LSI chip (main component Si).
And the hatched line in the figure indicates the limit value of the life in the CCB connection method. This figure is created based on the experimental results of the inventors using the CCB connection method.

From the above, it is apparent that the durability has reached the limit in the connection of the rigid structure by the simple CCB method.

The following is a summary of the deficiencies of the conventional and well-known LSI chip connection technology.

(1) The wire bonding method and the TAB method cannot be connected and mounted compactly in the horizontal direction.

(2) It is not possible to connect and mount a flexible structure by the CCB method.

In order to solve the above-mentioned problem (2) with respect to the disadvantages of the existing LSI chip connection technology, for example, the one described in Japanese Patent Application Laid-Open No. Sho 61-110441 is disclosed by Ehrfeld. Has been proposed by

[0035]

However, the above proposed method has the following problems.

(1) The connection between the LSI chip and the wiring board has no deformation (freedom) or elastic force (springiness) in the vertical (2) direction.

This means that after connecting the LSI chip to the wiring board, a problem arises in the contact portion between the back surface (non-electrical connection surface) of the LSI chip and the cooling body. That is, the LSI chips (plurality) connected to the wiring board are usually individually connected with some unevenness or oblique inclination (not completely horizontal). Therefore, a gap (or poor contact) may occur at the contact interface between the chip and the cooling body.
In order to compensate for this contact failure, the back surface of the chip is normally pressed from the side of the cooling body with a bar (heat radiating stud) provided with a spring mechanism (see FIGS. 19 and 24, and from Documents 1 and 2).

However, in this method, the cooling effect is reduced and the structure of the cooling body is complicated.

On the other hand, the connection method in which the LSI chip has an elastic force (spring property) in the vertical (2) direction has good contact properties and can simplify the conventional cooling body.

However, the conventional connection method of only soldering by the CCB method or the above-mentioned connection method of Ehlfeld has little or sufficient elasticity.

(2) In the Eilelt connection method, two connections are required for one terminal of the chip.

That is, Japanese Patent Application Laid-Open No. 61-110441
In connection with the above, when a chip is connected to a substrate, it is necessary to connect two terminals, one at the top and the other at the bottom, per terminal of the chip. This increases the number of connection points, which is not preferable in terms of chip connection work, reliability of electrical connection, and electrical resistance. This point is also one of the technical problems to be solved by the present invention. That is, in high-density mounting in which a large number of chips are mounted on one substrate, it is desirable that one terminal is connected to the substrate electrode at one place. FIG. 18 shows a configuration of a coupling element in a case where connection is made at two locations of the above-described Eilelt (FIG. 18 (a) is a perspective view, and FIG. 18 (b) is a plan view). [Fig. 19 (c) is a sectional view]
It is shown. In other words, the connecting element has two parallel pins 60a and 60b connected to each other by the thin leaf spring 60. In FIG. 18C,
One pin 60b of the coupling element is electrically connected to the conductor portion 65 of the ceramic substrate 62, and the other pin 60a is electrically connected to the electrode 64 of the chip 61 via the solder 63. With such a configuration, the one terminal 64 of the chip is connected to the conductor path 65 of the substrate via two pins 60a and 60b of the coupling element, and the number of connection points is two.

For the above reasons, it is desirable to complete the connection of the LSI chip by one (simultaneous simultaneous terminal) soldering as in the conventional CCB soldering, even though it is a flexible structure connection method.

In the Eilelt connection method, a high energy is required to produce a leaf spring (see Japanese Patent Application Laid-Open No. 61-110).
No. 441 uses synchrotron radiation), and the entire process is complicated and cannot be easily performed.

On the other hand, in an attempt to connect the LSI chip to a more or less flexible structure, Honda has proposed a method described in Japanese Patent Application Laid-Open No. 57-112255 besides the above-mentioned Eelfeld method.

In this method, as shown in FIG. 17, the wiring films 71A and 71B are formed on the LSI chip 70 (electric circuit element) itself.
And a metal pump (solder) 72A, 7
2B, and a method of connecting this LSI chip to the wiring board 74 is described. In this proposal, a film 73 (Pi) referred to as a spacer before or after connection of the chip is provided.
Q: Organic film) is removed, and the wiring film and metal pump absorb heat fluctuation distortion (from the text).

However, in this proposal, the following (1) to
Not only is (4) unclear, but there is a drawback in that there is no extensibility in a specific horizontal direction as described later.

(1) Shapes and dimensions of wiring films 71A and 71B (2) Formation of wiring films and spacers, etching conditions (etching solution name, time, etc.) (3) Specifics including the above (1) and (2) (4) Quantitative evaluation results of the invention Therefore, when mechanical expansion and contraction (from the text) due to thermal strain to the extent of (1) occurs, wiring films 71A and 71B are used to prevent solder destruction. Cannot be determined to what size (width, thickness, length, overall shape, etc.) should be designed.

(2) It is difficult to make a plan for operation procedures such as preparation of chemicals and the like, film formation, and etching for implementing this proposal.

Further, according to this method, the wiring film 71 shown in FIG.
If the shapes of A and 71B are rectangular, there is a defect in the connection structure that there is almost no extensibility in the horizontal inward direction in FIG. That is, the solder pumps 72A, 7
2B is, for example, a CCB soldering temperature (about 270 to 330 ° C.).
In the CCB connection / cooling step of lowering the temperature to about room temperature, the wiring films 71A and 71B are severely pulled (tensioned) inward in the drawing, and there is a structural defect that leads to disconnection or disconnection.

Another method different from the above is proposed by Mr. Amano (Japanese Patent Laid-Open No. 62-136830). FIG. 16 shows the method.

However, even in this method, the solder connection portion must be subjected to a strong tensile stress in a specific horizontal direction. That is, the conductor layer 80 in FIG. 16 greatly extends in a horizontal outward direction when the substrate 81 is heated by chip heat generation or the like. However, the LSI chip 83 has a small growth.
This results in the solder connection 82 being pulled out horizontally. Therefore, in the same manner as in the Honda method described above, in a specific horizontal direction (although the direction is opposite to the Honda method)
There are structural drawbacks that cause tension.

As described above, the method of Honda and Amano has a drawback in the connection structure in which the relaxation of the tension in the horizontal direction is not considered. In view of the above, an object of the present invention is to realize a connection structure having a freely deformable or springy property at least in a horizontal direction by using a simplified process.

[0054]

[0055]

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070]

[0071]

[0072]

[0073]

According to the present invention, in order to achieve the above object, a first member having a plurality of connection terminals and a second member are arranged to face each other, and the first member is provided. Alternatively, a connection terminal of the first member and a connection terminal of the second member are electrically connected using a lead having at least a bent shape or a curved shape in a horizontal direction substantially horizontal to the second member. The lead is formed by sequentially laminating a Cr layer, a Cu layer, and a Cr layer, and the thickness of the lead is less than its minimum width.

[0074]

[0075]

[0076]

[0077]

[0078]

A more specific means will be described below.

(Specific Means) FIGS. 12 to 14 show examples of the shape of the micro lead proposed above.

Here, the thickness (height) of the lead should be less than the horizontal direction (horizontal direction) so that the micro lead has an appropriate (not excessive or insufficient) spring property in the vertical direction and the micro lead is etched. This is a dimensional condition for easy formation (described later).

Now, assuming that Cu is used as the micro-lead material, a spiral shape (line width 50 μm) shown in FIG.
m, space width 50μm, spiral diameter 300μmφ, thickness 2
The effect (lifetime of the solder joint) when a micro lead of 0 μm) is used will be estimated by the finite element method and the joint solder life estimation formula.

Setting conditions (1) Coefficient of thermal expansion (α × 10 ⁻⁷ / ° C.) and dimensions of used parts

[0084]

(Equation 1)

(2) Operating Temperature Range and Cooling / Heat Cycle Time 0 ° C. to 80 ° C. (ΔT), 1 cycle / day The results calculated under the above conditions are shown in FIG. (However, it is assumed that the Young's modulus of the solder is 317 Kq / mm ² and the Young's modulus of Cu is 6000 to 12000 Kq / mm ^2. ) The spring constant of the microlead shown in FIG. 11 is 29 to 57 g / mm in the vertical (z) direction. , 100-380g / in horizontal (x, y) direction
mm.

[0086] The displacement amount difference [Delta] y = 8 [mu] m between the chip and the wiring substrate by cold, the maximum equivalent strain of the solder connection portion delta ^g eq
= 0.3-0.5%, and the life of the solder connection will be 26-49
Year was estimated.

As described above, the useful life is sufficient, and it is possible to predict that there is an effect as compared with the case where the life connection is impossible when the micro lead is not used.

The above service life is based on the cooling / heating cycle conditions indicated by the hatched line (1) shown in FIG. 20, and the service life is extended to two to three times under normal cooling / heating use conditions.

As a result of analyzing the electrical characteristics separately from the above, the self-inductance is 0.42 nH (nanohenry) or less and the resistance is about 12 mΩ or less, and there is no particular problem as an electrical connection medium.

As described above, using a highly conductive metal such as Cu as a material, a spiral (spiral-shaped or swirled) micro-floating state (one end may be fixed) in the air. By connecting the LSI chip and the wiring board via the leads, the basic structure of the flexible connection intended by the present invention can be obtained.

Hereinafter, a method of forming the micro lead structure (dimensions, shapes, floating states) will be outlined.

First, the micro lead group (many) is L
SI chip size, eg 10mm for 10mm ^□ chip
^□ .

The material used for the micro-lead may be any metal as long as it is a normal metal having good conductivity. However, the thermal expansion coefficient, the spring property (elastic modulus), the resistance to repeated deformation, and the processing such as etching In consideration of the properties, metals such as Al, Cu, Au, Ni, and Cr are preferable.

Next, a description will be given of a method of forming the micro lead in a state where one end of the micro lead is directly bonded to the wiring board and the other end is floating in the space. This method has been clarified by various experiments performed by the inventors for the present invention.

FIGS. 9 and 10 are diagrams illustrating the principle of the above method.

The method is as follows: a metal layer 18 for forming a micro lead itself through a contact hole portion where the through hole conductor 4 of the wiring board 6 of FIG. And a material layer of the lift-off layer 14 for supporting the micro-lead. The micro-lead is formed by forming or forming the micro-lead by etching, and then the material layer 14 for supporting the micro-lead is removed. (C of FIGS. 9 and 10) That is, the micro lead having a structure floating in the space according to the present invention is provided with a film for forming a void portion, which is more easily dissolved by a chemical or the like than the metal (eg, Cu) used for the micro lead on the wiring board. After the formation, micro leads can be easily formed by plating and etching thereon. Details of this manufacturing method will be described in Examples. In the present specification, the film material for forming a void is referred to as a lift-off material as described above, and the film is referred to as a lift-off film or a lift-off layer. Further, in the method for manufacturing a wiring board with micro leads of the present invention, it is important to select the above-mentioned lift-off material. In the present invention, when Cu is used for a micro lead, the following lift-off materials can be used. The lift-off material of the present invention may be any material that is more soluble than the material used for the microlead.

(1) Al or Al—Si (2) MqO (3) CuO (4) AlN (5) B ₂ O ₂ —SiO ₂ glass (6) Organic substance soluble in organic solvent (1) to (4) are easily dissolved in alkaline chemicals in which Cu metal is hardly soluble, and (4) to (4)
(6) is soluble in warm water and organic solvents. As a result, after micro-leads were formed by etching using Cu, Cu
The lift-off film can be removed by using an alkali solution that is hardly soluble in water or an organic solvent in which hot water is insoluble in Cu.

That is, by this step, the micro lead floats in the space with one end thereof being connected to the conductor of the wiring board. The present invention has been made possible by finding and employing this favorable selective etching process and conditions.

The following metal can be used to join the micro lead to the through-hole conductor of the wiring board.

(1) Ni or Ni alloy (2) Au or Au alloy (3) Cr or Cr alloy The above metals are selected depending on the kind of metal of the micro lead to be joined and the through hole conductor of the wiring board, but they are compatible with each other. Any easy metal may be used. These joining metals are extremely effective when the through-hole conductor is W or Mo.

Further, the metal used for the microlead can be used as long as it is a good conductor. For example, when Cu is used, other effects can be obtained by wrapping it in a sandwich shape with Cr or the like. This will be described in an embodiment. Here, if only one of the effects is described, it functions as a solder dam when an LSI chip is connected to the micro lead by soldering. That is, Au22 provided as a solder pump is very easily wetted with solder, so that soldering can be easily performed.

On the other hand, since Cr does not wet the solder in the 19 Cr portions other than Au, it serves to prevent the solder from adhering to places other than the intended purpose.

It is not always necessary to use the bonding metal when the through-hole conductor is Cu and Cu is used as the microlead material as shown in FIG. In this case, instead of Cr19 for the solder dam, A
Micro lead Cu surface other than u pump
It can fulfill its role by being covered with. Details of this method will be described in Examples.

By using the specific technical means described above, a wiring board with micro leads, which is the first part of the present invention, can be obtained by the following steps.

That is, a step of preparing a wiring board comprising a multilayer wiring structure having an electrode group formed on at least a surface on which electronic components are mounted: forming a lift-off material coating on the entire surface of the wiring board, Forming a contact hole of the above: providing a conductive layer for forming micro leads on the entire surface including on the electrode: forming a resist film on the conductive layer for forming micro leads, and then forming a bent or swirled spiral micro lead Forming a resist pattern of the micro lead by arranging a pattern mask on the electrode such that one end of a predetermined micro lead is positioned, and performing exposure and development treatments: forming the micro lead using the resist pattern as a mask; Step of etching the conductive layer for forming: then the lift-off film and the resist It is possible to create a wiring substrate with micro-lead by a method characterized by having a step of dissolving and removing the pattern.

According to the above method, a wiring board with micro leads can be easily obtained. Next, L using this
The connection method of the SI chip will be described.

The lead end of the wiring board with micro leads prepared by the above-described method (8 in FIG. 12).
A solder hole (see FIG. 25) already provided in the connection terminal portion of the LSI chip is aligned using a half mirror, and the LSI chip is connected by a normal face-down bonding method. The connection temperature at this time is LSI
It is carried out at 200-330 ° C from the solder base provided on the chip.

FIG. 5 shows a state in which the LSI chip is connected to the micro leads of the wiring board as described above.
The figure shows a cross-sectional view of a part thereof, 6 is a wiring board, 4 is a through-hole conductor, 7 is a micro lead, 24
Indicates a void portion, 10 indicates a solder, and 11 indicates an LSI chip.

As described above, the above-mentioned problems (1) to (1)
(5) can be achieved.

Next, the problem (6) mentioned above, that is, the durability of the connection portion of the LSI chip to the heat cycle is considered. This can be proved from the stress analysis described above and the results of the thermal cycling test described in a later example.

The first object of the present invention can be achieved by the above method. The second object is achieved by completing the first object, the flexible structure connection method. That is, the heat radiation stud of the cooling body can be omitted in FIG. In FIG. 2B, the micro leads 7 have a spring property in the vertical direction. Therefore, the back surface of the LSI chip 11 can be completely pressed against and adhered to the wall surface of the cooling body 12. As a result, the heat radiation stud (FIGS. 19 and 24)
) Can be omitted.

[0112]

In the above-mentioned wiring board with micro leads, even if the difference in thermal expansion coefficient between the LSI chip and the wiring board is largely different, the thermal stress generated in the solder joint can be reduced. That is, as shown in FIG. 2 (b), the wiring board 6 with micro leads is used,
The electrodes (not shown) of the SI chip 11 were joined with the solder 10. In this case, the wiring board 6 has a large coefficient of thermal expansion,
The SI chip 11 is small. For this reason, when an LSI chip is mounted and an electrically connected wiring board (hereinafter, abbreviated as a module) operates, the LSI chip generates heat. Extends more than the tip. As a result, a deformation displacement difference occurs between the LSI chip and the substrate.

Conventionally, this displacement difference has destroyed the soldered portion of the LSI chip. However, in the wiring board with micro leads according to the present invention, the micro leads themselves are deformed in the X and Y directions or all the horizontal directions by the amount of the displacement, and the stress can be reduced. Further, since the micro lead can be resilient or deformable in the vertical (Z) direction, the chip can be completely adhered to the cooling body 12 installed on the back (upper side) of the LSI chip. As a result, the effect of cooling the LSI chip can be sufficiently ensured, and the conventionally proposed heat radiation stud having a complicated structure can be omitted.
The cooling body can be simplified.

Further, in the present invention, one end of the micro lead is directly generated from the conductor of the wiring board (see FIG. 2 (b) 9). Therefore, the connection of the LSI chip is completed by joining the solder 10 at one place per terminal of the chip.

[0115]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 15 and Tables 1 and 2.

Example 1 Formation of Micro Lead on Wiring Board: Part 1 FIG. 1 is a cross-sectional view showing the structure of a substrate body 6 which is a starting point for forming a wiring board with micro leads. In this example, an alumina-based ceramic is used as the base layer 2d, and a polyimide-based heat-resistant resin is further provided thereon with the interlayer insulating layers 2a, 2b,
2c shows a substrate body having a multilayer structure having a multilayer structure. External terminal pins 5 for signal input / output, power supply, grounding, etc. are provided on the back surface of a ceramic base layer 2d, and a wiring pattern is provided on the surface thereof. 3c, and a through hole conductor 4 therein is electrically connected to the pin 5, the surface circuit pattern 3c, the circuit patterns 3a, 3b of the upper layers 2a, 2b, 2c, and the through hole conductor 4. That is,
Circuit patterns 3a, 3b are also provided on the surfaces of these interlayer insulating layers 2b, 2c in the same plane direction, and a vertical through-hole conductor 4 for connecting upper and lower circuits to each other is provided inside. An electrode 41 to which a micro lead is connected is exposed on the surface 1 of the uppermost insulating layer 2a, and this electrode 41 is exposed through the internal through-hole conductor 4 to the lower circuit patterns 3a, 3a.
b, 3c, and the through-hole conductor 4, respectively. The circuit pattern 3, the through-hole conductor 4, and the externally exposed electrode 41 were all formed of copper (Cu).

Next, the process of forming the micro leads 7 on the electrodes 41 of the wiring board body 6 will be described with reference to FIGS.
This will be described with reference to the process diagram (l). FIG. 2 is an enlarged cross-sectional view of a portion where the through-hole conductor 4 near the upper surface 1 of the substrate 6 is provided. Here, FIG. 3A shows that immediately after the wiring substrate 6 is formed, before the Cu surface exposed surface electrode 41 at the upper end of the through-hole conductor 4 is oxidized, Nl as a micro lead bonding material is formed on the electrode 41. About membrane 13
It is a process drawing formed to a thickness of 0.3 μm.

The Nl film 13 was formed by a sputtering method using a mask having holes provided in accordance with the positions of the exposed electrodes 41 of the through-hole conductors 4 of the wiring board. The diameter of the through-hole conductor was about 100 μm, and the diameter of the mask was slightly larger, 110 μm.

Next, as shown in FIG. 3B, the Al film 14 was lifted off by about 5 μm as a lift-off material by a sputtering method.
m was formed over the entire surface of the wiring substrate.

Next, an alkali-resistant resist (not shown)
Was applied on the lift-off material 14 and dried, and the resist on the Ni film 13 was removed by a photoetching method.

Subsequently, the Al film of the lift-off material 14 on the Ni film 13 was removed with an NaOH aqueous solution adjusted to 8% (weight percent, the same applies hereinafter), the contact hole 15 was opened, and then water washing and drying were performed. A wiring board in the state shown in FIG. 3C was obtained.

Next, as shown in FIG. 3D, a Cr film 16 and a Cu film 17 were formed on the wiring substrate to a thickness of 2 μm over the entire surface by a spun ring method.

Further, C is formed on the Cu film by electroplating.
After forming the Cu film layer 18 in which the thickness of u was increased to 20 μm, a Cr film 19 was formed to a thickness of 1000 nm by a sputtering method. The state at this time is shown in FIG.

That is, here, the Cr-Cu-Cr is in a sandwich state, and these are bonded to the above-mentioned Ni film 13 provided on the upper surface of the through-hole conductor and formed over the entire surface of the wiring board. . This Cr-C
The thick film of u-Cr is etched by
It is to be a conductor layer for forming the micro lead itself. In addition, a three-layer structure capable of preventing the microlead from curling was adopted.

The Ni, Al, Cr,
The Cu film was formed by an electroplating method using an aqueous solution of copper pyrophosphate under a pressure in an Ar gas flow of about 0.2 P ₃ under the condition of forming a film by the Cu sputtering method. These equipments and conditions are industrial techniques that are now routinely practiced and are easily reproducible.

The Cr- on the wiring board prepared as described above
0.5 hours at 200 ° C to remove residual stress of Cu-Cr film
Annealed.

Next, when micro-leads are formed by etching the Cr—Cu—Cr film, the process proceeds to a step for applying an Au layer to a portion corresponding to the position of a chip connection portion (8 in FIGS. 2 and 12). This Au layer is the LSI chip 11
This is to improve the wettability with the solder for connection and to prevent the surface of the contact portion from being oxidized in the air. In addition, the above Cr-Cu-C
In the r film, Cr is less likely to wet the solder than Au.

Therefore, it is effective to prevent the solder from flowing out to the lead part outside the connection part during the connection work and to prevent the solder from adhering to an extra part (solder dam). Hereinafter, a process for providing the Au film only on the LSI chip connecting portion 8 on the Cr-Cu-Cr film will be described.

First, a positive resist 20 for Au plating is applied on the Cr film 19 of FIG. 3E and dried.

Next, the center of the circle of the conductor joining portion 9 of the micro lead pattern 7 of FIG.
12 is drawn, and the entire micro lead pattern 7 of FIG. 12 is drawn at a position and a size corresponding to the chip connecting portion 8 (circle with a dotted line: about 11).
0 μmφ), and a part 21 of the resist film 20 shown in FIG. In this step, exposure is performed through a mask pattern on which the micro lead pattern end 8 is drawn in FIG. 12, and holes 21 are provided by development.

Next, the Cr film 19 of the same portion was coated with 16.6% Ce (NO ₃ ) ₄
After etching and removal at room temperature for about 2 minutes using a 2NH ₄ NO ₃ aqueous solution, an Au film 22 is formed by a normal electroplating method as shown in FIG. 3 (g), and the resist film 20 is removed. A wiring board in the state shown in (h) was obtained.

Next, in order to form the micro leads 7, FIG.
(H) A water-soluble negative resist was applied to the entire surface of the Au film 22 and the Cr film 19 and dried (not shown).

Next, the chip connecting portion 8 of the micro lead pattern shown in FIG. 12 is aligned with the center of the circle of the Au plating film 22, and the through-hole conductor joining portion 9 and the exposed electrode 41 of the through-hole conductor 4 are aligned. Using the micro-lead pattern, a part of which is shown in FIG. 12, as a mask, a pattern group is drawn by exposure and development, and the other resist is removed by a photo-etching method to draw a micro-lead pattern. The resulting resist pattern was formed.

Next, the Cr—Cu—Cr film exposed by the formation of the resist pattern is firstly made of 16.6% Ce (NO ₃ ) ₄ 2NH ₄
NO ₃ aqueous solution, Cr film in 2 min, followed by 3.8% FeCl ₃
A 50 sec Cu film is removed by etching with a (ferric chloride) aqueous solution, and Cr is further removed with the cerium nitrate aqueous solution.
A microlead group, a part of which is shown in FIG. 12, was formed. That is, the Cr-Cu-Cr film was removed by etching, except for a portion corresponding to the entire microlead, and all other portions were removed by etching. Reference numeral 23 denotes the removed hollow portion.

Next, the used resist pattern (not shown) for etching resistance of the micro leads was
Removal with an aqueous NaOH solution adjusted to 10.5, followed by 15.3
% NaOH solution, 55 ° C, 85min lift-off layer Al
14 is removed by etching, washed with water and dried.
A wiring board with microleads shown in (i) was obtained. In this figure, 4 is a through-hole conductor, 7 is a microlead, and 24 is a gap between the microlead and the wiring board formed by removing the Al film of the lift-off layer 14 between the microlead and the wiring board. .

The specifications of the wiring board with micro leads, which is one of the main parts of the present invention obtained as described above, are as follows.

(1) Dimensions of micro lead Lead band width: 50 μm Lead band thickness: about 20 μm Pitch between leads: 450μm (2) Number of microleads per chip connection ····························································· 1000
g / mm, and the spring constant in the vertical direction is 65 g / mm.

The dimensions of the microlead according to the embodiment of the present invention are not limited to the above examples, and the following dimension ranges are preferable.

The thickness is 10 to 40 μm and the width is 40 to 70 μm. The spring constant is 300 to 600 g / mm in the horizontal direction and 40 in the vertical direction.
~ 90g / mm, connection point density is 600 ~ 1200 pcs / 10mm
^□ .

Embodiment 2 FIG. Formation of Micro Lead on Wiring Board: Part 2 This embodiment is a modified application of the present invention. The through-hole conductor 4 is provided vertically on the alumina substrate 42 shown in FIG.
This was prepared by firing a perforated alumina substrate using a Cu conductor paste.

As shown in FIG. 4 (a), the method of forming the micro leads is as follows, as shown in FIG. 4 (b), over the entire upper surface 1 of the wiring substrate 42 formed as described above. Al film 14 as a lift-off material by sputtering
Is formed with a thickness of about 6 μm.

Then, an alkali-resistant resist (not shown) is applied on the upper surface of the Al film 14 and dried, and the resist in the Al film 14 on the through-hole conductor 4 is removed by a photo-etching method. The Al on the through-hole conductor 4 is adjusted with the adjusted sodium hydroxide (NaOH) solution.
The film 14 is removed, washed with water and dried to form a contact hole 15 in a state shown in FIG. The diameter of the contact hole 15 is about 110 μm.

Next, after removing the remaining resist on the Al film 14 on the wiring board, the resist was put into a copper pyrophosphate plating solution, and as shown in FIG.
Is formed over the entire surface of the Al film 14 with a thickness of about 20 μm. At this time, the through-hole conductor 4 in the contact hole 15 and the copper film 18 are directly bonded at the bonding surface 9.

After the wiring board 6 on which the copper film 18 has been formed is washed with water and dried in this manner, a positive resist 20 is applied on the copper film 18 while the copper film 18 is not oxidized. A portion of the resist 20 corresponding to the position of the joint 8 is removed on a circle having a diameter of about 110 μmφ.

Next, as shown in FIG. 4E, an Ni layer 25 is first formed to a thickness of about 0.5 μm on the portion where the resist has been removed and the copper film 18 has been exposed by ordinary electroplating, as shown in FIG. An Au (gold) layer 22 is formed with a thickness of 1 μm.

Next, in order to form the micro leads 7 shown in FIG. 14, the remaining resist film on the Cu film 18 on the wiring board 42 is removed, and then a negative resist is applied and dried. After exposing a large number of micro lead pattern groups having the shapes shown, the resist in the other portions is removed. Here, the joint 9 with one of the through-hole conductors 4 matches the center of the circle of the through-hole conductor 4, and the other solder joint 8 matches with the center of the circle of the gold layer 22.

Next, the exposed portion of the copper film 18 other than the portion protected by the negative resist is coated with an aqueous ferric chloride solution (Fecl3 · c).
Using an etching solution of 135 g / l), the micro leads 7 are formed by etching as shown in FIG.

Then, the Al film 14 is dissolved and removed using an aqueous solution of sodium hydroxide to form a void 24 between the microlead 7 and the wiring board 42 as shown in FIG. Dried.

Next, the wiring substrate 42 is heated at about 200 ° C. for 10 minutes in a mixed gas flow of air and oxygen to remove all the surfaces 26 other than the gold layer 22 of the microlead 7 as shown in FIG. Oxidize. At this time, the gloss of the copper film surface fades,
It was found that the surface of the copper film was oxidized, and thereby a wiring board with micro leads was prepared. The specifications of the wiring board with microleads thus produced are as follows.

(1) Micro lead dimensions Lead band width: 50 μm Lead band thickness: about 20 μm Lead pitch・ ・ 300μm (2) Number of micro leads per chip connection ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 1225 Connection of LSI chip: Part 1 The lead end (LSI chip connection portion 8) of the wiring substrate with micro leads prepared in Example 1 and the solder ball 10 already provided at the connection terminal portion of the LSI chip by the above-described process. The alignment was performed using a half mirror, and the LSI chips were connected by a normal face-down bonding method. The connection temperature at this time was an instantaneous peak temperature of 300 ° C. from the contact point of the solder provided on the LSI chip.

FIG. 5 shows a state in which the LSI chip 11 is connected to the micro leads 7 of the wiring board as described above. This figure shows a partial cross-sectional view of the wiring board, 6 is a wiring board, 4 is a through-hole conductor, 7 is a micro lead,
Reference numeral 4 denotes a gap, 10 denotes solder, and 11 denotes an LSI chip.

Embodiment 4 FIG. Connection of LSI chip: Part 2 Connection of the LSI chip can be performed before removing the lift-off layer. However, in that case, it is preferable to use an organic substance which dissolves the lift-off material in an organic solvent or a substance which dissolves in water or hot water.

FIG. 15 shows an example of this, and a heat-resistant organic resist soluble in trichlene is used as a lift-off material.

Embodiment 5 FIG. Cooling / Heat Cycle Test The wiring board connected to the LSI chip connected in the above Examples 3 and 4 is put in a chamber (champer) of a thermal shock tester, and is subjected to −50.
A cooling test was performed at a rate of 1 cycle per hour from 150 ° C to 150 ° C. Table 1 shows the results. Table 1 shows the conventional CCB
It shows the differences and effects of a method using only a soldering method and a method using a wiring board with micro leads, which is one of the main parts of the present invention.

[0155]

[Table 1]

As a result, it was found that the use of the wiring board with microleads, which is one of the main parts of the present invention, allows the solder joints to sufficiently withstand the cooling and heating cycle environment even if the α difference is largely different. .

[0157]

Embodiment 6 FIG. Spring property test Regarding the LSI chips connected in Examples 3 and 4,
The microreed was tested for springiness. as a result,
28.8 kg of the sample of Example 3 in the vertical (Z) direction per chip
/ Mm, 30.1 kg for the sample of Example 4.

As a result, it was found that the film had a spring property in the vertical direction.

Embodiment 7 FIG. Assembly of Electronic Device: Part 1 Using the wiring board with micro-leads connected to the LSI chip prepared in Example 3 above, the central control unit (CPU) of a large-sized computer was mounted and assembled. In this logical operation unit, a large number of modules (here, LS
One board connected with 25 to 100 I chips is called one module).

FIG. 6 is a cross-sectional view of a part of one of the modules mounted on the board 30 in large numbers. In FIG. 6, the back surface of the LSI chip 11 connected to the wiring board 6 with micro leads was sufficiently pressed against the wall surface of the cooling body 12 by the vertical spring property of the micro leads. For this reason, the cooling body 12 is provided with a heat radiating stud of a spring mechanism as in the prior art (see FIGS. 19 and 24).
Could be omitted. For this purpose, the cooling body 12 can be provided with water-cooled fins 32 having high heat exchange efficiency. With the water cooling and the fins, the heat exchange efficiency was improved several times or more as compared with the conventional cooling method. In FIG. 6, 11 is L
SI chip, 7 is a micro lead, 6 is a wiring board, 35
Is the electrical connector of pin 5, 31 is the cooling water channel, 32
Is a fin, 36 is a brazing filler metal, 33 is a cooler cover,
34 is a cooling water pipe, 30 is a board, and 37 is a power supply line of the module. Here, instead of using the brazing filler metal 36, only the LSI chip may be contacted.

As described above, the structure of the electronic device to be assembled, in particular, the simplification of the cooling body has been realized, and the method of improving the cooling effect has been improved.

Embodiment 8 FIG. Assembly of Electronic Device: Part 2 An LSI chip was packaged as shown in FIG. 7 using the wiring board with microleads prepared in Example 2.
In FIG. 7, 6 is a wiring board having a large coefficient of thermal expansion α, 7 is a micro lead, 42 is a wiring board with micro leads, 43 is a solder pump, 10 is a CCB solder, and 41 is a package cap.

Next, the above compactly packaged module was housed in a large water-cooled enclosure as shown in FIG. In FIG. 8, 11 is an LSI chip, 41 is L
The SI chip package cap, 12 is a cooling body, 32 is a fin, 33 is a cooler cover, 31 is a water channel, and 34 is a cooling water pipe.

As described above, the once packaged LS
The back surface of the module itself (the upper surface of 41) was sufficiently pressed against the wall surface of the cooling body 12 by the microleads provided at the bottom of the I chip module. As a result, there is no need to provide a spring heat radiation stud on the cooling body, and the structure and creation of the cooling body can be simplified. Further, the fins 32 are provided on the ground obtained for the simplification, and the cooling effect of the fins 32 and the water cooling can improve the cooling effect of the LSI chip several times or more than the conventional one.

[0166]

As described above, according to the embodiments of the present invention, it is possible to extend the life (improve the durability) of connecting and using electronic components with substrates having different linear thermal expansion coefficients, and to improve the electronic device. This is advantageous in the electronics industry because it simplifies the assembly and enhances the cooling effect. The informative numerical comparison is shown in Table 2.

According to the present invention, it is possible to realize a connection structure having a freely deformable or springy property at least in a horizontal direction by using a simplified process.

[0168]

[Table 2]

[0169]

[Table 3]

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a starting wiring board.

FIG. 2 is a cross-sectional view showing the principle of mounting, such as the shape, bonding, chip connection structure, and cooling body of a microlead of the present invention.

FIG. 3 is a manufacturing process diagram of a wiring board with microleads.

FIG. 4 is a manufacturing process diagram of a wiring board with microleads.

FIG. 5 is a principle partial sectional view of an LSI chip connection structure.

FIG. 6 is a partial sectional view of an assembly structure of an electronic device according to the present invention.

FIG. 7 is a partial sectional view of an assembly structure of an electronic device according to the present invention.

FIG. 8 is a partial sectional view of an assembly structure of an electronic device according to the present invention.

FIG. 9 is a principle diagram of a method for producing a wiring board with micro leads, which is one of the main parts of the present invention.

FIG. 10 is a principle view of a method for producing a wiring board with micro leads, which is one of the main parts of the present invention.

FIG. 11 is a diagram showing a result of stress calculation of a micro lead.

FIG. 12 is a diagram showing an example of a micro lead shape.

FIG. 13 is a diagram showing an example of a micro lead shape.

FIG. 14 is a diagram showing an example of a micro lead shape.

FIG. 15 is a diagram showing an example of a micro lead shape.

FIG. 16 is a diagram showing a chip connection method according to a conventionally proposed method.

FIG. 17 is a diagram showing a chip connection method according to a conventional proposed method.

FIG. 18 is a diagram showing a chip connection method according to a conventional proposed method.

FIG. 19 is an explanatory view of a conventional method.

FIG. 20 is a view showing a result of a CCB connection part life limit test.

FIG. 21 illustrates a TAB method.

FIG. 22 is a diagram of a wire bonding method.

FIG. 23 is a diagram showing the number of LSI chip terminals.

FIG. 24 is a conventional electronic device mounting diagram.

FIG. 25 is a diagram showing the connection principle of the CCB method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Board surface, 2 ... Insulation layer, 3 ... Horizontal wiring, 4 ... Through-hole conductor, 5 ... Pin, 6 ... Wiring board, 7 ... Micro lead, 8 ... Solder connection part, 9 ... Micro lead joint part, 10 ... Solder, 11 LSI chip, 12 cooling body, 13 joining metal, 14 lift-off layer of Al, 15 contact hole, 16-19 micro lead material, 20 photoresist, 21 resist hole, 22 Au Pump, 23 space, 24 void, 26 copper oxide film, 30 board, 31 water channel, 32 fin, 33 water cooler cover, 34 cooling water pipe, 35 electrical connector, 36 Bonded gold brazing material, 37: module power supply, 41: package cab, 42: alumina substrate, 43: solder pump.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Naoya Isada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Masaru Sakaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock (72) Minor Murata, 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture, Kanagawa Plant, Hitachi, Ltd. (56) References JP-A-54-74370 (JP, A) JP-A-59- 159553 (JP, A) JP-A-61-110441 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/60 311

Claims (1)

(57) [Claims] (1)A first member having a plurality of connection terminals and a second member
The second member and the first member or the
Small in the horizontal direction, which is almost horizontal to the second member
Use lead with curved or curved shape at least
The connection member of the first member and the second member
An electronic device electrically connected to connection terminals  The leadCr layer, Cu layer and Cr layer are laminated in orderform
And the thickness of the lead is set to be equal to or less than its minimum width.
An electronic device, comprising: