JPH0276251A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a fault of dielectric breakdown by a method wherein an electrode formed on a semiconductor substrate with a thin insulating film interlaid is divided into a plurality in a relatively small size and each electrode thus formed is connected by a relatively slender wiring material. CONSTITUTION:A capacitor is constructed of a semiconductor layer NSD formed on the surface of a semiconductor substrate PSUB and a polysilicon layer PSi formed on said layer with a thin oxide film SiO2 acting as a dielectric interlaid, and the semiconductor substrate PSUB is constructed of a P-type substrate. An electrode formed of the polysilicon layer is divided in a relatively small size, and each divided electrode is connected to others to be one electrode electrically by a slender wiring A of aluminum or the like formed thereon. When there is any weak place of an insulating film in terms of voltage resistance, accordingly, the slender wiring material is cut off by such a current as to cause dielectric breakdown. Thereby the electrode being weak in terms of dielectric strength is cut off automatically and thus the occurrence of a fault of dielectric breakdown as the capacitor is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective when applied to a semiconductor integrated circuit device that includes a built-in capacitor with a relatively large capacitance value. .

[Conventional technology]

In a floppy desk memory control circuit, etc., the read signal includes data and a clock signal.
It has a data separate VFO to separate it. This VFO has approximately 200V to form the control voltage.
It has a built-in capacitor with a relatively large capacitance value such as pF. An example of a floppy disk control integrated circuit (FDC) having such a VFO is, for example, "rHD63265" sold by Hitachi.

[Problem to be solved by the invention]

The capacitor used in the above VFO has a large occupied area as its capacitance value is increased. When such a capacitor is built into a semiconductor integrated circuit,
Insulation breakdown failures occurred frequently.

The inventor of the present application analyzed the above-mentioned dielectric breakdown failure and found that the main cause was as follows.

That is, when using a diffusion layer formed on a semiconductor substrate as one electrode of a capacitor, a thin insulating film such as a gate insulating film as a dielectric is used to form the diffusion layer.
Ion implantation is performed through a polysilicon layer or the like which acts as another electrode. At this time, the polysilicon layer is in an electrically floating state, and charges are charged therein during the ion implantation process, generating a relatively high voltage of about 10-odd volts.

Therefore, if there is a defect or the like in the insulating film, a discharge current flows intensively to the defect, leading to dielectric breakdown.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that has a built-in capacitor that has a simple structure and has a function of effectively preventing dielectric breakdown failures.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an electrode formed through a semiconductor substrate and a thin insulating film is divided into a plurality of relatively small pieces, and each electrode is connected with a relatively thin wiring material.

[For production]

According to the above-mentioned means, if there is a part of the insulating film that has a weak withstand voltage, the thin wiring material is cut by the current that causes dielectric breakdown, so the electrode that has a weak withstand voltage is automatically disconnected. It is possible to prevent the occurrence of dielectric breakdown defects as a capacitor.

〔Example〕

FIG. 1 shows a diagram of an upper electrode pattern of a capacitor built into a semiconductor integrated circuit, and FIG. 2 shows a schematic cross-sectional view of its structure.

As is clear from the cross-sectional view of FIG. 2, the capacitor consists of a semiconductor layer NSD formed on the surface of the semiconductor substrate PSUB and a thin oxide film SiO□ acting as a dielectric like a gate insulating film thereon. Polysilicon i formed by
It is composed of i P S i. The above semiconductor substrate PS
UB is composed of a P-type substrate. Therefore, the diffusion layer NSD is of N type. The capacitor in this example is
It is formed directly using the MOSFET manufacturing process.

Therefore, the thin oxide film as the dielectric is formed in the same step as the step of forming the gate insulating film of the MOSFET. A polysilicon layer PSi is formed on this oxide film using the same process as that for forming the gate electrode of the MOS FET. After this, N-type impurities are introduced by ion implantation, which is an impurity introduction process for the source and drain regions, using MOSFET self-line technology to form the above-mentioned diffusion layer NSD, and annealing treatment is performed in the same manner as for the source and drain. .

In this embodiment, in order to substantially prevent the occurrence of the dielectric breakdown failure described above, the electrode made of the polysilicon layer is divided into relatively small sizes as is clear from FIG. Configure.

The divided electrodes are connected to each other by a thin wiring A1 made of aluminum or the like formed thereon, and electrically form one electrode.

By adopting such a configuration, it is possible to prevent the occurrence of insulation defects as described above. The ion implantation described above charges the polysilicon layer and generates a relatively high voltage. When a voltage breakdown occurs in a certain divided electrode portion due to this voltage, current flows intensively there. This current is supplied by charges of other polysilicon layers through the thin wiring. Therefore, current flows intensively through the thin wire to the electrode with the defective withstand voltage, causing the wire to be cut. In other words, the wiring is formed in such a way that it is cut off by the above-mentioned concentrated current. Therefore, the electrodes having the above-mentioned breakdown voltage defects are automatically separated, and it is possible to substantially prevent insulation defects from occurring.

In this embodiment, the wiring interconnecting the divided electrodes is cut by the current that causes dielectric breakdown as described above, so in addition to the ion implantation process as described above,
Even under normal operating conditions, if an undesired high voltage is supplied, if there is an unused electrode with a low withstand voltage, it will be automatically disconnected in the same way as above, and the function as a capacitor will be completely disabled. It is possible to prevent this from occurring.

FIG. 3 shows a circuit diagram of an embodiment of a voltage-controlled oscillation circuit used in a VFO and a charge pump circuit using the above-mentioned capacitor that forms the control voltage thereof. In the same figure, the P-channel MO3FET is changed to an N-channel MO3FET by adding a small circle to its gate.
Distinguished from FET.

The voltage controlled oscillation circuit VCO is composed of the following circuit elements. One electrode of the pair of capacitors CI and C2 is connected to the ground potential of the circuit. This capacitor CI, C
2, N-channel type switches MO3FETQ21°C23 constituting a discharge circuit are provided in parallel. Between the other electrodes of the capacitors CI and C2 and a current source circuit, which will be described later, is a P-channel switch MO3FETQ20, which constitutes a charging circuit. Q22 is provided respectively. In order to switch between the charging operation and the discharging operation of the capacitors C1 and C2, MO3FETQ20. The gates of C21, C22, and C23 are each shared, and complementary output signals of a flip-flop circuit, which will be described next, are supplied.

The voltage at the other electrode of the capacitors C1 and 02 is supplied to the gates of MO3FETQ25 and C27 as a voltage detection circuit. These MO3FETQ25 and C2
P-channel MO3FETs Q24 and C26, which act as constant current loads by having their gates supplied with a constant voltage VP formed by a constant voltage circuit VC, which will be described later, are provided at the drains of MO3FETs Q24 and C26, although not particularly limited thereto.

Thereby, MO3FETQ25 and C24 and C27 and C26 form an inverter circuit, and perform a voltage comparison operation using the logic threshold voltage as a reference voltage.

Instead of this configuration, MO3FETQ24 and C25
and C26 and C27 (7) gates are connected in common and CM
It may also function as an OS inverter circuit. The output signal of one of the inverter circuits (C25, C24>) is passed through three inverter circuits arranged in series to form a NOR circuit (N) which constitutes a flip-flop circuit.

R) Supplied to one input of gate circuit G3.

The output signal of the other inverter circuit (C27, C26) is transmitted to the AND(A
ND) is supplied to one input of the gate circuit Gl. The other input of this AND gate circuit G1 is supplied with a signal passed through two inverter circuits that receive the output signal of the inverter circuit (C25°C24). The output signal of this AND gate circuit is supplied to one input of the NOR gate circuit G2. The other input and output of the NOR gate circuits G2 and G3 are cross-connected to form a flip-flop circuit.

The output signal of one NOR gate circuit G3 constituting the flip-flop circuit is supplied to the gates of MO3FETQ22 and C23 constituting a charge/discharge switch corresponding to the capacitor C2. The output signal of the other NOR gate circuit G2 is sent to the MOS FETQ20. which constitutes a charge/discharge switch corresponding to the capacitor C1. Supplied to the gate of C21.

For example, when the output signal of NOR gate circuit G3 is high level and the output signal of NOR gate circuit G2 is low level,
The high level of the output signal of the NOR gate circuit G3 turns on the N-channel MO3FET Q23 and discharges the capacitor C2. On the other hand, due to the low level of the output signal of the NOR gate circuit G2, the P-channel MO3FET Q20 is turned on, and the capacitor C1 is charged by a current generated by a current source circuit described later. This capacitor C1 is charged! The pressure is MO3
When the logic threshold voltage of the inverter circuit made up of FETs Q25 and C24 is reached, the output signal passes through the three inverter circuits arranged in series to make the input of the NOR gate circuit G3 a high level (logic "1").

As a result, the output signal of the NOR gate circuit G3 switches from high level to low level (logic "0"). Depending on the stiffness, the N-channel MO3FETQ23 switches from the on state to the off state, and the P-channel MO3FETQ22 switches from the off state to the on state.

As a result, capacitor C2 switches from discharging operation as described above to charging operation.

On the other hand, the output signal of the NOR gate circuit G2 is at a high level due to the low level of the output signal of the NOR gate circuit G3 and the low level of the output signal of the AND gate circuit G1 corresponding to the low level of the output signal of the inverter circuit (C25, C24). Changes to In response, the P-channel MOS FETQ20 changes from the on state to the off state, and the N
Channel MO3FETQ21 switches from off state to on state. As a result, the capacitor C1 switches from the charging operation as described above to the discharging operation (reset).

The charging voltage of the capacitor C2 is MO3FETQ27
When the logic threshold voltage of the inverter circuit consisting of and C26 is reached, the output signal is passed through the three inverter circuits arranged in cascade to the AND gate circuit G1.
set the input to high level. At this time, capacitor C1
By resetting the other inverter circuit (C25, C2
Since the output of 4) is at a high level, the other input of the AND gate circuit G1 is also at a high level, causing the input of the NOR gate circuit G2 to be at a high level.

As a result, the output signal of the NOR gate circuit G2 switches from high level to low level. In response to this, the N-channel MO3FETQ21 is switched from the on state to the off state, and the P channel MOS FETQ20 is switched from the off state to the on state. As a result, capacitor C1 becomes
The discharging operation as described above is switched to the charging operation again.

On the other hand, the output signal of the NOR gate circuit G3 is such that the high level of the output signal of the inverter circuit (C25, C24) is 3.
Since it is supplied as a low level through two inverter circuits, it changes from low level to high level depending on the low level of the output signal of the NOR gate circuit G2.

In response, the P-channel MO3FETQ22 changes from the on state to the off state, and the N-channel MO3FETQ23
switches from off state to on state. As a result, the capacitor C2 switches from the charging operation to the discharging operation (reset) again as described above. Such a capacitor C1
The switching between charging and discharging C2 is repeated to perform an oscillation operation. Although not particularly limited, the oscillation output Fo is output from the inverter circuit that receives the output signal of the NOR gate circuit G3.

The charging currents of the capacitors C1 and C2 are changed by a control voltage VC as described later, so that the oscillation output Fo changes according to the control voltage VC, and the circuit operates as a voltage-controlled oscillation circuit.

P channel switch MO3FET that flows the above charging current
P-channel MOSFETs QIO to C14, which act as current sources, are provided at the drains of Q20 and C22. The drains of these MO3FETs QIO to C14 are supplied with an operating voltage V via MO3FETs Q15 to C19, which act as power switches as follows.
cc is supplied. MO3FETQ15 is constantly turned on by constantly applying a ground potential to its gate. Therefore, the MO connected in series with it
A current constantly flows through the 3FETQIO. On the other hand, other power switches MO3FETQ
16 to C19 are selectively operated by the control signal supplied to their gates, so that the current source MO3 corresponding to the power switch MOS FET is turned on.
Only the FET is allowed to conduct current.

A phase comparison output signal formed by a phase comparison circuit (not shown) is supplied to the gates of the power switches MO3FETQI 6 to Q19. That is, MO5FETQI
A high gain up signal HGU is supplied to the gate of MO3FETQI6 via an inverter circuit, a high gain down signal HGD is supplied to the gate of MO3FETQI7,
The gate of ETQI 8 has a low gain up signal LGU.
is supplied through the inverter circuit, MO3FETQI
A low gain down signal LCD is supplied to the gate of 9.

In a state in which no output signal is supplied from the phase comparison circuit, in other words, in a state in which the phase (frequency) of the re-input signal to the phase comparison circuit matches, all of the above signals become low level. Therefore, power switch MO3FET Q17 and C1
9 is turned on, and the current generated by current source MO3FETQI 2 and C14 is constantly turned on.
Together with the current of IO, it acts as a charging current for capacitors C1 and C2.

The current sources MOSFETs QIO to C14 are configured in a current mirror configuration together with the MO5FETQ8 which receives a combined current of the MOSFETQ5 that performs a voltage/current conversion operation and the MOSFETQ6 that flows a constant current that sets the lower limit frequency. A power switch MO3FETQ9 is provided on the drain side of the MO5FETQ8 to reduce power consumption. That is, in the non-operating state, the signal LP
When set to a high level, the MO3FETQ9 turns off and the MO3FETQ8 is turned off, so the corresponding current source MO3FETQ10
~Q14 is also turned off, and the oscillation operation is stopped. A switch MO3F is connected between the source of constant current MO3FETQ6 for setting the above lower limit frequency and the ground potential point of the circuit.
ETQ7 is provided, inverted by an inverter circuit, and switched by a signal LP.

A control voltage VC is supplied to the gate of MO3FETQ5. The control signal VC is a capacitor C and a constant current MO3F.
It is formed by a charge pump circuit consisting of ETCI to C4. This charge pump circuit functions as a loop filter (low-pass filter) in the PLL circuit, and performs an operation of integrating the output signal of the phase comparison circuit.

The constant voltage ■P generated by the constant voltage generating circuit VC drives the P-channel MO3FETs QI and C3, and the constant voltage VN drives the N-channel MO3FETs Q2 and C4. The drains of the P-channel MO3FETQI and N-channel MOS FETQ2 and the drains of the P-channel MO3FETQ3 and N-channel MO3FETQ4 are commonly connected to the capacitor C.

The MO3FETs QI and C2 are adapted to low gain up and down signals, and are made small in size to allow a relatively small current to flow. Above M
The O3FETs Q3 and C4 are adapted to high gain up and down signals, and are made large in size to allow a large current to flow.

A low gain up signal LDU is supplied to the source of the P-channel MOSFET QI through two inverter circuits. On the other hand, N-channel MO3FET
The source of Q2 is supplied with a low gain down signal LCD. Further, a high gain up signal HGU is supplied to the source of the P-channel MO3FETQ3 through two inverter circuits, and a high gain down signal HGD is supplied to the source of the N-channel MO3FETQ4.

The capacitor C is charged through the P-channel MO5FETs Q1 and C3, and the capacitor C is charged through the P-channel MO5FETs Q1 and C3.
A discharge operation is performed through ETQ2 and C4. The voltage VC held there is converted into voltage/current by MO3FETQ5 to control the oscillation frequency of the VCO.

A phase comparison circuit (not shown) has one input supplied with the reference frequency and the other input supplied with the voltage controlled oscillation circuit V.
A frequency-divided signal formed based on the oscillation output Fo of the CO is supplied. A phase comparison circuit forms the phase comparison output signal which is a phase comparison output according to the phase difference between the two signals.

When the phase of the divided output of the voltage controlled oscillator circuit VCO is significantly delayed (low frequency) with respect to the reference frequency, the phase comparison circuit forms a high gain up signal HGU according to this phase difference. This high gain up signal HGU causes the MO3FET Q3 to flow a constant current according to the constant voltage vp, thereby charging the capacitor C and raising the control signal VC. In parallel with this, only when the high gain up signal HGU is formed, the power switch MO3FETQ1
6 is turned on. Therefore, the above MO3FET
The current from II is added and acts to increase the oscillation frequency. This increases responsiveness.

When the phase of the divided output of the voltage controlled oscillator circuit VCO is slightly delayed (low frequency) with respect to the reference frequency, the phase comparison circuit generates a low gain up signal L according to this phase difference.
Form GU. This low gain up signal LGU causes the MO3FET QI to flow a constant current according to the constant voltage VP, so that the capacitor C is charged and the control signal VC is made slightly higher.

In parallel with this, the power switch MO3FETQ1B is turned on only when the low gain up signal LGU is formed. Therefore, the above MO8FET13
The current from the oscillator is added and acts to increase the oscillation frequency. Since the current MOS FETQl and Q13 corresponding to the low gain up signal LGU are formed relatively small in size, the loop gain is made small to ensure stability.

On the other hand, the phase comparator circuit shows that the phase of the voltage-controlled oscillator circuit VCOO divided output is significantly ahead of the reference frequency (
(high frequency), a high gain down signal HGD is formed according to this phase difference.

This high gain down signal HGD causes MO3FETQ
4 causes a constant current to flow according to the constant voltage VN, so that the capacitor C is discharged and the control signal VC is lowered.

In parallel with this, the power switch MO3FETQ17 is turned off only when the high gain down signal HGD is generated. Therefore, the above MO3FET12
The current is subtracted from the oscillation frequency to lower the oscillation frequency. This increases responsiveness.

When the phase of the voltage-controlled oscillator circuit VCOO divided output is slightly ahead of the reference frequency (the frequency is high), the phase comparison circuit generates a low gain down signal L according to this phase difference.
Form GD. This low gain down signal LGD causes the MO3FET Q2 to flow a constant current according to the constant voltage VN, thereby discharging the capacitor C and lowering the control signal VC a little.

In parallel with this, the power switch MO3FETQ19 is turned off only when the low gain down signal LGD is generated. Therefore, the above MO3FET14
The current from the oscillation frequency is subtracted from the oscillation frequency to lower the oscillation frequency. Since the current MOS FETs Q2 and Q14 corresponding to the low gain down signal LGD are formed relatively small in size, their loop gains are made small to ensure stability.

The effects obtained from the above examples are as follows. In other words, (11) By dividing the electrode formed through the semiconductor substrate and a thin insulating film into multiple parts of relatively small size and connecting each electrode with a relatively thin wiring material, the withstand voltage of the insulating film is weak. Since the thin wiring material is cut by a current that causes dielectric breakdown in the part, the electrode with a weak withstand voltage is automatically disconnected, and it is possible to prevent the occurrence of dielectric breakdown defects as a capacitor.

(2) By using the above-mentioned capacitor in a VFO, the product yield can be increased or high reliability can be obtained without increasing the number of external components.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, the size of one electrode may be any size as long as the variation in capacitance value remains within an allowable value even if one electrode is separated.

Further, the wiring connecting the divided electrodes to each other may be constructed using other wiring materials such as aluminum, or may be constructed using the divided electrode material. That is, in FIG. 1, the thin connection wiring may also be integrally constructed using a polysilicon layer.

The capacitor according to the present invention can be widely used in various semiconductor integrated circuit devices that require a built-in capacitor with a relatively large capacitance value, in addition to those used in charge pump circuits used in the VFO.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, by dividing the electrode formed between the semiconductor substrate and a thin insulating film into multiple parts of relatively small size and connecting each electrode with a relatively thin wiring material, the parts with weak breakdown voltage of the insulating film can be removed. Since the thin wiring material is cut by a current that may cause dielectric breakdown, the electrodes having a weak withstand voltage are automatically separated and can be used as a capacitor to prevent dielectric breakdown from occurring.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of a capacitor according to the present invention, FIG. 2 is a structural sectional view showing an embodiment of the capacitor according to the present invention, and FIG. 3 is a VFO using the above capacitor. FIG. PSUB...substrate, NSD--diffusion layer, PSi...polysilicon layer, AI...aluminum wiring, SiO2
...Oxide film, VG... Constant voltage generation circuit. Figure 1 Figure 2 & 7PjB Figure

Claims (1)

[Claims] 1. Includes a capacitor in which an electrode formed through a semiconductor substrate and a thin insulating film is divided into a plurality of relatively small pieces, and each electrode is connected with a relatively thin wiring material. A semiconductor integrated circuit device characterized by: 2. The electrode formed on the thin insulating film is composed of a polysilicon layer, and a semiconductor layer constituting another electrode is formed on the surface of the semiconductor substrate through this polysilicon layer. A semiconductor integrated circuit device according to claim 1.