JP3337979B2 - Charge pump circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit used in a phase locked loop.

[0002]

2. Description of the Related Art Generally, a phase locked loop (PLL: Phase Lo) is used.
In a cked Loop, a phase comparison circuit is used to handle the phase error between the signal obtained by appropriately dividing the output of a voltage controlled oscillator (VCO) and a reference pulse signal having a reference frequency (phase). A pulse having a pulse width is generated, the pulse is converted into an output charge amount by a charge pump circuit, and a subsequent capacitive charge tank (for example, LPF: Low Pass Filter) is charged and discharged. Frequency (phase) is controlled.

As a basic charge pump circuit used in such a PLL, as shown in FIG. 4, a constant current source X1, switching elements X2, X3, and a constant current source are connected between power supply terminals VDD and VSS. In some cases, the switching elements X2 and X3 are connected in series with each other, and the connection point between the switching elements X2 and X3 is set as an output terminal X5, to which a capacitance element X6 as a charge tank is connected. Switching element X
2, X3 are error signals of a pulse width corresponding to the delay of the phase of the pulse signal based on the output of the VCO with respect to the reference pulse signal output from the phase comparison circuit (not shown), and an error of the pulse width corresponding to the advance. It is turned on by a signal to charge and discharge the capacitive element X6. However,
In such a device, MOS transistors are used as the switching elements X2 and X3, and there exist transistor parasitic capacitances CX and CY. When the switching elements X2 and X3 are turned on, the transistor parasitic capacitances CX and CY are connected to each other. When there is a potential difference with the capacitance element X6,
Charge redistribution is performed between them, causing an error in the output charge amount. Since this error amount changes depending on the output voltage value of the output terminal X5, that is, the charging voltage value of the capacitive element X6, it is difficult to obtain stable input / output characteristics with such a charge pump circuit. This problem cannot be ignored in the final stage of synchronization when the phase error becomes small.

Therefore, as an attempt to avoid the above problem, there is a charge pump circuit as shown in FIG. 5 (for example, “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
32, NO.7, JULY 1997 p.1158 ”). This is because a current mirror circuit Y3 composed of P-channel MOS transistors Y1 and Y2 and N-channel MOS transistors Y4 and Y5
The drains of the P- and N-channel MOS transistors Y1 and Y4 on the output side of the current mirror circuit Y6 are connected to each other, and this connection point is used as an output terminal Y7, to which a capacitive element Y8 is connected. Further, the current values flowing through the P- and N-channel MOS transistors Y2 and Y5 which are self-biased and connected to the constant current sources Y9 and Y10, respectively, are connected to each other to form a differential circuit, and are respectively delayed and advanced. Are controlled by P and N channel MOS transistors Y11 and Y12 driven by an error signal having a pulse width corresponding to
7 controls the amount of charge output to the capacitor Y8. Since this charge pump circuit has no switching element on the output terminal side, the above-described charge redistribution does not occur, and stable input / output characteristics independent of the output voltage value of the output terminal Y7 can be obtained.

[0005]

However, in the charge pump circuit as shown in FIG. 5, a P (N) channel MOS transistor Y1 controlled by an error signal having a pulse width corresponding to a delay (advance) given as an input signal.
When 1 (Y12) turns off, the P (N) channel MOS
A current starts to flow from the transistor Y2 (Y5). The gate and the drain of the P (N) MOS transistor Y2 (Y5) have a P (N) channel MOS receiving an input signal.
The transistor Y11 (Y12) is forcibly set to the same potential as the source until just before the transistor Y11 (Y12) turns off. Therefore, it takes a considerable time for the drain current of the P (N) channel MOS transistor Y2 (Y5), which is a quadratic function of the source-drain voltage, to reach the current value set by the constant current source. During this time, the output charge of the charge pump circuit is significantly lower than the set value, the sensitivity to the input signal is reduced, and a so-called dead zone is formed.

As a countermeasure against such a dead zone, by adding an additional component to the pulse width of the input signal in addition to the net error component, the above-described time is compensated and the self-biased MOS transistor is surely provided. There is an attempt to switch. Specifically, it is as shown in FIG. In the figure, the voltage value of the input signal corresponding to the phase delay,
The voltage values of the input signal corresponding to the advance are VUP and V
DOWN and charge the capacitive element by these input signals.
The discharged current values are shown as IUP and IDDOWN, respectively, and the output current value from the output terminal to the capacitor is represented by IUP.
Shown as OUT. FIG. 3 shows a state in which a phase delay has occurred, and the hatched portion is a net error signal. As can be seen from the figure, the charging current IUP,
The additional component is canceled by the simultaneous flow of the discharge current IDDOWN, and an output current IOUT corresponding to a net error is obtained from the output terminal. The premise of this method is that the charge current value and the discharge current value output from the charge pump circuit match.

However, in reality, the balance between the two varies depending on the voltage value of the output terminal, and the balance is lost due to process variations. This imbalance causes a phase offset error when the PLL is locked as shown in FIG. Further, there is an imbalance between the charging current IUP and the discharging current IDOWN,
Noise having the same cycle as the cycle in which the phase comparison is performed occurs. For this reason, it is necessary to minimize the additional components to such an extent that the adverse effects of noise do not occur, and the effect of suppressing the dead zone is limited.

[0008]

SUMMARY OF THE INVENTION In the present invention, first and second switching elements which are turned on by first and second input signals corresponding to phase delay and lead and have an additional component are provided. The first and second inverted signals are obtained by connecting the gate and drain of the first and second current mirrors to supply current to the self-biased transistors, respectively, and inverting the input signals corresponding to the leading and lagging phases, respectively. With the third and fourth switching elements turned on by
The current flowing through the self-biased transistors of the first and second current mirrors is stopped by controlling the current flowing through the first and second switching elements. For this reason, in the self-biased transistor, the current flow is controlled by the operation of turning on each switching element, so that the delay of the switching operation with respect to the input signal is suppressed. Further, the additional component of the input signal is correctly canceled on the input side by the operation of each switching element, thereby avoiding the additional component from affecting the output side and causing noise.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the phase delay or advance of a specific pulse signal in response to a first or second input signal having a pulse width corresponding to the advance or delay of a specific pulse signal with respect to a reference pulse signal, respectively. In a charge pump circuit for charging a corresponding charge to a capacitance element, a first transistor of a first conductivity type having a gate and a drain connected to each other and the first conductivity type having a source connected to a first power supply terminal having a first potential. A first current mirror circuit formed by connecting the respective gates of the second transistor of the second conductivity type, a third transistor of the second conductivity type having the gate and the drain connected, and a source connected to the third transistor of the second potential. A second current mirror circuit formed by connecting the respective gates of the fourth transistor of the second conductivity type connected to the second power supply terminal to each other; Connect in each other, and an output terminal for charging the charge on the capacitive element provided on the connection point, is connected between the drain and the first constant current source of the first transistor, the first A first switching element that is turned on in response to the first input signal, is connected between a drain of the third transistor and a second constant current source, and is turned on in response to the second input signal; A second switching element, a first switching element connected between the first power supply terminal and a connection point between the first switching element and the first constant current source and inverting the second input signal; A third switching element that is turned on in response to the inverted signal of the second switching element and a connection point between the second switching element and the second constant current source and the second power supply terminal; A second inverted signal obtained by inverting one input signal Answer to the fourth switching element is turned on is provided.

[0010] Preferably, the first and second input signals are inverted and delayed by respective inverters to be second and first inverted signals.

[0011]

Next, a charge pump circuit according to a first embodiment of the present invention will be described.

First, the configuration of the present embodiment will be described with reference to FIG. In the figure, terminals UP and DOWN are terminals for inputting first and second input signals, respectively. Although not shown here, the reference pulse signal and a frequency pulse signal based on the output of the VCO are compared by a phase comparison circuit in the PLL, and an error signal corresponding to a phase delay is output, and a phase lead corresponding to the reference pulse signal is output. Is output. These are obtained by adding a predetermined same pulse width as an additional component to the pulse width of each phase error, and the former is further inverted to become a first input signal and a second input signal, respectively.

The sources of P-channel MOS transistors 1 and 2 (hereinafter simply referred to as "transistors 1 and 2") are connected to a power supply terminal VDD. Transistor 1 is self-biased by connecting its drain and gate. The first current mirror circuit CM1 is formed by connecting the gates of the transistors 1 and 2 to each other.

The sources of N-channel MOS transistors 3 and 4 (hereinafter simply referred to as "transistors 3 and 4") are connected to power supply terminal VSS. Transistor 3 is self-biased by connecting its drain and gate. Further, the gates of the transistors 3 and 4 are connected to form a second current mirror circuit CM2.

The capacitor C0 has one terminal connected to an output terminal OUT provided at a connection point between the drains of the transistors 2 and 4 via a resistor r, and the other terminal connected to a power supply terminal VSS. .

C1 and C2 are first and second constant current sources, respectively. SW1 and SW2 are P-channel MOS transistors as first and second switching elements, respectively.
This is an N-channel MOS transistor, and is hereinafter simply referred to as transistors SW1 and SW2. The transistor SW1 is provided between the transistor 1 and the first constant current source C1,
The gate is turned on and off by receiving a first input signal input from the terminal UP. The transistor SW2 is provided between the transistor 3 and the second constant current source C2, and has a terminal DO
The second input signal input from WN is received by the gate and turned on and off.

SW3 and SW4 are a P-channel MOS transistor and an N-channel MOS transistor as third and fourth switching elements, respectively, and are hereinafter simply referred to as transistors SW3 and SW4. Transistor SW3
Is the drain of the transistor SW1 and the first constant current source C1.
Is provided between the power supply terminal VDD and the power supply terminal VDD, and is turned on and off by receiving the first inverted signal from the inverter i1 that has inverted the second input signal at the gate. Transistor S
W4 is provided between the power supply terminal VSS and a connection point between the drain of the transistor SW2 and the second constant current source C2, and receives at its gate a second inverted signal from the inverter i2 which has inverted the first input signal. On and off.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

The terminals UPN and D are connected to UPN and DOWN in FIG.
The state of the first and second input signals input to OWN is shown. First, when neither the first nor the second input signal is generated, all of the transistors SW1 to SW4 are off.

Next, when a delay occurs in the pulse signal with respect to the reference pulse signal, an error signal corresponding to the phase delay is generated earlier by an amount corresponding to the delay. Thus, at timing t0, the first input signal is generated first, that is, the signal at the terminal UPN falls, and the transistor SW
1 is turned on, and the potential of the drain of the transistor 1 is rapidly reduced. As a result, the current value set by the first constant current source C1 is allowed to flow quickly to the current mirror circuit CM1. For convenience, FIGS. 1 and 2 show the current mirror circuit CM.
The current flowing in 1 is shown as IUP. This current charges the capacitive element C0 as a charging current, and the output terminal OUT
To generate the control voltage of the VCO.

In this embodiment, the output section of the charge pump circuit is constituted by the current mirror circuits CM1 and CM2 and does not include a switch element, so that the error charge due to the charge redistribution phenomenon does not occur.

At the timing t1, when the second input signal is generated after the first input signal, that is, when the signal at the terminal DOWN rises, this signal is inverted by the inverter i1 to become the first inverted signal. The transistor SW3 is turned on. Thereby, the transistor S
The drain potential of W3 is raised to the potential of the power supply terminal VDD. As a result, the drain potential of the transistor SW1 is forcibly raised to its source potential, and the current flowing through the current mirror circuit CM1 stops. In this state, the signals at the terminals UPN and DPWN rise and fall at timing t2, respectively, and the transistor SW
1 is maintained until SW4 is turned off. The time t1 to t2 during which this state is maintained corresponds to the time during which the additional component commonly added to the first and second input signals is sent,
During this time, the charging current from the charge pump circuit stops. This means that the additional component is correctly canceled at the input portion, that is, the transistors SW1 and SW3. The significance of providing the additional component to be canceled here is to surely turn on and off the transistors SW1 to SW4, thereby suppressing the dead zone caused by the small pulse width of the error signal. is there. Such additional components are almost completely canceled in the present embodiment, so that noise generated in the conventional device does not occur, sufficient additional components can be provided, and the dead zone can be effectively suppressed.

Now, even when the pulse signal is advanced with respect to the reference pulse signal, the same effect as when a delay occurs is obtained by the following operation.

If the error signal corresponding to the advance of the phase occurs earlier by an amount corresponding to the advance, the second input signal occurs earlier at the timing t3, that is, the signal at the terminal DOWN rises, Transistor S
W2 is turned on, and the potential of the drain of the transistor 3 is quickly increased. This allows the current value set by the second constant current source C2 to flow quickly to the current mirror circuit CM2. For convenience, FIGS. 1 and 2 show the current mirror circuit CM.
2 is shown as IDDOWN. This current discharges the charge of the capacitive element C0 as a discharge current,
The control voltage of the output terminal OUT is lowered. No charge redistribution phenomenon occurs during this discharging operation.

At timing t4, when the first input signal is generated after the second input signal, that is, when the signal at the terminal UP falls, this signal is output to the inverter i2.
, And becomes the second inverted signal, turning on the transistor SW4. Thereby, the transistor SW4
Is lowered to the potential of the power supply terminal VSS. As a result, the drain potential of the transistor SW2 is forcibly reduced to its source potential, and the current flowing through the current mirror circuit CM2 stops. Also in this state, the signals at the terminals UPN and DPWN rise and fall respectively at the timing t5, and the transistors SW1 to SW1 are turned off.
It is maintained until SW4 is turned off. Here, the additional component is correctly canceled by the transistors SW2 and SW4.

In the above description, the delay of the inverters i2 and i1 for inverting the first and second input signals is not described. However, the additional component is not actually canceled by the delay but only by this. Extra output current flows. This is offset by the current flowing through the current mirror circuits CM1 and CM2 when the net error component is small enough to be regarded as “0”. This can be positively used as a safety measure to prevent the charge pump circuit from falling into a non-reactive state when the error is small. At this time, even if the currents flowing through the current mirror circuits CM1 and CM2 are unbalanced, the duration is short and the influence is small.

When the first and second input signals return to the initial state due to the delay, the transistors SW3 and SW4 continue to be turned on longer than the transistors SW1 and SW2 by the delay, so that the current mirror circuits CM1 and CM2 With the current stopped, the transistors SW1 and SW2 are turned off, that is, the transistors are turned off,
There is also an effect that no switching noise is output on the output side.

The current mirror circuits CM1 and CM2
It is also possible to cancel the delay in order to minimize the influence of the current imbalance of FIG.
As shown in the figure, immediately before the transistors SW1 and SW2,
Transfer gates T1 and T2 having the same delay as the inverters i1 and i2 may be provided.

[0029]

According to the present invention, the first and second switching elements which are turned on by an input signal having an additional component corresponding to the phase lag and lead, respectively, have a first and a second current mirror, respectively. The current is supplied to a self-biased transistor by connecting the gate and the drain of the first and second transistors. The current flowing through the self-biased transistors of the first and second current mirrors is stopped by controlling the current flowing through the first and second switching elements by the fourth switching element. Therefore, in the self-biased transistor, a current flow is controlled by an operation of turning on each switching element, so that a delay in a switching operation with respect to an input signal is suppressed.
Thereby, the sensitivity to the input signal is improved, and the dead zone can be suppressed.

The additional component of the input signal is correctly canceled on the input side by the operation of each switching element.
It is possible to prevent the additional component as described above from affecting the output side and causing noise. In other words, a sufficient additional component can be provided, the sensitivity to the input signal is improved, and the dead zone can be suppressed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a charge pump circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is an explanatory diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration of a conventional charge pump circuit.

FIG. 5 is an explanatory diagram showing a configuration of a conventional charge pump circuit.

FIG. 6 is an explanatory diagram for explaining an operation of a conventional charge pump circuit.

FIG. 7 is an explanatory diagram for explaining an operation of a conventional charge pump circuit.

[Explanation of symbols]

1, 2 P-channel MOS transistors (first and second transistors) 3, 4 N-channel MOS transistors (third and fourth transistors) CM1 first current mirror circuit CM2 second current mirror circuit OUT output terminal C0 Capacitance element SW1 P-channel MOS transistor (first switching element) SW2 N-channel MOS transistor (second switching element) SW3 P-channel MOS transistor (third switching element) SW4 N-channel MOS transistor (fourth switching element) in1 inverter in2 inverter

Claims (2)

(57) [Claims] 1. A capacitor corresponding to a delay or advance of a phase in response to first and second input signals having a pulse width corresponding to a delay or advance of a phase of a specific pulse signal with respect to a reference pulse signal, respectively. A self-biased first transistor having a gate and a drain connected to each other, and a source connected to a first power supply terminal having a first potential. A first current mirror circuit formed by connecting the respective gates of the second transistor to each other; a self-biased third transistor having a gate and a drain connected to each other; and a source connected to a second potential A second current mirror circuit formed by connecting the respective gates of the second transistor of the second conductivity type connected to the second power supply terminal of the second current mirror; An output terminal for connecting the drains of the transistors to each other and charging the capacitive element provided at the connection point; and a connection between the drain of the first transistor and a first constant current source. A first switching element that is turned on in response to the first input signal, is connected between a drain of the third transistor and a second constant current source, and responds to the second input signal. A second switching element, which is turned on and turned on, a connection point between the first switching element and the first constant current source, and the first power supply terminal, and the second input signal A third switching element that is turned on in response to the inverted first inverted signal; a connection between the connection point between the second switching element and the second constant current source and the second power supply terminal And inverts the first input signal. And a fourth switching element that is turned on in response to the second inverted signal. 2. The charge pump circuit according to claim 1, wherein said first and second input signals are inverted and delayed by respective inverters to become second and first inverted signals.