JPH0275874U - - Google Patents
Info
- Publication number
- JPH0275874U JPH0275874U JP15455488U JP15455488U JPH0275874U JP H0275874 U JPH0275874 U JP H0275874U JP 15455488 U JP15455488 U JP 15455488U JP 15455488 U JP15455488 U JP 15455488U JP H0275874 U JPH0275874 U JP H0275874U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- control
- latch
- switching element
- tally
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案のスイツチヤ制御回路のブロツ
ク図、第２図は一般的な２段切替スイツチの系統
図、第３図は従来のスイツチヤ制御回路のブロツ
ク図である。
１……外部制御データ、２……ラツチ回路（瞬
停ホールド機能付）、３……ラツチ・デコード回
路、４……ラツチ回路、５……第１の切替素子制
御出力、６……第２の切替素子制御出力、７……
タリーゲート回路、８……第１の切替素子の制御
データ、９……第２の切替素子の制御データ、１
０……タリーステータス入力、１１……タリーデ
ータ、１２……タリーステータスデータ、１３…
…タリー要求信号、１４……ストローブ信号、１
５……極性変換回路、１６……ＶＴＰ、１７……
入力端子、１８……切替素子、１９……バツフア
アンプ、２０……出力端子。
FIG. 1 is a block diagram of a switch control circuit according to the present invention, FIG. 2 is a system diagram of a general two-stage changeover switch, and FIG. 3 is a block diagram of a conventional switch control circuit. 1... External control data, 2... Latch circuit (with instantaneous power failure hold function), 3... Latch/decode circuit, 4... Latch circuit, 5... First switching element control output, 6... Second Switching element control output of 7...
Tally gate circuit, 8... Control data for the first switching element, 9... Control data for the second switching element, 1
0...Tally status input, 11...Tally data, 12...Tally status data, 13...
...Tally request signal, 14...Strobe signal, 1
5...Polarity conversion circuit, 16...VTP, 17...
Input terminal, 18... switching element, 19... buffer amplifier, 20... output terminal.
Claims (1)
ールドの機能を持つラツチ回路と、ラツチ回路の
出力を再度ラツチ・デコードして第１の切替素子
を制御するラツチ・デコード回路と、第２の切替
素子の制御データをラツチし第２の切替素子を制
御するラツチ回路と、前記ラツチ回路の出力を入
力とし外部からのタリー要求に対してゲートを開
きタリーを出力するタリーゲート回路と、タリー
出力として第１の切替素子の制御ホールドデータ
を出力し、タリーステータスデータとして第２の
切替素子の制御ホールドデータをアクテイブＬＯ
Ｗに変換した信号を出力する回路とを有すること
を特徴とするスイツチヤ制御回路。 A latch circuit that accepts external control data and has latch and momentary power failure hold functions; a latch/decode circuit that relatches and decodes the output of the latch circuit to control the first switching element; and a latch/decode circuit that controls the first switching element. a latch circuit that latches control data to control the second switching element; a tally gate circuit that receives the output of the latch circuit as input and opens a gate in response to an external tally request and outputs a tally; Outputs the control hold data of the second switching element and outputs the control hold data of the second switching element as tally status data.
A switcher control circuit comprising: a circuit that outputs a signal converted into W.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15455488U JPH0275874U (en) | 1988-11-28 | 1988-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15455488U JPH0275874U (en) | 1988-11-28 | 1988-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0275874U true JPH0275874U (en) | 1990-06-11 |
Family
ID=31431388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15455488U Pending JPH0275874U (en) | 1988-11-28 | 1988-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0275874U (en) |
-
1988
- 1988-11-28 JP JP15455488U patent/JPH0275874U/ja active Pending
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