JPH027542A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH027542A
JPH027542A JP15964488A JP15964488A JPH027542A JP H027542 A JPH027542 A JP H027542A JP 15964488 A JP15964488 A JP 15964488A JP 15964488 A JP15964488 A JP 15964488A JP H027542 A JPH027542 A JP H027542A
Authority
JP
Japan
Prior art keywords
circuit
logic elements
layout
integrated circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15964488A
Other languages
Japanese (ja)
Inventor
Yasushi Kawakami
靖 川上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15964488A priority Critical patent/JPH027542A/en
Publication of JPH027542A publication Critical patent/JPH027542A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the mandays of layout modifying work by a method wherein a plurality of logic elements which are not used in the circuit drawings but are to be used for the circuit modification are arranged in raws where logic elements of the integrated circuit automatically designed according to the circuit drawings are arranged, with the gate terminals of the logic elements for circuit modification connected to the power supply line. CONSTITUTION:Logic elements 2 are layout, automatically arranged and wired on the basis of connection information of circuit drawings, for example, an invertor, two-input NANDs, two-input NORs and the like are arranged as arbitrary circuit modifying logic elements 3 without the connecting information which is used in an automatic layout and its gate contact 4 is fixed on a power source. The contact 4 connects a gate so as to fix the gate signal of the circuit modifying logic elements 3 on the power source.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動レイアウトの可能な半導体集積回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit capable of automatic layout.

〔従来の技術〕[Conventional technology]

一般に、半導体集積回路の自動レイアウトは、論理設計
した回路図の接続情報を基に、論理素子、1!能ブロツ
クを自動的に配置、配線するため、その回路機能を実現
するのに必要な配置位置、配線長1種類を十分に満足す
ることができないことがある。この半導体集積回路を拡
散により形成し、評価を行うと、信号線の重負荷によっ
て機能を十分達することができなくなり、レイアウト修
正が必要となる。このレイアウト修正は、最初の工程か
ら始めなければならなくなる。
In general, automatic layout of semiconductor integrated circuits is performed based on the connection information of the logically designed circuit diagram. Since functional blocks are automatically placed and wired, it may not be possible to satisfy one type of placement position and wiring length necessary to realize the circuit function. If this semiconductor integrated circuit is formed by diffusion and evaluated, it will not be able to achieve sufficient functionality due to the heavy load on the signal lines, and the layout will need to be modified. This layout modification will have to start from the first step.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体集積回路の自動レイアウトは、半
導体集積回路が実現すべき機能を十分に満足するために
必要とされる配置位置、配線長。
The conventional automatic layout of semiconductor integrated circuits described above determines the placement positions and wiring lengths required to fully satisfy the functions that the semiconductor integrated circuit should achieve.

種類を任意に指定することができないため、自動レイア
ウトで配置、配線された結果、信号線に必要以上の負荷
があって機能障害を起したような場合、レイアウト修正
を最初の工程から始めなければならず、莫大な費用と工
数がかかるという欠1点がある。
Since it is not possible to specify the type arbitrarily, if the signal line is placed and routed using automatic layout, and a signal line is overloaded and malfunctions, it is necessary to start correcting the layout from the beginning. However, one drawback is that it requires a huge amount of cost and man-hours.

本発明の目的は、このような欠点を除き、当初の設計回
路より多い付加回路を設けることにより、後からの回路
修正、レイアウト修正を可能にした半導体集積回路を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit which eliminates such drawbacks and allows subsequent circuit modifications and layout modifications by providing more additional circuits than the originally designed circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路の構成は、回路図に従って自動
レイアウトされた集積回路の論理素子が配置された各列
に、前記回路図で使わない複数の回路変更用論理素子を
、そのゲート端子を電源ラインに接続して配置したこと
を特徴とする。
In the configuration of the semiconductor integrated circuit of the present invention, a plurality of logic elements for circuit modification not used in the circuit diagram are placed in each column in which the logic elements of the integrated circuit automatically laid out according to the circuit diagram are arranged, and their gate terminals are connected to the power supply. It is characterized by being connected to the line.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を説明する半導体集積回路の
レイアウト図である。このレイアウトにおいて、1は電
源ライン、2は各種論理素子、3は当初の設計に使用し
ていない回路変更用論理素子、4は回路変更用論理素子
3のゲート信号を電源に固定するようにゲートを接続す
るコンタクトである。
FIG. 1 is a layout diagram of a semiconductor integrated circuit illustrating an embodiment of the present invention. In this layout, 1 is a power supply line, 2 is various logic elements, 3 is a logic element for circuit modification that is not used in the original design, and 4 is a gate that fixes the gate signal of logic element 3 for circuit modification to the power supply. This is the contact that connects the

このように本実施例において、論理素子2は、回路図の
接続情報を基に自動的に配置、配線されたレイアウトで
あり、このレイアウト各列に、自動レイアウトで使用し
た接続情報が存在しない任意の回路変更用論理素子3と
して、例えばインバータ、2人力NAND、2人力NO
R等を配置し、そのゲートコンタクト4を電源に固定し
たものである。
In this way, in this embodiment, the logic element 2 is in a layout that is automatically placed and wired based on the connection information of the circuit diagram, and in each column of this layout, there is an arbitrary layout in which the connection information used in the automatic layout does not exist. As the logic element 3 for changing the circuit, for example, an inverter, a two-man NAND, a two-man NO
R, etc. are arranged, and the gate contact 4 is fixed to a power source.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、最初から第1回の論理回
路レイアウトでは必要としない論理素子をレイアウト中
に作込んでおくことにより、自動レイアウトされた半導
体集積回路の拡散、評価後、配置、配線の不具合による
信号線の重負荷などで機能を十分に満足できない場合に
も、各列に作込んだ回路変更用論理素子を用いて配線と
コンタクト工程のみの変更で機能対応ができ、レイアウ
ト変更工数の削減、費用の削減、納期の短縮に非常に大
きな効果がある。
As explained above, the present invention enables diffusion, evaluation, and placement of automatically laid out semiconductor integrated circuits by incorporating logic elements that are not required in the first logic circuit layout into the layout from the beginning. Even if the function cannot be fully satisfied due to heavy load on the signal line due to a wiring defect, the function can be changed by changing only the wiring and contact process using logic elements for circuit modification built in each column, making it possible to change the layout. It is extremely effective in reducing man-hours, costs, and delivery times.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明する半導体集積回路の
レイアウト図である。 1・・・電源ライン、2・・・任意の論理素子、3・・
・回路変更用論理素子、4・・・ゲート入力のコンタク
ト。
FIG. 1 is a layout diagram of a semiconductor integrated circuit illustrating an embodiment of the present invention. 1...Power supply line, 2...Arbitrary logic element, 3...
・Logic element for circuit modification, 4...Gate input contact.

Claims (1)

【特許請求の範囲】[Claims] 回路図に従って自動レイアウトされた集積回路の論理素
子が配置された各列に、前記回路図で使わない複数の回
路変更用論理素子を、そのゲート端子を電源ラインに接
続して配置したことを特徴とする半導体集積回路。
A plurality of logic elements for circuit modification not used in the circuit diagram are arranged in each column in which logic elements of an integrated circuit automatically laid out according to the circuit diagram are arranged, with their gate terminals connected to a power supply line. Semiconductor integrated circuit.
JP15964488A 1988-06-27 1988-06-27 Semiconductor integrated circuit Pending JPH027542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15964488A JPH027542A (en) 1988-06-27 1988-06-27 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15964488A JPH027542A (en) 1988-06-27 1988-06-27 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH027542A true JPH027542A (en) 1990-01-11

Family

ID=15698217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15964488A Pending JPH027542A (en) 1988-06-27 1988-06-27 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH027542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02283048A (en) * 1989-04-25 1990-11-20 Fujitsu Ltd Manufacture of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181643A (en) * 1983-03-31 1984-10-16 Toshiba Corp Semiconductor integrated circuit
JPS6161437A (en) * 1984-09-03 1986-03-29 Toshiba Corp Semiconductor integrated circuit device
JPS62123739A (en) * 1985-11-25 1987-06-05 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181643A (en) * 1983-03-31 1984-10-16 Toshiba Corp Semiconductor integrated circuit
JPS6161437A (en) * 1984-09-03 1986-03-29 Toshiba Corp Semiconductor integrated circuit device
JPS62123739A (en) * 1985-11-25 1987-06-05 Hitachi Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02283048A (en) * 1989-04-25 1990-11-20 Fujitsu Ltd Manufacture of semiconductor device

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