JPH0273705A - Oscillation circuit - Google Patents

Oscillation circuit

Info

Publication number
JPH0273705A
JPH0273705A JP22613288A JP22613288A JPH0273705A JP H0273705 A JPH0273705 A JP H0273705A JP 22613288 A JP22613288 A JP 22613288A JP 22613288 A JP22613288 A JP 22613288A JP H0273705 A JPH0273705 A JP H0273705A
Authority
JP
Japan
Prior art keywords
oscillation
circuit
turned
transistor
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22613288A
Other languages
Japanese (ja)
Inventor
Akira Yazawa
矢沢 晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22613288A priority Critical patent/JPH0273705A/en
Publication of JPH0273705A publication Critical patent/JPH0273705A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the lower limit of the operating power voltage low more than that of a negative power supply Vss by switching the state of oscillation and stop with a MOS transistor(TR) provided between a power supply and an input terminal of an inverse circuit. CONSTITUTION:Feedback MOS TRs 1, 2 are connected between an input terminal and an output terminal of an inverse circuit 5, an N-channel MOS TR 6 is provided between an OSCIN and the inverse circuit and an oscillation start terminal as a control signal terminal is connected to the gate and gates of feedback resistor MOS TRs 1, 2. Thus, the feedback resistor MOS TRs 1, 2 are turned on in the oscillation and since the N-channel MOS TR G is turned off, then the circuit is oscillated. On the other hand, the feedback MOS TRs 1, 2 are turned off at the oscillation stop and since the N-channel MOS TR 6 is turned on, the level of the input of the inverse circuit 5 is decreased up to the Vss level and then the oscillation is stopped. Thus, it is possible to decrease the lower limit of the operating power voltage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は発振回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an oscillation circuit.

〔従来の技術〕[Conventional technology]

第3図は従来の発振回路の一例を説明するための回路図
である。同図に示すように、VDD及びV99は正、負
電源を表わし、P型MO3)ランジスタ1とN型MOS
トランジスタ2はそれぞれゲートがV911. vIl
flに接続されており、帰還抵抗として動作する。P型
MOSトランジスタ11.12及びN型MO3)ランジ
スタ13.14はナンド回路を構成シテおり、O20I
NとO20OUTは水晶振動子等の振動子と接続される
。ナンド回路には、発振開始信号とO20IN端子がら
の信号が入力され、出力はO20CUT端子及び、O8
C信号として出力される。そこで、発振開始信号が■。
FIG. 3 is a circuit diagram for explaining an example of a conventional oscillation circuit. As shown in the figure, VDD and V99 represent positive and negative power supplies, and P-type MO3) transistor 1 and N-type MOS
Transistor 2 has its gate at V911. vIl
It is connected to fl and operates as a feedback resistor. P-type MOS transistors 11.12 and N-type MO3) transistors 13.14 constitute a NAND circuit, and O20I
N and O20OUT are connected to a resonator such as a crystal resonator. The oscillation start signal and signals from the O20IN terminal are input to the NAND circuit, and the output is from the O20CUT terminal and the O8 terminal.
It is output as a C signal. Therefore, the oscillation start signal is ■.

DレベルのときはP型MO8)ランジスタ11はオフ状
態となり、ナンド回路は反転回路として動作し発振する
。一方、発振開始信号がv、3レベルのときはP型MO
3)ランジスタ11がオン状態になるためナンドの出力
は常にVD+)レベルとなり発振は止められる。このよ
うに、ナンドの一方の入力を発振開始信号とすることに
より発振状態の切換えを可能にしている。
At D level, the P-type MO8) transistor 11 is turned off, and the NAND circuit operates as an inverting circuit and oscillates. On the other hand, when the oscillation start signal is v, level 3, the P-type MO
3) Since the transistor 11 is turned on, the NAND output is always at the VD+) level and oscillation is stopped. In this way, by using one input of the NAND as the oscillation start signal, it is possible to switch the oscillation state.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の発振回路は、ナンド回路を使用すること
によって発振の開始、停止を行なっている。ところがナ
ンドはその構成上N型MO8)ランジスタ13及び14
が縦積み2段となってしまい、このことが動作電源電圧
の下限を引き上げてしまうという欠点がある。
The conventional oscillation circuit described above uses a NAND circuit to start and stop oscillation. However, due to its configuration, NAND is equipped with N-type MO8) transistors 13 and 14.
are stacked vertically in two stages, which has the disadvantage of raising the lower limit of the operating power supply voltage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の発振回路は反転回路と、前記反転回路の入力端
子及び出力端子間に設けられた帰還抵抗用MOSトラン
ジスタと、前記反転回路の入力端子と電源間に設けられ
たトランジスタから成り、発振時には前記帰還抵抗用M
O3)ランジスタをオン、前記トランジスタをオフにし
、発振停止時には前記帰還抵抗用MO8)ランジスタを
オフ、前記トランジスタをオンにすることにより構成さ
れる。
The oscillation circuit of the present invention includes an inverting circuit, a feedback resistor MOS transistor provided between the input terminal and the output terminal of the inverting circuit, and a transistor provided between the input terminal of the inverting circuit and the power supply. M for the feedback resistor
O3) Turns on the transistor and turns off the transistor, and when oscillation is stopped, MO8) Turns off the transistor for the feedback resistor and turns on the transistor.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を説明するための発振回
路の回路図である。同図に示すように、O20INとO
20CUTの間に水晶振動子等の振動子が接続され、M
OSトランジスタがら成る反転回路5の入力端子と出力
端子間に帰還抵抗用MO8)ランジスタ1及び2を接続
する。08CINと反転回路らの間にN型MOS)ラン
ジスタロを設け、そのゲート及び帰還抵抗用MO3)ラ
ンジスタ1及び2のゲートに制御信号端子としての発振
開始端子を接続する。P型MO3)ランジメタ1.N型
MO3)ランジスタ2は発振開始信号によりスイッチン
グされ、発振時には帰還抵抗として動作し、発振停止時
にはオフされる。これにより、発振停止時のVDDから
トランジスタ6へ流れ込む電流を防止することができる
。P型MOSトランジスタ3.N型MOSトランジスタ
は反転回路5を構成し、入力はO20IN端子に、出力
はO20OUT端子に出力されると同時に、反転回路8
を介してO8C信号として出力される。
FIG. 1 is a circuit diagram of an oscillation circuit for explaining a first embodiment of the present invention. As shown in the figure, O20IN and O
A resonator such as a crystal resonator is connected between 20CUT, and M
Feedback resistor MO8) transistors 1 and 2 are connected between the input terminal and output terminal of the inverting circuit 5 consisting of OS transistors. An N-type MOS transistor is provided between 08CIN and the inverting circuit, and an oscillation start terminal as a control signal terminal is connected to its gate and the gates of MO3) transistors 1 and 2 for feedback resistance. P type MO3) Langimeta 1. The N-type MO3) transistor 2 is switched by an oscillation start signal, operates as a feedback resistor during oscillation, and is turned off when oscillation is stopped. This can prevent current from flowing into the transistor 6 from VDD when oscillation is stopped. P-type MOS transistor 3. The N-type MOS transistor constitutes an inverting circuit 5, and the input is output to the O20IN terminal and the output is output to the O20OUT terminal.
It is output as an O8C signal via the .

N型MOS)ランジスタロは反転回路5の入力と電源7
33間に入り、ゲートには発振開始信号の反転信号が入
力されている。つまり、発振時には帰還抵抗用MO3)
ランジスタ1,2はオンし、N型MOS)ランジスタロ
はオフするため発振する。
N-type MOS) Ranjistaro is the input of the inverting circuit 5 and the power supply 7
33, and an inverted signal of the oscillation start signal is input to the gate. In other words, during oscillation, MO3 for feedback resistor)
Transistors 1 and 2 are turned on, and N-type MOS transistor transistor 2 is turned off, causing oscillation.

一方、発振停止時には帰還用MO8)ランジスタ1.2
はオフし、N型MOS)ランジスタロはオンするため反
転回路5の入力はVSSレベルまで弓き下げられ、発振
は停止する。このように帰還抵抗用MO8)ランジスタ
1,2及びN型MOSトランジスタ6を発振開始信号に
よりオン、オフすることにより発振状態及び発振停止を
行なうことができる。反転回路8は反転回路5と同じ入
力スレッショルドを持ち、O3C信号がデユーティ−5
0%となるように設計されているが、デユーティ−50
%必要でなければ特に必要としない。
On the other hand, when the oscillation is stopped, the feedback MO8) transistor 1.2
is turned off and the transistor (N type MOS) is turned on, so the input of the inverting circuit 5 is lowered to the VSS level and oscillation is stopped. In this way, by turning on and off the feedback resistor MO8) transistors 1 and 2 and the N-type MOS transistor 6 in response to the oscillation start signal, the oscillation state and oscillation stop can be established. The inverting circuit 8 has the same input threshold as the inverting circuit 5, and the O3C signal has a duty of -5.
It is designed to be 0%, but the duty is -50
%Not particularly required unless necessary.

第3図は本発明の第2の実施例を説明するための発振回
路の回路図である。P型MO8)ランジメタ1.N型M
O3)ランジスタ2で構成される帰還抵抗、及びP型M
O8)ランジスタ3.N型MoSトランジスタ4で構成
される反転回路5、及び反転回路8は第1の実施例と同
様である。P型MO8)ランジスタフが反転回路5の入
力と電源vl、D間に入り、発振開始信号がゲート入力
されており発振停止時に反転回路5の入力を第1の実施
例とは逆にVSSレベルに引き上げるものである。
FIG. 3 is a circuit diagram of an oscillation circuit for explaining a second embodiment of the present invention. P type MO8) Langimeta 1. N type M
O3) Feedback resistor composed of transistor 2 and P type M
O8) Transistor 3. The inverting circuit 5 and the inverting circuit 8, which are constituted by an N-type MoS transistor 4, are the same as those in the first embodiment. P-type MO8) Langistav is inserted between the input of the inverting circuit 5 and the power supplies vl and D, and the oscillation start signal is input to the gate, and when the oscillation is stopped, the input of the inverting circuit 5 is set to the VSS level, contrary to the first embodiment. It is something to raise.

上述した2つの実施例においても、もしN型MOS)ラ
ンジスタロ、P型MO8)ランジスタフを反転回路5の
出力端子と電源間にそれぞれ設けた場合、反転回路5の
入力端子のレベルが発振停止時に固定されず、このため
ノイズ等の影響でトランジスタ3および6が共にオン、
トランジスタ4および7が共にオンしてしまい、直流電
流が電源間に流れてしまう欠点がある。
In the two embodiments described above, if an N-type MOS Langistaro and a P-type MOS Langistur are provided between the output terminal of the inverting circuit 5 and the power supply, the level of the input terminal of the inverting circuit 5 is fixed when oscillation is stopped. Therefore, both transistors 3 and 6 are turned on due to the influence of noise, etc.
There is a drawback that both transistors 4 and 7 are turned on, and direct current flows between the power supplies.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は反転回路の入力端子と電源
間に設けられたMOS)ランジスタにより発振時と停止
時を切換えることにより、動作電源電圧の下限をV3S
まで低く出来る効果がある。
As explained above, the present invention sets the lower limit of the operating power supply voltage to V3S by switching between oscillation and stop using a MOS transistor provided between the input terminal of the inverting circuit and the power supply.
It has the effect of lowering the

更に、停止時には帰還用MO8)ランジスタはオフ状態
となっているため、余分な電流が流れるのを防止できる
。また、発振の為に必要な反転回路に、発振開始、停止
の為の特別なゲートが存在しないため、発振回路の設計
も非常に楽になるという効果もある。
Furthermore, since the feedback transistor MO8) is in an off state when the motor is stopped, excess current can be prevented from flowing. Furthermore, since there is no special gate for starting and stopping oscillation in the inverting circuit required for oscillation, the design of the oscillation circuit is also very easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例を説明するための発振回
路の回路図、第2図は本発明の第2の実施例を説明する
ための発振回路の回路図、第3図は従来の発振回路の一
例を説明するための回路図である。 1、.3.7・・・・・・P型MO8)ランジスタ、2
゜4.6・・・・・・N型MO3)ランジスタ、5,8
・・・・・・反転回路。 代理人 弁理士  内 原   晋 粥1図 傷z区
FIG. 1 is a circuit diagram of an oscillation circuit for explaining a first embodiment of the present invention, FIG. 2 is a circuit diagram of an oscillation circuit for explaining a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an oscillation circuit for explaining a second embodiment of the present invention. FIG. 2 is a circuit diagram for explaining an example of a conventional oscillation circuit. 1. 3.7...P-type MO8) transistor, 2
゜4.6...N-type MO3) transistor, 5,8
・・・・・・Inversion circuit. Agent Patent Attorney Uchihara Shingayu 1

Claims (1)

【特許請求の範囲】[Claims] 反転回路と、前記反転回路の入力端子及び出力端子間に
設けられた帰還抵抗用トランジスタと、前記反転回路の
入力端子と電源間に設けられたトランジスタとを有し、
発振時には前記帰還抵抗用トランジスタをオン、前記ト
ランジスタをオフにし、発振停止時には前記帰還抵抗用
トランジスタをオフ、前記トランジスタをオンにするこ
とを特徴とする発振回路。
an inverting circuit, a feedback resistance transistor provided between an input terminal and an output terminal of the inverting circuit, and a transistor provided between the input terminal of the inverting circuit and a power supply,
An oscillation circuit characterized in that the feedback resistor transistor is turned on and the transistor is turned off during oscillation, and the feedback resistor transistor is turned off and the transistor is turned on when oscillation is stopped.
JP22613288A 1988-09-08 1988-09-08 Oscillation circuit Pending JPH0273705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22613288A JPH0273705A (en) 1988-09-08 1988-09-08 Oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22613288A JPH0273705A (en) 1988-09-08 1988-09-08 Oscillation circuit

Publications (1)

Publication Number Publication Date
JPH0273705A true JPH0273705A (en) 1990-03-13

Family

ID=16840349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22613288A Pending JPH0273705A (en) 1988-09-08 1988-09-08 Oscillation circuit

Country Status (1)

Country Link
JP (1) JPH0273705A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200986A (en) * 1983-04-28 1984-11-14 Seiko Epson Corp Analog electronic timepiece

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59200986A (en) * 1983-04-28 1984-11-14 Seiko Epson Corp Analog electronic timepiece

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