JPH0273505A - Reading circuit - Google Patents

Abstract

PURPOSE:To attain a high-speed switching operation and to execute a high-speed reading by making small the time constant of an AGC circuit when the fluctuation of a bias voltage exceeds a prescribed voltage and quickening the convergence of transient response. CONSTITUTION:A read signal from a storage device is inputted to an AGC circuit 19 through a capacitor 20. The integration time constant of a circuit 38 to detect the amplitude of the output signal of the circuit 19 can be changed. The read signal is inputted to a comparator 22 through an LPF 21, compared with a reference voltage level, and when it is within a prescribed range, a timer 23 outputs a pulse signal with a prescribed time width in accordance with a decision signal. A switching means 36 switches the integration time constant of the circuit 38 so that it may be smaller than usual in a period specified by the pulse width. When the fluctuation of the bias voltage caused by the transient response generated at the time of switching preamplifiers 10-13 or at the time of the switching of a read operation and a write operation exceeds the prescribed range, the integration time constant of the circuit 38 is controlled to be small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a read circuit for a data storage device used in an information processing device, and particularly to a read circuit suitable for use in a high-speed magnetic disk device.

[Conventional technology]

Conventional readout circuits of this type include those shown in FIGS. 3 and 4. The readout circuit in FIG.
4 to 17, preamplifiers (hereinafter abbreviated as PRA) 10 to 13 provided in each of the magnetic heads 14 to 17, the wired-ORed output terminals of PRAlO to 13, and an automatic gain control circuit (hereinafter abbreviated as AGC). ) 19 input terminals, and a capacitor 20 inserted in series between the 19 input terminals. AG
C19 is composed of a voltage control amplifier (hereinafter abbreviated as VCA) 37, an amplitude detection circuit (hereinafter abbreviated as DET) 38, and an integrating capacitor 41. Furthermore, the response characteristic of the AGCl 9 determined by the capacitor 41 is set so that it is difficult to follow instantaneous amplitude fluctuations of the read signal due to external noise or the like.

When the read signal is superimposed with a transient response when switching from a write operation to a read operation or when PRAIO to 13 are switched by the PRA selection signal 106, a transient response due to a DC voltage step resulting from a difference in the individual output offset voltages is superimposed on the capacitor 20. The electric charge is charged and a DC component is generated, and the AG
This will adversely affect the operation of C19. That is,
Since the voltage step is directly applied to the AGC 19, the 80C 19 operates to respond to amplitude fluctuations corresponding to the voltage step. There is a drawback that it takes time for the AGC output signal 104, which is the output signal, to become stable.

The readout circuit shown in FIG. 4 is an improvement over the above-mentioned drawbacks of the conventional circuit shown in FIG. In addition to the configuration shown in FIG. 3, the readout circuit shown in FIG. An integrating capacitor 35 is provided which is grounded via a . The combined capacitance of capacitor 34 and capacitor 35 is set to a value equivalent to the value of capacitor 41 in FIG.

Analog switch 36 is turned on and off in response to external logic signal 50. External logic signal 50 is generated to turn off analog switch 36 for a predetermined period of time in synchronization with the switching between write and read operations and the switching by PRA selection signal 106. According to the readout circuit shown in FIG. 4, by turning off the analog switch 36 for a predetermined period of time when switching between write and read operations and switching by the PRA selection signal 106, the capacitor 35 is disabled and the integration time constant is changed to the capacitor 34. Minimize as only due to. As a result, the time for stabilizing the amplitude fluctuation of the AGC output signal 104 caused by a transient response can be accelerated.

[Problem to be solved by the invention]

As mentioned above, the readout circuit shown in FIG. 3 has the drawback that it takes time for the readout signal to become stable, making it unsuitable for high-speed readout operations, while the readout circuit shown in FIG. 4 is unsuitable for high-speed readout operations. However, since a control signal called the external logic signal 50 is added, it is necessary to add an interface signal between the readout circuit and the control circuit. Adding an interface signal is not a big problem for large data storage devices, but it becomes a big problem for small models.

Another problem is that when the interface is standardized, it is impossible to add signal lines.

The present invention was made in view of these circumstances, and
The object of the present invention is to provide a circuit that can read data at high speed without requiring an interface signal with an external control circuit.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a capacitor inserted in series in a transmission line through which a read signal read from a storage device is transmitted, and the read signal is input to an automatic gain control circuit through this capacitor. The readout circuit is configured to be able to change an integration time constant of a detection signal of an amplitude detection circuit that detects the amplitude of an output signal of the automatic gain control circuit, and receives an input signal of the automatic gain control circuit;
A low pass filter that removes high frequency components of this signal,
a comparator that compares the level of the output signal of the low-pass filter with a reference voltage level and determines whether the level of the output signal of the low-pass filter is within a predetermined range;
A timer that outputs a pulse signal of a predetermined time width in response to a determination signal output when the level of the output signal of the low-pass filter is determined to be within a predetermined range by this comparator, and a pulse output from this timer. The present invention is characterized in that it has a switching means that receives the signal and switches the integration time constant of the detection signal of the amplitude signal circuit to be smaller than usual during a period defined by the pulse width of the signal.

According to the present invention, the level of the read signal is adjusted when the bias voltage fluctuation due to the transient response that occurs when switching the preamplifier that amplifies the read signal or when switching between the read operation and the write operation exceeds a predetermined range. The integration time constant of the automatic gain control circuit that performs this is controlled to be small. This allows high-speed reading without requiring an interface signal with an external control circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a readout circuit according to the present invention. In the figure, the readout circuit includes a plurality of magnetic heads 14 to 17 and preamplifiers (hereinafter abbreviated as PRA) 10 to 1 that amplify the output signals of each of the magnetic heads 14 to 17.
A capacitor 20 is inserted in series between A 3 and the input terminal of an automatic gain control circuit (hereinafter referred to as AGC) 19;
A low pass filter (hereinafter abbreviated as LPF) 21 receives the input signal of the GC 19, and a first filter receives the output signal of the LPF 21.
a voltage of +V volts is applied to the second input terminal,
A comparator (hereinafter abbreviated as COMP) 22 to which a voltage of −■ volts is input to the third input terminal, and CO
MP22(7) Timer to which the output signal is input (hereinafter referred to as T
(abbreviated as M) 23.

Further, the AGC 19 is a voltage control amplifier (hereinafter referred to as VCA, l!) whose first input terminal receives an input signal of the AGC 19.
:omitted) 37, and AG which is the VCA37(7) output signal.
An amplitude detection circuit (hereinafter abbreviated as DET) 38 to which the C output signal is input, a capacitor 34, 35 that integrates the output signal of DET38, and an on/off control input terminal provided between the capacitor 35 and the ground, which receives the output signal of TM23. and an analog switch 36 to which the TM output signal 105 is input. Further, the output signal of the DET 38 is input to the second input terminal of the VCA 37. Figure 2 shows waveforms of various parts of the readout circuit shown in Figure 1.

Next, FIG. 1 shows the operation of the readout circuit according to this embodiment.
This will be explained with reference to FIG. The PRA selection signal 106 applied to PRA10-13 is
, the selected PRA is activated, and the other PRAs are inactivated. Now, PRA
When IO is selected and in operation, the hend output signal 90 of the magnetic head 14 is amplified by the PRAIO with a predetermined gain, and the PRA output signal 100 is output.

The bias DC voltage of the PRA output signal 100 is PRAIO
is unique to The bias DC voltage is removed from the PRA output signal 100 by a capacitor 20, and the AGC 19
The bias DC voltage of the AGC input signal 101, which is the 0 input signal, becomes the input bias voltage of the AGCl 9.

The VCA 37 amplifies the AGC input signal 101 input to the first input terminal with a gain corresponding to the voltage input to the second input terminal, and outputs the amplified signal.

The DET 38 receives the AGC output signal 104, compares an internal predetermined voltage with the amplitude of the ΔGC output signal 104, and outputs a DET output signal 107 corresponding to their magnitude. The response speed of the DET output signal 107 is determined by the time constant due to the parallel combined capacitance of the capacitor 34 and the capacitor 35 when the analog switch is on.
6 is off, the response speed is determined by the time constant determined by the capacitance of the capacitor 34 alone.

Furthermore, the response speed of the amplitude response of the AGC output signal 104 is determined in exactly the same manner as the DET output signal 107.

The LPF 21 is for suppressing the signal component of the AGC input signal 101, and the cutoff frequency is set sufficiently lower than the signal frequency, but the response speed of the LPF output signal 102, which is the output signal, must also be considered. It's not good if it's too low.

COMP22 compares the voltage of the LPF output signal 102 with the voltages of +■ volts and -V volts, and outputs the LPF output signal 102.
When the voltage is higher than +V volts or lower than -■ volts, a high level signal is output, otherwise a low level signal is output. TM23 is a circuit that outputs a positive pulse of time T in synchronization with the rising waveform of the COMP output signal 103.

The analog switch 36 is turned off when the TM output signal 105 is at a high level, and turned on when it is at a low level.

The capacitance value of the capacitor 34 is set to be sufficiently smaller than that of the capacitor 35, and the parallel combined capacitance of the capacitor 34 and the capacitor 35 is set to a value that makes it difficult for the response of the AGC 19 to follow instantaneous amplitude fluctuations such as external noise. .

If the PRA selection signal 106 changes at switching time 32 shown in FIG. 2 and switches from PRA 10 to PRAII,
The DC bias voltage and signal amplitude of the PRA output signal 100 vary as shown in FIG. LPF output signal 10
2 becomes larger than +V volts, the COMP output signal 103 becomes high level, and in synchronization with this rise, a positive pulse with a pulse width of time T is output from TM23.

During the time period T when the TM output signal 105 is at a high level, the analog switch 36 is turned off. This speeds up the convergence of the transient response of the DET output signal 107, and similarly speeds up the convergence of the amplitude fluctuation of the AGC output signal 104. A broken line 43 shows the amplitude fluctuation when the analog switch 36 continues to be turned on.

〔Effect of the invention〕

As explained above, in the present invention, bias voltage fluctuations accompanying transient responses that occur when switching preamplifiers, etc. are detected, and when this fluctuation exceeds a predetermined voltage range, the automatic gain control circuit integrates Since the configuration is configured such that the convergence of the transient response is accelerated by reducing the constant, the present invention enables high-speed switching operation and therefore high-speed reading.

Furthermore, since this control does not require an interface with an external circuit, it can be applied to all types of magnetic storage devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a readout circuit according to the present invention, FIG. 2 is a waveform diagram showing the operating state of FIG. 1, and FIG. 3 is an example of the configuration of a conventional readout circuit. Block Diagram FIG. 4 is a block diagram showing another example of the configuration of a conventional readout circuit. IO~13...Preamplifier, 14~17...Magnetic head, 19...Automatic gain control circuit, 21...Low pass filter, 22... ... Comparator, 23 ... Timer, 36 ... Analog switch. Map 2 applicant: NEC Corporation agent
Patent Attorney Umeo Yamauchi 3 maps, 1 map, 4 maps, 1 map

Claims (1)

[Claims] A capacitor is inserted in series with a transmission line through which a read signal read from a storage device is transmitted, and the read signal is input to an automatic gain control circuit via this capacitor. The readout circuit is configured to be able to change an integration time constant of a detection signal of an amplitude detection circuit that detects the amplitude of an output signal of the automatic gain control circuit, and receives an input signal of the automatic gain control circuit, and receives an input signal of the automatic gain control circuit. a low-pass filter that removes high-frequency components; a comparator that compares the level of the output signal of the low-pass filter with a reference voltage level and determines whether the level of the output signal of the low-pass filter is within a predetermined range; a timer that outputs a pulse signal of a predetermined time width in response to a determination signal output when it is determined that the level of the output signal of the low-pass filter is outside the predetermined range; and a timer that outputs a pulse signal of a predetermined time width. 1. A readout circuit comprising: a switching circuit for switching an integration time constant of a detection signal of the amplitude detection circuit to be smaller than normal for a period defined by the pulse width thereof.