JPH02152318A - Pulse detecting circuit - Google Patents

Abstract

PURPOSE:To remove a noise without fail by changing a set amplification factor so that the output level of an amplifying circuit can be in a fixed range. CONSTITUTION:When the set amplification factor of a variable amplifying circuit 1' is 50dB, the amplitude of a fine amplitude input signal 21 passes through the circuit 1' and an amplifying signal 22', for which a truth signal component amplitude achieves a saturation level and a noise amplitude goes to be 2.5V, is obtained. Then, the noise is not removed in a peak clamp circuit 2. Next, when the set amplification factor is 35dB, the amplifying signal 22', for which the truth signal component amplitude is 1.4V and the noise amplitude is 0.44V, is obtained and this noise is removed in the circuit 2. Then, only a truth signal component is obtained as a peak clamp signal 23. The signal 23 is transformed to a logical level in a comparing circuit 3 and defined as a detecting signal 24.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention amplifies a minute amplitude input signal, removes unnecessary signal components (hereinafter abbreviated as noise) using a piece level clamp, and converts the true signal into a true signal. Regarding the pulse detection circuit that detects only the component, it is particularly useful for video tape recorders (hereinafter referred to as VTR).
(abbreviated as )).

[Conventional technology]

Conventionally, this type of pulse detection circuit has an amplifier circuit and a peak/peak detection circuit.
It consists of a clamp circuit and a comparison circuit.

The conventional example shown in FIG. 2 is composed of an amplifier circuit 1, a peak clamp circuit 2, and a comparison circuit 3.

The amplifier circuit 1 receives a small amplitude input signal 21, amplifies it by a set amplification amount, and outputs an amplified signal 22.

The peak clamp circuit 2 receives the amplified signal 22 as input, removes noise using a set clamp characteristic from the peak level of the true signal component, and generates a peak clamp signal 23.
Output. The comparison circuit 3 inputs the peak clamp signal 23, converts the true signal component into a logic level by comparing it with a reference level, and outputs a detection signal 24.

FIG. 3 is a timing chart for explaining the operation of the conventional example shown in FIG.

Figure 3 shows that the true signal component amplitude 5 of the minute amplitude input signal 21 is mV, the noise amplitude is 1.58 mV, and the repetition frequency is fl.
In addition, the set amplification factor of the amplifier circuit 1 is 50 dB, the set clamp characteristic of the peak clamp circuit 2 is gentle (indicated by a broken line), the reference level of the comparator circuit 3 is 1 V, and all the circuits are This is an example in which the operating power supply potential is 5V and the operating point potential is 2.5V (reference power supply: Ov).

First, the amplitude of the small amplitude input signal 2 is amplified by the amplifier circuit l, the true signal component amplitude is L58V, and the noise amplitude is 0.5V.
An amplified signal 22 of v is obtained. Next, this amplified signal 22
The noise in is removed by the peak clamp circuit 2,
Only the true signal components are obtained as peak clamp signal 23. Finally, the analog level of this peak clamp signal 23 is converted to a logic level by the comparison circuit 3, and a detection signal 24 is obtained.

FIG. 4 is also another timing chart for explaining the operation of the conventional example shown in FIG.

FIG. 4 shows that the true signal component amplitude of the minute amplitude input signal 21 is 25 mV, the noise amplitude is 7.9 mV, and the repetition frequency is 2.
5.f, and the credit union is the same as the case in FIG. 3 above.

In the amplified signal 22, the true signal component amplitude reaches a saturated level, and the noise amplitude becomes 2.5V. Therefore, the peak
The clamp characteristic is not effective and noise appears in the detection signal 24.

[Problem to be solved by the invention]

In the conventional pulse detection circuit described above, since the set amplification factor of the amplifier circuit 1 is constant, when the amplitude of the minute amplitude input signal 21 increases and the noise amplitude reaches the saturation level, the peak clamp characteristic becomes ineffective. , which has the disadvantage of not being able to remove noise.

In particular, when this conventional example is used in a pulse detection circuit for a repeating huntroll signal in a VTR, the noise amplitude increases with the increase in the amplitude of the true signal component during high-speed playback, that is, when the playback control signal frequency increases, making it a good choice. The disadvantage is that accurate tracking may not be obtained.

[Means to solve the problem]

The pulse detection circuit of the present invention includes an amplifier circuit that can change the set amplification factor, a noise canceler circuit that removes noise from the output of the amplifier circuit, and a comparison circuit that converts the logic level of only the true signal component obtained by the amplifier circuit. the first and second inputs of the amplifier circuit are connected to the minute amplitude input signal terminal and the set amplification factor data signal terminal, the output is connected to the input terminal of the noise canceller circuit, and the output of the noise canceller circuit is connected to the input terminal of the noise canceller circuit. Connect to the input end of the comparison circuit,
The output of the comparison circuit is connected to a detection signal terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment of the pulse detection circuit shown in FIG. 1 includes a variable frequency divider circuit 1', a peak clamp circuit 2, and a comparator circuit 3.

The second and second inputs of the variable amplification circuit 1' are connected to the terminal of the minute amplitude input signal 21 and the terminal of the setting amplification factor data signal 25, and the output is connected to the output terminal of the amplified signal 22', respectively. The input of peak clamp circuit 2 is amplified signal 2
2', the outputs are connected to the outputs of the peak clamp signal 23, respectively. The input of the comparison circuit 3 is connected to the output terminal of the peak clamp signal 23, and the output is connected to the terminal of the detection signal 24.

Next, its operation will be explained.

FIG. 5 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 5 shows that the true signal component amplitude of the small amplitude input signal 21 is 2.
5 m V s The noise amplitude is 7.9 mV, the repetition frequency is 25 f, and the set amplification factor of the variable amplifier circuit 1' is initially 50 dB depending on the set amplification factor data signal.
However, it is set to 35 dB so that the amplified signal is in the range of 1v to 2v, and furthermore, the setting clamp characteristic of the peak clamp circuit 2 is gentle (indicated by a broken line), and the setting clamp characteristic of the comparison circuit 3 is set to 35 dB. The reference level is IV, the operating power supply voltage of all circuits is 5■, and the operating point potential is 2.5V (reference potential:
This is an example of the case of Ov).

Initially, since the set amplification factor is 50 dB, the amplitude of the minute amplitude input signal 21 is amplified by the variable amplifier circuit 1', the true signal component amplitude reaches the saturation level, and the noise amplitude is 2.5 V.
An amplified signal 22'-1 is obtained, but the noise cannot be removed by the peak clamp circuit 2. Next, when the set amplification factor becomes 35 dB, an amplitude signal 22'-2 with a true signal component amplitude of 1.4 V and a noise amplitude of 0.44 V is obtained.
This noise is removed by the peak clamp circuit 2, and only the true signal component is obtained as the peak clamp signal 23. Finally, the analog level of this peak clamp signal 23 is converted to a logic level by the comparison circuit 3, and a detection signal 24 is obtained.

FIG. 6 is also another timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 6 shows that the true signal component of the small amplitude input signal 21 is 5 m
In this example, the noise amplitude is 1.58 mV, the repetition frequency is f, and the set amplification factor is set from 35 dE to 50 dB.

When the set amplification factor is 35 dB, the true signal component amplitude is 0.
Amplified signal 22'- with 28V and noise amplitude of 0.089V
However, when the set amplification factor is 50 dB, an amplified signal 22'-2 with a true signal component amplitude of 1.58 V and a noise amplitude of 0.5 V can be obtained.

In this way, the set amplification factor data signal 25 is set so that the amplitude of the amplified signal is in the range of 1V to 2V, the peak clamp characteristic is always applied, noise is removed, and only the true signal component is detected. Signal.

FIG. 7 is a circuit diagram showing another embodiment of the present invention.

The embodiment shown in FIG. 7 has a configuration in which a peak hold circuit 2' is added in place of the peak clamp circuit 20 in the embodiment shown in FIG. 1, and everything else is the same as the embodiment shown in FIG. It is.

Noise is removed using a peak hold characteristic instead of a peak clamp characteristic, but the peak hold characteristic here means that by holding the peak level, a signal with a lower level than the signal with that peak level can be removed. Since the operation is the same as that shown in the time charts of FIGS. 5 and 6, the explanation of the operation will be omitted.

〔Effect of the invention〕

As explained above, the present invention has the effect of reliably removing noise by changing the set amplification factor as specified so that the output level of the amplifier circuit falls within a certain range.

In particular, when the present invention is used in a pulse detection circuit for a reproduction control signal in a VTR, noise can be removed and only the true signal component can be detected even during high-speed reproduction, that is, when the reproduction control signal is high, resulting in good tracking. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the pulse detection circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional pulse detection circuit, and FIGS. 3 and 4 are examples of the pulse detection circuit shown in FIG. 5 and 6 are timing charts for explaining the operation of the embodiment shown in FIG. 1. FIG. 7 is a timing chart for explaining the operation of the embodiment shown in FIG. FIG. 2 is a block diagram showing one embodiment of the present invention. ■...Amplification circuit, 1'...Variable amplification circuit, 2...Peak clamp circuit, 2'...
...Peak hold circuit, 3...Comparison circuit, 21...Minute amplitude input signal, 22.22'
, 22'-1, 22'=2...Amplified signal, 23
...Peak clamp signal, 23'...
・Peak hold signal, 24...detection signal,
f,...minimal amplitude input signal frequency. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] The amplifier circuit includes an amplifier circuit that can change the set amplification factor, a noise canceler circuit that removes noise from the output of the amplifier circuit, and a comparison circuit that converts the logic level of only the true signal component obtained by the amplifier circuit. The first and second inputs of the noise canceller circuit are connected to the minute amplitude input signal terminal and the set amplification factor data signal terminal, respectively, and the outputs thereof are connected to the input terminal of the noise canceller circuit, and the output of the noise canceller circuit is connected to the input terminal of the comparison circuit. , a pulse detection circuit characterized in that the output of the comparison circuit is connected to a detection signal terminal.