JPH0250362A - Data read circuit - Google Patents

Abstract

PURPOSE:To prevent the output of a noise at the tip of a signal existent part when a signal nonexistent part is switched to the signal existent part by comparing a control voltage with a prescribed slice level, and changing the slice level of a pulsing circuit. CONSTITUTION:In a data read circuit having a variable gain amplifier 1 in which a gain for an input signal is changed by the control voltage, a control voltage generating part 2 to generate the control voltage by the output of the variable gain amplifier 1, and a pulsing circuit 3 to pulse the output of the variable gain amplifier 1 with the use of a slice level and to output data, the control voltage is supervised by a comparator 4. While the control voltage is <= the slice level, since a gain G is excessive, the slice level to pulse the pulsing circuit 3 is made larger, and the output of the noise is prevented. Thus, the output of the noise at the top of the signal existent part can be prevented when the signal nonexistent part is switched to the signal existent part.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 6 and 7) Means for solving the problem to be solved by the invention (Figure 1) Working examples (a) Explanation of the configuration of one embodiment (Figures 2 and 3) (b)
Description of the operation of one embodiment (Figs. 4 and 5) (C) Description of other embodiments Effects of the invention [Summary] Regarding a data read circuit that pulses a read signal and outputs it after AGC@@ The purpose is to prevent the output of noise at the beginning of the signal section when switching from the signal section to the signal section.The purpose is to prevent noise output at the beginning of the signal section when switching from the signal section to the signal section. In a data read circuit that has a control voltage generation section that generates a control voltage from a control voltage, and a pulse generation circuit that pulses the output of a variable gain amplifier using a slice level and outputs data, the control voltage and a predetermined slice level are combined. A comparator is provided that compares the signals and changes the slice level of the pulse north circuit based on the comparison result.

[Industrial application field]

The present invention relates to a data read circuit that converts a read signal into a pulse after AGC@ control and outputs the pulsed signal.

Data read circuits are widely used to obtain pulsed data from an input analog signal, such as an optical disk read signal.

In this data read circuit, an automatic gain adjustment circuit (hereinafter referred to as an AGC circuit) is widely used in order to compensate for the level strength of the input signal and obtain a uniform level signal.

This type of AGC circuit can exhibit good AGC characteristics when a signal is present, but when a signal is not present, gain saturation occurs, and once a signal begins to exist, it cannot be tracked.
Since noise is output, countermeasures are desired.

[Conventional technology]

FIG. 6 is an explanatory diagram of the prior art, and FIG. 7 is an explanatory diagram of AGC operation.

As shown in FIG. 6(A), in the conventional data read circuit, the AGC circuit includes a variable gain amplifier 1 whose gain with respect to the human input signal changes depending on the control voltage VAGC.
and a peak detector (control voltage generation section) 2 that monitors the level of the output of the variable gain amplifier l and generates the control voltage VAGC.

When this AGC output is shaped into a pulse signal by the pulse generator 3, reproduced data for an input signal such as a read signal is obtained.

This AGC operation is performed as follows.

Figure 7 (A) is a gain characteristic diagram of the variable gain amplifier 1, where vl is the control voltage when the gain is minimum, v2 is the control voltage when the gain is in standby before AGC operation, and v3 is the saturation voltage. This is the control voltage for gain.

The standby gain is set so that any signal can be reproduced if it has this gain, and the control voltage v3 is
This is the saturation point where the gain hardly changes even if the voltage drops further.

On the other hand, the peak detector 2 monitors the output of the variable gain amplifier 1 using two slices 1 and vh.

High slice vh is a voltage that is controlled to increase control voltage VAGC, and when the peak of a certain signal pulse exceeds vh, control voltage VAGC is increased and AGC gain G is decreased.

Also, low slice ■l is a voltage that controls the control voltage VAGC to lower it, and the peak of a certain signal pulse is v
h or less and 71 or more, the control voltage VAG
Control is performed to lower C, and the AGC gain G is increased.

Furthermore, the peak of a certain signal pulse is ■! In the following cases,
The control voltage VAC;C decreases with a certain time constant and finally reaches zero, reaching the maximum gain G.

Through these controls, the gain is automatically controlled so that the peak of the input signal is equal to the high slice vh, and it is possible to respond to the strength of the input signal.

[Problem to be solved by the invention]

AGC III like this? II is extremely effective when signals are input continuously.

However, problems occur when the signal is interrupted midway.

For example, when used in a data reproducing system of an optical disk device, since the optical disk uses a random write method, data is not necessarily written continuously.

Therefore, an unrecorded portion exists between write (record) data. FIG. 7(B) shows the behavior of the control voltage VAGC when an unrecorded portion is read before and after the write data portion.

The control voltage VAGC starts at ■2, but since there is no signal at this time, it decreases with a certain time constant and starts at ■3.
As the value approaches , the amplifier gain G increases more and more.

Therefore, among the noise components, those exceeding the low slice 1 appear.

If the signal is present, the signal component exceeds the high slice vh;
The control voltage VAGC exceeds ■2, the gain G decreases, and according to the signal, the gain G is changed so that the peak of the signal is high slice vh
controlled so that

Then, in the period when there is no signal in the unrecorded area, the signal peak appears again ■! Since it is below, the control voltage VAGC decreases, and as it approaches v3, the amplifier gain G increases more and more.

And since the gain increases, ■! among the noise components!
, and the control voltage VAGC begins to fall even faster.

■When it reaches 3, the amplifier gain G is saturated, and most of the noise at that time is low slice■! ! exceeds.

Although some of the noise may exceed the high slice vh, its proportion is much smaller, so the control voltage V
AGC rapidly decreases, passing through ■3 and dropping to zero.

Therefore, as shown in Figure 6 (B), when a signal is read in a state where there is no signal and the AGC amplifier gain G is at its maximum, the AGC gain changes from the maximum at the beginning of the signal. Since it takes time to follow up, there is a problem in that the noise in the pulse generation circuit 3 exceeds the slice level during this time, and not only the recorded signal but also the noise is output.

This condition often occurs when searching for sector marks on an optical disc, resulting in deterioration of sector mark detection performance.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data read circuit that can prevent noise from being output at the beginning of a signal area when switching from a non-signal area to a signal area.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention includes a variable gain amplifier 1 whose gain for a human input signal changes depending on a control voltage;
A data lead having a control voltage generating section 2 that generates a control voltage from the output of the variable gain amplifier l, and a pulsing circuit 3 that pulses the output of the variable gain amplifier l using a slice level and outputs data. The circuit is provided with a comparator 4 that compares the control voltage with a predetermined slice level and changes the slice level of the pulsing circuit 3 based on the comparison result.

[Effect]

In the present invention, the control voltage is monitored by the comparator 4, and when the control voltage is small below the slice level, the gain G is excessive. This is to prevent it from being output.

This allows the AG to move from the state where the gain is maximum.
Until C follows up, noise output can be prevented and errors can be reduced.

〔Example〕

(a) Description of the configuration of one embodiment FIGS. 2 and 3 are circuit diagrams of an embodiment of the present invention.

In the figure, the same parts as shown in Figures 1 and 6 are:
They are indicated by the same symbols, 4a is an inverting circuit that inverts the output of comparator 4 and outputs the gate signal GT, 6 is a differentiation circuit that differentiates the input read signal, and 7 is a low-pass filter. A parallel circuit of a coil L and a capacitor C is formed, and the high frequency component of the output of the variable gain amplifier l is cut and output to the peak detector 2.

In addition, rl and r2 are voltage dividing resistors that provide the slice level (voltage) Vs to the comparator 4, "a" is an input resistor that is used to input the control voltage VAGC to the comparator 4, and r4 is the one that provides the comparator 4 with a slice level (voltage) Vs. This is a gain adjustment resistor.

FIG. 3 shows details of the pulsing circuit 3, 30 is a pulse shaper (pulse shaping circuit), and 2-phase AGC output A
GCO1*AGCO pulse shaped and output, 3
1 is a slice bias applying circuit, and a gate signal GT
When the gate signal GT is "low", the potential difference between the resistors rs is made large, and the potential difference between the resistors rG is made small, and the potential difference between the resistors rG and the gate signal GT is "high". This is given to the input of the comparator.

32 is the first comparator, and the second AGC output *
33 is a second comparator that slices the first AGC output AGC0 as a slice level for the first AGC output AGCO.
This is to slice using the GC output *AGCO as the slice level.

34 is a flip-flop, and the first comparator 3
2 and reset by the output of the second comparator 33 to create the data window wd;
35 is an AND gate that opens in the data window wd and outputs the pulse output of the pulse shaper 30;
6 is a monostable circuit which converts the output of the AND gate 35 into read data RD DATA of a constant width,
This is what is output.

(C) Description of operation of one embodiment FIG. 4 is a waveform diagram of essential parts of an embodiment of the present invention, and FIG. 5 is an explanatory diagram of operation of an embodiment of the present invention.

The RF signal (read signal) RDS read by the optical head from the optical disk is input to the differentiation circuit 6 and differentiated, and the differential signal RDS' becomes as shown in FIG.

The differential read signal RDS' is inputted to the variable gain amplifier l, given a desired gain G, passed through the low-pass filter 7, inputted to the peak detector 2, and outputted from the AGC output AGC.
O(*AGCO) and input to the pulse generator 3.

The peak detector 2 detects the peak of the output signal of the variable gain amplifier 1, compares it with the two slice levels vz and vh as described above, and outputs the control voltage VAGC to the variable gain amplifier 1.

Therefore, during standby, the control voltage VAGC decreases from the voltage V2 and increases the gain G, and when a signal is input, it rapidly increases and decreases the gain G.

Thereafter, AGC'lHH is performed so that the AGC output AGCO becomes vh according to the input signal, and when the signal disappears, the control voltage VAGC rapidly decreases in order to increase the gain G.
It approaches zero and exhibits the behavior shown in Figure 4.

Therefore, as in the AGC output AGCO in FIG. 4, when a no-signal period changes to a signal period, the signal is amplified to a large amplitude at a large gain until the AGC follows up at the beginning of the signal period.

That is, at the beginning of the signal period, the noise component also has a large amplitude until the AGC follows and the control voltage VAGC exceeds 3.

On the other hand, the comparator 4 compares the control voltage VAGC of the peak detector 2 with the slice level v3 created by the voltage dividing resistors r1 and r2.

This slice level v3 is the control voltage v at the saturation point mentioned above.
It is set to the same value as 3.

Comparator 4 indicates “noh” V if VAGC≦v3.
If AGC≧■3, a “low” output is generated.

Therefore, when the control voltage VA(1;C becomes less than the saturation voltage 3), a "high" output is generated, which is inverted by the inverting circuit 4a and becomes the gate signal GT.

As shown in FIG. 4, this gate signal GT is a "high" signal when the control voltage VAGC exceeds the saturation potential v3, and is a "low" signal when it is below V3, and is a signal during the low gain period of the signal period and the no signal period. Identifying the saturation gain period.

In the slice bias applying circuit 31, when the gate signal GT is "low", the potential difference between a and b between the resistors re becomes large.

Therefore, as shown in FIG. 5(C), the comparator 32
The bias potential between input AGCO*AGCO is set to be large as vbh.

On the other hand, when the gate signals C and T are "high", the resistance rG
The potential difference between a and b becomes small.

Therefore, as shown in FIG. 5(B), the bias potential between the inputs AGCO1IAGCO of the comparator 32 is set to be low as vb2.

This means that the slice level AGCO in the comparator 32 is changed.

The comparator 33 has a reverse phase input, but operates in a similar manner, and the slice level *AGCδ changes.

In the comparator 32, as shown in FIG. 5(A), the AGC
AGC output *AG with output AGCO as slice level
The CO is sliced and the output is input to the set terminal of the flip-flop 34.

On the other hand, in the comparator 33, as shown in FIG. 5(A),
Slice the AGC output AGCO using the AGC output *AGCO as the slice level, and send the output to the flip-flop 34.
input to the reset terminal.

The flip-flop 34 is set at the rising edge of the output of the comparator 32 and reset at the rising edge of the output of the comparator 33, thereby creating a data window Wd.

The AND gate 35 opens in the data window wd and outputs the pulse output of the pulse shaper 30 to the monostable circuit 36.
Output to.

Therefore, as shown in FIG. 4, when the control voltage VAGC becomes 3 or less during the no-signal period, the gate signal GT becomes "low", the slice bias becomes high vbh, and the slice level rises.

Therefore, as shown in FIG. 5(C), even if the noise is amplified, it will not be applied to the slice, and no data window wd will occur in the noise portion.

As a result, even if the noise is greatly amplified, the output of the noise is cut.

This operation is also performed during the AGC tracking period at the beginning of the signal period when the control voltage VAGC exceeds ■3, so even if the noise level becomes large at the beginning of the signal period, no noise component will be output. do not have.

When the AGC follows, the gate signal GT becomes "high" level, the slice bias becomes low vb2, the slice level is lowered, and slicing according to the AGC gain G is performed.

Furthermore, in this embodiment, during the no-signal period that follows the signal period, the control voltage VAGC becomes small as shown in FIG.
The GC gain G becomes large and the noise level becomes large, but at this time as well, the gate signal GT becomes "low" level,
Since the slice bias is set high, noise is similarly cut.

In this way, when the control voltage VAGC becomes small and the gain G becomes large, the slice bias is set high to create a window signal that cuts the noise component, thereby preventing the output of the noise component.

As a result, when a signal is input with the AGC gain at its maximum, noise output can be prevented until the AGC follows up, and errors can be reduced.

(C) Description of other embodiments In the embodiments described above, the slice level for creating a data window signal is manipulated by the gate signal GT, but the slice level for creating other pulses is manipulated by the gate GT. You may also do so.

Furthermore, although the read signal of an optical disk device is used as the target, other read signals or other well-known input signals may be used.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, A
It has the effect of preventing the output of noise until the AGC gain follows up when a signal is input with the maximum GC gain, and contributes to improving the reproduction performance of read signals that have a no-signal part and a signal part. do.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Figs. 2 and 3 are circuit diagrams of an embodiment of the invention, Fig. 4 is a waveform diagram of essential parts of an embodiment of the invention, and Fig. 5 is an embodiment of the invention. FIG. 6 is a diagram explaining the operation of the embodiment, FIG. 6 is a diagram explaining the conventional technique, and FIG. 7 is a diagram explaining the AGC operation. In the figure, 1.--variable gain amplifier, 2.--peak detector), 3.--pulsing circuit, 4.-- comparator. (Control voltage generator

Claims (1)

[Claims] (1) A variable gain amplifier (1) whose gain relative to an input signal changes depending on a control voltage; a control voltage generator (2) that generates a control voltage from the output of the variable gain amplifier (1); and a control voltage generator (2) that generates a control voltage from the output of the variable gain amplifier (1). A pulsing circuit (3) that pulses the output of 1) using a slice level and outputs data.
), further comprising a comparator (4) that compares the control voltage with a predetermined slice level and changes the slice level of the pulsing circuit (3) based on the comparison result. Data read circuit.