JPH0272658A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0272658A JPH0272658A JP22522588A JP22522588A JPH0272658A JP H0272658 A JPH0272658 A JP H0272658A JP 22522588 A JP22522588 A JP 22522588A JP 22522588 A JP22522588 A JP 22522588A JP H0272658 A JPH0272658 A JP H0272658A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- amorphous silicon
- impurities
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、積層容量素子の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a multilayer capacitive element.
（従来の技術）
高濃度不純物を含んだ低抵抗ポリシリコンを下地電極と
しその表面上に絶縁膜を形成しさらに上部電極を形成し
た素子は、容量素子として半導体装置において広い範囲
で使用されている。最近では、高集積化のため素子寸法
の微紺化が進んでいる。この様な情勢の中で十分な容量
を確保する為絶縁膜の薄膜化が強く要求されている。従
来ポリシリコン上の絶縁膜の形成方法は、不純物を含む
ポリシリコンを直接熱酸化や熱窒化することによって形
成してきた。しかし、この方法で形成した絶縁膜中は不
純物が残ってしまい耐圧及び絶縁破壊の寿命特性も劣化
させてしまうという欠点があった。ジャーナルオブエレ
クトローケミカルソサイエティー：ソリッドステートサ
イエンスアンドテクノロジー（Ｊｏｕｒｎａｌ Ｅｌｅ
ｃｔｒｏｃｈｅｍ、 Ｓｏｃ、 ： ５ｏｌｉｄ−８ｔ
ａｔｅ ５ｃｉｅｎｃｅ ａｎｄ Ｔｅｃｈｎｏｌｏｇ
ｙ）１９８３ 年７ 月 、１５９７〜１６０３頁に
ランプブレークダウンスタディオブダブルポリシリコン
ラムズアズアファンクションオブフアプリケイションパ
ラメーターズ（Ｒａｍｐ Ｂｒｅａｋｄｏｗｎ ５ｔｕ
ｄｙ ｏｆ Ｄｏｕｂｌｅ ＰｏｌｙｓｉｌｉｃｏｎＲ
ＡＭ’ｓ ａｓ ａ Ｆｕｎｃｔｉｏｎ ｏｆ Ｆａｂ
ｒｉｃａｔｉｏｎ Ｐａｒａｍｅｔｅｒｓ）と題して発
表された論文において示されているように、下地ポリシ
リコン中に含まれるリンの濃度が多くなるに従い絶縁膜
中に不純物が取り込まれ耐圧が劣化するという欠点があ
る。(Prior art) Elements in which low-resistance polysilicon containing high concentration impurities is used as a base electrode, an insulating film is formed on the surface of the base electrode, and an upper electrode is further formed are widely used as capacitive elements in semiconductor devices. . Recently, element dimensions have become increasingly finer due to higher integration. Under these circumstances, there is a strong demand for thinner insulating films to ensure sufficient capacity. Conventionally, insulating films on polysilicon have been formed by directly thermally oxidizing or thermally nitriding polysilicon containing impurities. However, there is a drawback that impurities remain in the insulating film formed by this method, which deteriorates the breakdown voltage and the life characteristics of dielectric breakdown. Journal of Electrochemical Society: Solid State Science and Technology
ctrochem, Soc, : 5olid-8t
ate 5science and technology
y) Ramp Breakdown Study of Double Polysilicon Rams as a Function of Application Parameters, July 1983, pp. 1597-1603.
dy of Double PolysiliconR
AM's as a Function of Fab
As shown in a paper published under the title ``Reduction Parameters'', there is a drawback that as the concentration of phosphorus contained in the underlying polysilicon increases, impurities are incorporated into the insulating film and the breakdown voltage deteriorates.
（発明が解決しようとする課題）
絶縁膜中の不純物濃度を減らす試みとして昭和６３年春
季応用物理学会予稿集３１ａ−Ｖ−８で”ｉｎ ５ｉｔ
ｕリンドープ／アンドープ多結晶Ｓｉ膜連続形成による
高アスペクト比溝の埋め込み″と題して発表された報告
では第２図に示すごとく不純物を含むポリシリコン下部
電極上（３）に導電型不純物を含まないポリシリコン（
４）を堆積し、そのポリシリコンを酸化して容量絶縁膜
（５）を形成することによって不純物の少ない絶縁膜の
形成が示されている。しかしながら、この方法で形成し
た絶縁膜は、ポリシリコンのグレインによる影響特にポ
リシリ表面の凸凹の影響を受は耐圧分布がブロードにな
る等信頼性のあるものが得られないという問題点がある
。(Problem to be solved by the invention) In an attempt to reduce the impurity concentration in an insulating film, "in 5it" was published in 1985 Spring Proceedings of the Japan Society of Applied Physics 31a-V-8.
In a report titled ``Filling of high aspect ratio grooves by continuous formation of u-phosphorous doped/undoped polycrystalline Si films'', as shown in Figure 2, the polysilicon lower electrode (3) containing impurities does not contain conductive type impurities. Polysilicon (
4) and oxidizes the polysilicon to form a capacitor insulating film (5), thereby forming an insulating film with less impurities. However, the insulating film formed by this method has problems such as a broad breakdown voltage distribution due to the effects of the grains of polysilicon, especially the unevenness of the surface of the polysilicon, making it difficult to obtain a reliable film.
本発明の目的は、従来の問題点を除去し信頼性の高い薄
い絶縁膜を有する容量素子を形成する方法を提供するこ
とである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a highly reliable capacitive element having a thin insulating film by eliminating the conventional problems.
（課題を解決するための手段）
本発明は、高濃度不純物を含んだ低抵抗ポリシリコンを
形成後該低抵抗ポリシリコン上に不純物濃度の低いもし
くは不純物を含まない薄いアモルファスシリコンヲ堆積
し、次に前記の薄いアモルファスシリコンを熱酸化ある
いは熱窒化して少なくとも第一層目の絶縁膜として形成
した一層あるいは多層容量膜を形成し、その後熱処理を
行い前記低抵抗ポリシリコン中の不純物を前記薄いアモ
ルファスシリコン中に拡散し、その後上部電極を形成す
る積層容量素子の製造方法である。(Means for Solving the Problems) The present invention involves forming low resistance polysilicon containing high concentration impurities, depositing thin amorphous silicon with low impurity concentration or no impurities on the low resistance polysilicon, and then depositing thin amorphous silicon with low impurity concentration or no impurities. The thin amorphous silicon is thermally oxidized or thermally nitrided to form a single-layer or multilayer capacitive film as at least the first layer of insulating film, and then heat-treated to remove impurities in the low-resistance polysilicon from the thin amorphous silicon. This is a method of manufacturing a multilayer capacitor element in which the element is diffused into silicon and then an upper electrode is formed.
（作用）
不純物濃度が高いシリコンを熱酸化や熱窒化して形成し
た膜ではその不純物等の膜中への取込みによる影響を受
は本来の膜の持つ絶縁性を悪化させることがある。本発
明の方法では、不純物を含まないあるいは不純物の濃度
の低いシリコン層を酸化あるいは窒化することで信頼性
の高い容量絶縁膜を得ることが可能である。また本発明
においてはこのシリコン層としてアモルファスシリコン
層を用いているために酸化あるいは窒化するシリコン層
にグレインがない。このために熱酸化あるいは熱窒化す
るときにポリシリコンのような面方位依存性や膜の凸凹
は少なく、均一な絶縁膜が形成できる。(Function) A film formed by thermal oxidation or thermal nitridation of silicon with a high impurity concentration may be affected by the incorporation of impurities into the film, which may deteriorate the original insulation properties of the film. According to the method of the present invention, a highly reliable capacitor insulating film can be obtained by oxidizing or nitriding a silicon layer that does not contain impurities or has a low impurity concentration. Further, in the present invention, since an amorphous silicon layer is used as the silicon layer, there are no grains in the silicon layer to be oxidized or nitrided. For this reason, when thermal oxidation or thermal nitridation is performed, a uniform insulating film can be formed without surface orientation dependence or film irregularities unlike polysilicon.
（実施例） 以下本発明の実施例について図面を用いて説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図の（ａ）〜（ｄ）において本発明の一実施例の容
量絶縁膜の形成方法を順次断面図で示す。1A to 1D, a method for forming a capacitor insulating film according to an embodiment of the present invention is shown in sequential cross-sectional views.
まず第１図（ａ）に示すように、トレンチを形成したシ
リコン基板（１）にシリコン酸化膜（２）を形成、その
シリコン酸化膜上にポリシリコン（３）を堆積しリンま
たはヒ素、ポロン等の高濃度熱拡散を行う。ボッシリコ
ン（３）を低抵抗にするためここでは不純物の熱拡散を
行っているが低抵抗ポリシリコンを得る方法としては、
この他にイオン注入法やリン、ヒ素ポロン等のドープト
ポリシリコンの堆積がある。First, as shown in FIG. 1(a), a silicon oxide film (2) is formed on a silicon substrate (1) on which a trench is formed, and polysilicon (3) is deposited on the silicon oxide film. Perform high-concentration heat diffusion such as In order to make polysilicon (3) low in resistance, thermal diffusion of impurities is performed here, but as a method to obtain low resistance polysilicon,
Other methods include ion implantation and deposition of polysilicon doped with phosphorus, arsenic, or the like.
次に第１図（ｂ）に示すように不純物を含まないアモル
ファスシリコン層（４）をポリシリコン層の上に堆積す
る。Next, as shown in FIG. 1(b), an amorphous silicon layer (4) containing no impurities is deposited on the polysilicon layer.
次に第１図（Ｃ）に示すようにアモルファスシリコン層
（４）を熱酸化し容量絶縁膜（５）を形成する。この絶
縁膜形成の作業が終わった後に（４）の層の酸化されて
いない部分にアニールによりポリシリコン層（３）から
不純物を拡散して抵抗を低くし電極として用いる。この
時にアモルファスシリコン層（４）は、結晶成長しポリ
シリコンとなる。Next, as shown in FIG. 1C, the amorphous silicon layer (4) is thermally oxidized to form a capacitor insulating film (5). After this insulating film formation work is completed, impurities are diffused from the polysilicon layer (3) by annealing into the unoxidized portion of the layer (4) to lower the resistance and use it as an electrode. At this time, the amorphous silicon layer (4) undergoes crystal growth and becomes polysilicon.
次に第１図（ｄ）に示すように容量絶縁膜（５）の上に
上層の電極となるポリシリコンロを堆積しリンまたはヒ
素、ボロンを拡散して上部電極を形成する。Next, as shown in FIG. 1(d), a polysilicon film which will become an upper layer electrode is deposited on the capacitor insulating film (5), and phosphorus, arsenic, or boron is diffused to form an upper electrode.
ただし、前記のリン押し込みは、上層のポリシリコン（
第１図（ｄ）の（６））を形成した後に行ってもよい。However, the above-mentioned phosphorus intrusion
This may be performed after forming (6) in FIG. 1(d).
この実施例では容量絶縁膜として熱酸化膜を用いたが、
第３図（ａ）のようにその上にＣＶＤ窒化膜（３３）を
形成した多層容量膜でもよいし、さらに（ｂ）図のよう
にＣＶＤ窒化膜（３３）の表面を酸化（３４）してもよ
い。また（Ｃ）図に示すようにノンドープアモルファス
シリコン（４）を熱窒化し熱窒化膜（３５）を形成して
もよいし、（ｄ）図に示すように熱酸化膜表面を窒化（
３６Ｌでもよい。In this example, a thermal oxide film was used as the capacitive insulating film, but
It may be a multilayer capacitive film with a CVD nitride film (33) formed thereon as shown in Fig. 3(a), or the surface of the CVD nitride film (33) may be oxidized (34) as shown in Fig. 3(b). It's okay. Alternatively, as shown in figure (C), the non-doped amorphous silicon (4) may be thermally nitrided to form a thermal nitride film (35), or the surface of the thermal oxide film may be nitrided (35) as shown in figure (d).
36L may be sufficient.
第１図（ａ）〜（ｄ）は、本発明の一実施例の製造方法
を説明するための工程順に示した半導体チップの模式的
断面図である。
第２図は、従来例を説明した半導体チップの模式的断面
図である。
第３図（ａ）〜（ｄ）は、種々の容量絶縁膜構造を示し
た模式的断面図である。
１・・・シリコン基板
２・・・酸化シリコン膜
３・・・リンまたは、ヒ素、ボロンが拡散されているポ
リシリコン
４・・ノンドープアモルファスシリコン４′・・・リン
または、ヒ素、ポロンがポリシリコンから拡散された層
５・・・酸化シリコン膜
６・・・上層ポリシリコン
３２・・・熱酸化膜
３３・・・ＣＶＤ窒化膜
３４ 、 、 、窒化膜を酸化した膜
３５・・、熱窒化膜
３６・９．熱酸化膜を窒化した膜FIGS. 1A to 1D are schematic cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor chip illustrating a conventional example. FIGS. 3(a) to 3(d) are schematic cross-sectional views showing various capacitor insulating film structures. 1...Silicon substrate 2...Silicon oxide film 3...Polysilicon in which phosphorus, arsenic, or boron is diffused 4...Non-doped amorphous silicon 4'...Polysilicon in which phosphorus, arsenic, or boron is diffused Layer 5 diffused from... Silicon oxide film 6... Upper layer polysilicon 32... Thermal oxide film 33... CVD nitride film 34, , , Film 35 obtained by oxidizing the nitride film..., Thermal nitride film 36.9. A film made by nitriding a thermal oxide film
Claims (1)
部電極となる低抵抗ポリシリコンを形成後この低抵抗ポ
リシリコン上に不純物濃度の低いもしくは不純物を含ま
ない薄いアモルファスシリコンを堆積し、次に前記の薄
いアモルファスシリコンを熱酸化あるいは熱窒化して少
なくとも第一層目の絶縁膜として形成した一層あるいは
多層容量膜を形成し、その後熱処理を行い前記低抵抗ポ
リシリコン中の不純物を前記薄いアモルファスシリコン
中に拡散し、その後上部電極を形成することを特徴とす
る半導体素子の製造方法。(1) In a multilayer capacitive element, after forming low-resistance polysilicon that will serve as the lower electrode containing high-concentration impurities, deposit thin amorphous silicon with a low impurity concentration or no impurities on this low-resistance polysilicon, and then The thin amorphous silicon is thermally oxidized or thermally nitrided to form a single-layer or multilayer capacitive film as at least a first layer of insulating film, and then heat-treated to remove impurities in the low-resistance polysilicon from the thin amorphous silicon. 1. A method for manufacturing a semiconductor device, comprising diffusing into the interior of the semiconductor device and then forming an upper electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63225225A JP2826324B2 (en) | 1988-09-07 | 1988-09-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63225225A JP2826324B2 (en) | 1988-09-07 | 1988-09-07 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0272658A true JPH0272658A (en) | 1990-03-12 |
| JP2826324B2 JP2826324B2 (en) | 1998-11-18 |
Family
ID=16825948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63225225A Expired - Lifetime JP2826324B2 (en) | 1988-09-07 | 1988-09-07 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2826324B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5587614A (en) * | 1995-03-01 | 1996-12-24 | Texas Instruments Incorporated | Microplanarization of rough electrodes by thin amorphous layers |
| US5913125A (en) * | 1992-06-26 | 1999-06-15 | International Business Machines Corporation | Method of controlling stress in a film |
| US6328794B1 (en) | 1993-06-26 | 2001-12-11 | International Business Machines Corporation | Method of controlling stress in a film |
| KR100560583B1 (en) * | 1997-07-14 | 2006-03-14 | 마이크론 테크놀로지, 인크. | Hemispherical grained polysilicon semicondonductor capacitor structure and method |
| US8987145B2 (en) | 2011-03-04 | 2015-03-24 | Asahi Kasei Microdevices Corporation | Semiconductor device, manufacturing method of the semiconductor device |
| FR3099964A1 (en) * | 2019-08-14 | 2021-02-19 | Stmicroelectronics (Crolles 2) Sas | Method of making an electrode in a base substrate and electronic device |
| CN114400261A (en) * | 2021-12-27 | 2022-04-26 | 理想晶延半导体设备(上海)股份有限公司 | Battery back structure, preparation method thereof and battery |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61295644A (en) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62130550A (en) * | 1985-12-02 | 1987-06-12 | Hitachi Ltd | Manufacture of mis type capacitor |
-
1988
- 1988-09-07 JP JP63225225A patent/JP2826324B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61295644A (en) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62130550A (en) * | 1985-12-02 | 1987-06-12 | Hitachi Ltd | Manufacture of mis type capacitor |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5913125A (en) * | 1992-06-26 | 1999-06-15 | International Business Machines Corporation | Method of controlling stress in a film |
| US6328794B1 (en) | 1993-06-26 | 2001-12-11 | International Business Machines Corporation | Method of controlling stress in a film |
| US5587614A (en) * | 1995-03-01 | 1996-12-24 | Texas Instruments Incorporated | Microplanarization of rough electrodes by thin amorphous layers |
| KR100560583B1 (en) * | 1997-07-14 | 2006-03-14 | 마이크론 테크놀로지, 인크. | Hemispherical grained polysilicon semicondonductor capacitor structure and method |
| US8987145B2 (en) | 2011-03-04 | 2015-03-24 | Asahi Kasei Microdevices Corporation | Semiconductor device, manufacturing method of the semiconductor device |
| FR3099964A1 (en) * | 2019-08-14 | 2021-02-19 | Stmicroelectronics (Crolles 2) Sas | Method of making an electrode in a base substrate and electronic device |
| US11251053B2 (en) | 2019-08-14 | 2022-02-15 | STMicroelectronics (Grolles 2) SAS | Process for producing an electrode in a base substrate and electronic device |
| CN114400261A (en) * | 2021-12-27 | 2022-04-26 | 理想晶延半导体设备(上海)股份有限公司 | Battery back structure, preparation method thereof and battery |
| CN114400261B (en) * | 2021-12-27 | 2023-09-15 | 理想晶延半导体设备(上海)股份有限公司 | Battery back structure, preparation method thereof and battery |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2826324B2 (en) | 1998-11-18 |
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