KR100250750B1 - Method for fabricating a capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to secure enough capacitance by increasing the density of dopant of a charge storage electrode and a plate electrode. CONSTITUTION: An interlayer dielectric(2) is formed on an upper portion of a silicon substrate(1). A contact hole is formed by etching a selected region of the silicon substrate(1). An undoped polysilicon layer(3) and an oxide layer(4) are formed sequentially on an upper portion of the whole structure. The first high density doped polysilicon layer(5) is formed on the upper portion of the whole structure. The first high-density doped polysilicon layer(5), the oxide layer(4), and the undoped polysilicon layer(3) are removed partially and patterned. A hemispherical polysilicon thin film(6) is formed on the patterned undoped polysilicon layer(3), the oxide layer(4), and the first high density doped polysilicon layer(5). An insulating layer(7) is formed on the upper portion of the whole structure. The second high density doped polysilicon layer(8) is formed thereon.

Description

Capacitor Manufacturing Method of Semiconductor Device

The present invention relates to a method for manufacturing a semiconductor device, and in particular, to increase the dopant concentration of the storage node electrode and the plate electrode to increase the capacitance (capacitance) and the capacitance change rate (ΔC) It relates to a method for manufacturing a capacitor of a semiconductor device capable of reducing).

In general, as the degree of integration of semiconductor devices increases, the cell area also decreases. However, to keep the device's characteristics constant, a certain amount of capacitance must be maintained even though the cell area of the design is small. Therefore, in order to increase the surface area of the charge storage electrode in the device of 16M DRAM class or more, a structure in which a nitride oxide oxide layer (NO multi layer) is used in the three-dimensional charge storage electrode structure is used. However, these three-dimensional structure diagrams are difficult to secure a capacitance amount of a predetermined amount or more in a device of 256M DRAM class or more. Therefore, some have developed thin film materials having high dielectric properties such as Ta ₂ O ₅ , BST, but these materials also have many problems to be applied to devices such as DRAM. As described above, a method of reducing the thickness of a dielectric, applying a dielectric having a high dielectric constant, or increasing the area of a storage node has been developed in the conventional charge storage electrode fabrication to increase capacitance. In addition, in the case of the NO capacitor, carrier depletion occurs in the electrode when the doping concentration of the electrode is low, thereby increasing the capacitance change rate, which may cause a problem in the operation of the device.

Accordingly, the present invention provides a method of manufacturing a capacitor of a semiconductor device capable of securing sufficient capacitance by increasing the dopant concentration of the charge storage electrode and the plate electrode, which are the upper and lower electrodes of the capacitor, to obtain a sufficient amount of charge in a small area. Its purpose is to.

The present invention for achieving the above object is to form an interlayer insulating film on the silicon substrate and to form a contact hole by etching the selected region of the interlayer insulating film, and the undoped polysilicon film and oxide film on the entire structure sequentially Forming a first high concentration doped polysilicon film over the entire structure to fill the contact hole; and removing selected regions of the first high concentration doped polysilicon film, an oxide film, and an undoped polysilicon film. Patterning, forming a semi-spherical polycrystalline silicon thin film on the side surfaces and top surfaces of the patterned undoped polysilicon film, the oxide film, and the first high concentration doped polysilicon film, and forming an insulating film on the entire structure, followed by a second It is characterized by consisting of forming a high concentration doped polysilicon film.

1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method for manufacturing a capacitor of a semiconductor device according to the present invention.

2 is a graph comparing the capacitance of a capacitor manufactured by the method of the present invention with a conventional base line.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 interlayer insulating film

3: undoped polysilicon film 4: oxide film

5: first high concentration doped polysilicon film

6: hemispherical polycrystalline silicon thin film

7: NO multilayer insulating film

8: first high concentration doped polysilicon film

The present invention will be described in detail with reference to the accompanying drawings.

1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a charge storage electrode of a semiconductor device according to the present invention.

As shown in FIG. 1A, an interlayer insulating film 2 is formed on the silicon substrate 1. Selected regions of the interlayer insulating film 2 are etched to expose the silicon substrate 1 to form contact holes. An undoped polysilicon film 3 is formed in a uniform thickness on the entire structure, and an oxide film 4 is formed in a thickness of 5 to 15 Å on the upper portion. A first high concentration doped polysilicon film 5 to be used as a charge storage electrode is formed on the entire structure so that the contact hole is buried. Herein, the undoped polysilicon film 3 and the oxide film 4 may be formed of silicon substrates having a dopant in the first heavily doped polysilicon film 5 that is excessively doped when the first heavily doped polysilicon film 5 is deposited. As it diffuses into 1), it is formed to prevent a phenomenon that the channel of the transistor is shortened or device characteristics such as an increase in leakage current are lowered. In addition, the undoped polysilicon film 3 and the first high concentration doped polysilicon film 5 are formed to have a constant ratio of thickness. Here, the undoped polysilicon film 3 which prevents dopant diffusion is doped at a concentration of 1E17 atoms / cm 3 to 1E19 atoms / cm 3 using a gas containing silicon such as SiH ₄ or Si ₂ H ₆ gas. The oxide film 4 to be used as the diffusion barrier is grown in a native oxide film by exposure to air or by using an O ₂ gas using N ₂ O or N ₂ as a carrier gas. In order to form the first high concentration doped polysilicon film 5, a gas containing silicon such as SiH ₄ Si ₂ H ₆ gas or the like is used, and to dope the first high concentration doped polysilicon film 5 with impurities. Doping is performed at a concentration of 3E20 atoms / cm 3 to 9E21 atoms / cm 3 using a gas containing phosphorus (P) or arsenic (As) such as PH ₃ . Here, the method of doping the first high concentration doped polysilicon (5), in addition to the method of depositing in-situ doped polysilicon, doping by thermal diffusion using POCl ₃ to the undoped polysilicon, and implantation (implantation) ) Method.

FIG. 1 (b) shows that the charge storage electrode is formed by removing the selected regions of the first high concentration doped polysilicon film 5, the oxide film 4 and the undoped polysilicon film 3 by performing a mask and etching process. It is a cross section.

Fig. 1 (c) is a cross-sectional view of a hemispherical polycrystalline silicon thin film 6 having a predetermined thickness on the entire structure.

FIG. 1D is a cross-sectional view of the hemispherical polycrystalline silicon thin film 6 formed on the exposed interlayer insulating film 2.

FIG. 1 (e) is a cross-sectional view of a capacitor structure formed by forming a second high concentration doped polysilicon film 8 serving as a plate electrode after forming an insulating film 7 using a NO multilayer structure on the entire structure. The second high concentration doped polysilicon film 8 is deposited under the same conditions as the deposition conditions of the first high concentration doped polysilicon film 5. That is, it is formed using a gas containing silicon such as SiH ₄ or Si ₂ H ₆ , and the concentration of 3E20 atoms / cm 3 to 9E21 atoms / cm 3 using a gas containing phosphorus or arsenic such as PH ₃ to inject impurities Doping with The method of doping the second high concentration doped polysilicon film 8 is also the same as the method of doping the first high concentration doped polysilicon film 5.

The following table shows the capacitance value and the capacitance change rate (ΔC) which are significantly improved than the baseline when the dopant concentration of the dopant polysilicon used as the charge storage electrode and the plate electrode is significantly increased according to the method proposed in the present invention. 2 illustrates this graphically. At this time, the capacitance change rate is calculated as follows.

[expression]

[table]

The table and the graph shown in Figure 2 is 200 × 200 ㎛²of It was measured on the planar pattern of the polycrystalline silicon thin film.

As described above, according to the present invention, not only a sufficient capacitance can be secured within a narrow cell area, but also ΔC can be reduced, thereby greatly contributing to the improvement of device characteristics and the yield. In addition, the diffusion of the charge storage electrode due to excessive dopants can be prevented, thereby reducing the refresh characteristics.

Claims (5)

Forming a contact hole by forming an interlayer insulating film over the silicon substrate and etching selected regions of the interlayer insulating film, sequentially forming an undoped polysilicon film and an oxide film over the entire structure, and filling the contact hole Forming a first high concentration doped polysilicon film over the entire structure, removing and patterning selected regions of the first high concentration doped polysilicon film, an oxide film, and an undoped polysilicon film, and patterning the undoped pattern Forming a semi-spherical polycrystalline silicon thin film on the side and top surfaces of the polysilicon film, the oxide film, and the first high concentration doped polysilicon film, forming an insulating film on the entire structure, and then forming a second high concentration doped polysilicon film. A capacitor manufacturing method of a semiconductor device, characterized in that made. The method of claim 1, wherein the oxide film is exposed to air and grown as a natural oxide film, or grown using O ₂ gas using N ₂ O or N ₂ as a carrier gas to form a thickness of 5 ~ 15Å A method for producing a capacitor of a semiconductor device. The method of claim 1, wherein the first high concentration doped polysilicon film is doped at a concentration of 3E20 to 9E21 atoms / cm 3 using a gas containing phosphorus or arsenic. The method of claim 1, wherein the second high concentration doped polysilicon film is doped at a concentration of 3E20 to 9E21 atoms / cm 3 using a gas containing phosphorus or arsenic. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein a light-doped polysilicon film doped at a concentration of 1E17 to 1E19 atoms / cm 3 is used in place of the undoped polysilicon film.

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