JPH0271674A - Video signal clamping circuit - Google Patents

Abstract

PURPOSE:To attain stable clamping independently of the presence of an input signal by discriminating the presence of the television signal to control the clamping level. CONSTITUTION:A composite video signal 101 is separated by a synchronizing separator circuit 115 synchronizingly and a synchronizing separation output signal 116 is extracted. The signal 116 is given to a clamp timing pulse generating circuit 117 to generate a clamp pulse 118 such as a blanking signal, which is inputted to an OR circuit 120. On the other hand, a color killer detection signal from a chroma signal processing circuit 103 is inputted to the OR circuit 120. When a signal 101 is inputted, an SW signal 121 being an output signal of the circuit 120 operates a clamp level control circuit 113 in the timing of the clamp pulse 118. Since a color killer detection signal is inputted to the circuit 120 in the case of no signal, the signal 121 operates the circuit 113 in a full video period. Thus, stable clamping is applied independently of the presence of the input signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to A/D conversion of television signals,
This invention relates to a signal clamping method before A/D conversion processing.

[Conventional technology]

In a digital television system, television signals (hereinafter abbreviated as television signals) such as a composite video signal, a luminance signal, one color difference signal, etc.
When performing D conversion, it is necessary to accurately set the clamp level before A/D conversion processing.

For example, in digital signal processing after A/D conversion,
When performing processing such as changing the black level (blanking period) of a television signal, if the clamp level before A/D conversion is not set to match the black level to be replaced by digital signal processing, the A/D A clamp level error occurs between the television signal before D conversion processing and the D/A conversion converter revision signal, and there is a possibility that the black level and white balance change. Further, when there is no signal, an offset occurs between the black level and the video signal even though there is no signal, and the screen may become brighter or colored.

An example of a conventional device that solved this problem is Jikai No. 58-124373.

In this device, a clamp circuit is placed before the A/D converter, and the clamp level is controlled in accordance with the output signal level of the A/D converter.

[Problem to be solved by the invention]

When using the above conventional technology in a digital television system, when a television signal is input, a pulse synchronized with a synchronization signal separated from this can be used as a clamp pulse to operate a clamp circuit before A/D conversion processing. Although it is possible.

No consideration is given to the state when there is no signal, and when there is no signal, the above-mentioned clamp pulse is missing and the clamp operation stops, so in the unclamped state, the A/D
The level of the signal input to the converter exceeds the dynamic range of the A/D converter. For this reason, even though it is a D/A conversion converter signal, it becomes a signal with an offset to the black level set by digital signal processing, so there is a problem that subsequent signal processing is not performed correctly.

An object of the present invention is to provide a lamp circuit in which the clamp level can match the black level set by digital signal processing even when there is no signal.

[Means to solve the problem]

The above purpose is to provide an A/D converter that converts a television signal into a digital signal, and a clamp circuit that matches the black level set by digital signal processing with the clamp level before A/D conversion processing.

A clamp timing pulse generation circuit that obtains a clamp pulse from a synchronization signal in order to operate the clamp circuit, and a clamp timing pulse generation circuit that controls the timing pulse generation circuit.
A clamp level of the clamp circuit is controlled by comprising a circuit (hereinafter abbreviated as a signal detection circuit) for determining the presence or absence of a television signal input to the /D converter from the television signal or the synchronization signal. This is achieved by

[Effect]

The clamp timing pulse generation circuit generates a clamp pulse for operating so that the black level set by the clamp circuit through digital processing matches the clamp level before A/D conversion processing based on the determination result of the signal detection circuit. By generating this, stable clamping operation is possible regardless of the presence or absence of a signal input to the A/D converter, and efficient signal processing by the D/A converter becomes possible.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG.
In the figure, 101 is a composite video signal, 102
103 is a band pass filter (BPF), 103 is a chroma signal processing circuit, 104 is a color difference signal (R-y signal tB-y signal), 105 is a differential amplifier, 106 is an analog-digital converter (A/D converter) , 107 is a digital color difference signal, 108 is a digital signal processing circuit, and 109 is a digital color difference signal subjected to digital signal processing.

110 is a digital black level, 111 is a digital-to-analog converter (D/A converter), 112 is a differential amplifier,
113 is a clamp level control circuit, 114 is a capacitor, 115 is a synchronous separation circuit 116 is a synchronous separation output signal, 1
17 is a clamp timing pulse generation circuit, 118 is a clamp pulse, 119 is an OR circuit for a color killer detection signal 120, and 121 is an SW multiplication signal.

Next, the operation of the clamp circuit shown in FIG. 1 will be explained.

The composite video signal is first band-limited by the BPF 102 and then input to the chroma signal processing circuit 103. The chroma signal is color demodulated here to become a color difference signal 104, and then the DC is shifted by the voltage valve held by the capacitor 114 by the differential amplifier 105. And A/D
The signal is A/D converted by the converter 106 to become a digital color difference signal 107, which is sent to the digital signal processing circuit 108.

After completing digital signal processing such as changing the black level, the signal becomes an output 109 of the digital signal processing circuit. On the other hand, digital black level 1 that can be replaced with a digital signal processing circuit
10 is digital-to-analog converted by a D/A converter 111 and then input to a differential amplifier 112. In the differential amplifier 112, the output of the operational amplifier 105 and the D/A
The difference voltage with the output of the converter 111 is output. This differential voltage is applied to the capacitor 1 by the clamp level control circuit 113.
Hold it at 14. This clamp level control circuit is
It is operated by the W signal 121.

Here, a specific example of means for generating the SW signal 121 will be explained. The composite video signal 101 is synchronously separated by a sync separation circuit 115, and the synchronous separation output signal 1
Take out 16. The synchronous separation output signal 116 is generated by the clamp timing pulse generation circuit 117 so as to match the clamping period of the signal (color difference signal 104) to be clamped.
For example, during a blanking period), a clamp pulse 118 is generated and input to an OR circuit 120. On the other hand, OR circuit 102
A color killer detection signal 119 from the chroma signal processing circuit 103 is input to the chroma signal processing circuit 103 . When a composite video signal (color signal) is input, the SW signal 121 of the output signal of the OR circuit 120 operates the clamp level control circuit 113 at the timing of the clamp pulse 118.

Furthermore, since the color killer detection signal is input to the OR circuit 120 when there is no signal, the SW signal 121 operates the clamp level control circuit during the entire video period.

On the other hand, when clamping a composite video signal or a luminance signal, the configuration in the first regeneration line is changed to the configuration shown in FIG. 2. 201 is an integrator, and 202 is a no-signal detection signal obtained from the integrator. The synchronous separation output signal 116 is sent to the integrator 20
It is integrated by 1 and outputs gratuitous issue (i1 issue 202).

This no-signal detection signal is the color killer detection signal 1 in Figure 1.
Since it has the same function as No. 19, the explanation of the operation will be omitted.

As another example, this can be achieved by configuring the inside of the first regeneration line as shown in FIG. 301 is F
BT pulse, 302 is horizontal AFC circuit, 303 is 32f
, a VCO circuit, and 304 a horizontal down counter.

The operation will be explained below. television signal 1
01 Clamp timing pulse generation circuit 117 when using manual power
The clamp level control circuit 103 is operated by the clamp pulse 118 generated by.

On the other hand, when there is no signal, the VCO circuit 303 oscillates in free run at 32f, and the pulses counted down by the horizontal down counter 304 are sent to the clamp timing pulse generation circuit 1.
17, a clamp pulse 118 is constantly generated even when there is no signal, and the clamp level control circuit 113 is operated.

〔Effect of the invention〕

According to the present invention, the drawbacks of the prior art described above are solved, and the clamp level before A/D conversion processing is accurately set to match the black level set by the digital signal processing circuit, regardless of the presence or absence of an input signal. This has the effect that it can be set to

[Brief explanation of the drawing]

FIG. 7 is a block diagram showing one embodiment of the present invention, and FIG.
3 are block diagrams showing other embodiments of the clamp control circuit.

Claims (1)

[Scope of Claims] 1. A clamping means that receives an analog video signal and clamps the analog video signal, and is connected to the output of the clamping means and converts the analog video signal with the DC component clamped into a digital video signal. an analog-to-digital conversion circuit that converts the output of the analog-to-digital conversion circuit into an analog signal, and an output signal of the digital-to-analog conversion circuit and an input signal of the analog-to-digital conversion circuit are input. clamp level control means for controlling the clamp voltage of the clamp means so that both signals are equal; and clamp timing signal generation means for generating a clamp timing signal for the clamp means according to a synchronization signal of the video signal. In the video signal clamp circuit provided with the video signal, the clamp timing signal generating means generates a different clamp timing signal when there is no synchronization signal of the video signal than when there is a synchronization signal of the video signal. clamp circuit. 2. The video signal clamp circuit according to claim 1, wherein the clamp timing signal generating means outputs a color killer signal as the clamp timing signal when there is no synchronizing signal for the video signal. 3. In claim 1, the clamp timing signal generating means is characterized in that, when the synchronization signal of the video signal disappears, the clamp timing signal generating means outputs, as the clamp timing signal, an integral signal of the synchronization signal before the synchronization signal disappears. Video signal clamp circuit. 4. In claim 1, the clamp timing signal generating means comprises a horizontal A whose oscillation frequency is inputted to change in accordance with a synchronization signal.
an FC circuit; and an oscillation circuit into which the output of the horizontal AFC circuit is input, and outputs a signal corresponding to a free run signal of the oscillation circuit as a clamp timing signal when there is no synchronization signal of the video signal. Features a video signal clamp circuit.