JPH0965356A - Chroma signal processor - Google Patents
Chroma signal processorInfo
- Publication number
- JPH0965356A JPH0965356A JP7217791A JP21779195A JPH0965356A JP H0965356 A JPH0965356 A JP H0965356A JP 7217791 A JP7217791 A JP 7217791A JP 21779195 A JP21779195 A JP 21779195A JP H0965356 A JPH0965356 A JP H0965356A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- chroma signal
- chroma
- type detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Processing Of Color Television Signals (AREA)
Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【発明の属する技術分野】本発明は、ＳＥＣＡＭクロマ
信号を処理するＳＥＣＡＭクロマ信号処理回路とＰＡＬ
クロマ信号を処理するＰＡＬクロマ信号処理回路とを備
えるクロマ信号処理装置に関するもので、特に、ＳＥＣ
ＡＭクロマ信号処理回路内のＶＣＯの中心周波数を自動
調整するクロマ信号処理装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SECAM chroma signal processing circuit and PAL for processing SECAM chroma signals.
The present invention relates to a chroma signal processing device including a PAL chroma signal processing circuit that processes a chroma signal, and more particularly to a SEC
The present invention relates to a chroma signal processing device that automatically adjusts the center frequency of a VCO in an AM chroma signal processing circuit.
【０００２】[0002]
【従来の技術】ＳＥＣＡＭクロマ信号は、Ｂ−Ｙ信号と
Ｒ−Ｙ信号とがＦＭ変調されて線順次で送られており、
そのキャリア周波数も４.２５ＭＨＺ（ＢーＹ）と、４.
４０６ＭＨＺ（ＲーＹ）とで異なっている。そこで、従
来はＰＬＬ型検波器のＶＣＯの中心周波数を４.３３Ｍ
ＨＺ（４.２５ＭＨＺと４.４０６ＭＨＺの中間）に手動
で調整し、クロマ信号の検波を行っていた。2. Description of the Related Art In a SECAM chroma signal, a BY signal and an RY signal are FM-modulated and sent line-sequentially.
Its carrier frequency is also 4.25MHZ (BY) and 4.
406MHZ (RY) is different. Therefore, conventionally, the center frequency of the VCO of the PLL type detector is 4.33M.
It was manually adjusted to HZ (between 4.25 MHZ and 4.406 MHZ) to detect the chroma signal.
【０００３】図２は、そのようなＳＥＣＡＭクロマ信号
処理回路を示すもので、ベルフィルタ（１）より抽出さ
れたＳＥＣＡＭクロマ信号は、リミッタアンプ（２）で
振幅制限された後、ＰＬＬ検波器（３）に印加される。
位相比較器（４）は、リミッタアンプ（２）の出力信号
とＶＣＯ（５）の出力信号との掛け算を行う。その掛け
算結果は、不要成分が第１ＬＰＦ（６）で除去された
後、ＶＣＯ（５）に帰還される。FIG. 2 shows such a SECAM chroma signal processing circuit. The SECAM chroma signal extracted by the bell filter (1) is amplitude-limited by a limiter amplifier (2) and then a PLL detector ( 3) is applied.
The phase comparator (4) multiplies the output signal of the limiter amplifier (2) and the output signal of the VCO (5). The multiplication result is fed back to the VCO (5) after the unnecessary component is removed by the first LPF (6).
【０００４】その為、ＶＣＯ（５）は、外部より到来す
るＳＥＣＡＭクロマ信号に同期する。 ここで、ＶＣＯ
（５）の中心周波数は、４.３３ＭＨＺになるように可
変抵抗（７）が調整される。この為、第１ＬＰＦ（６）
の出力端にはＦＭ復調されたＳＥＣＡＭクロマ信号が現
れ、第２ＬＰＦ（８）で更に不要成分が除去されて、出
力端子（９）に導出される。Therefore, the VCO (5) is synchronized with the SECAM chroma signal coming from the outside. Where VCO
The variable resistor (7) is adjusted so that the center frequency of (5) is 4.33 MHZ. Therefore, the first LPF (6)
The SECAM chroma signal demodulated by FM appears at the output terminal of, the unnecessary component is further removed by the second LPF (8), and the signal is led to the output terminal (9).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図２の
ＳＥＣＡＭクロマ信号処理回路では、手動の調整を必要
とするので、調整に手間がかかるという問題を有する。However, the SECAM chroma signal processing circuit of FIG. 2 requires a manual adjustment, and thus has a problem that the adjustment is troublesome.
【０００６】[0006]
【課題を解決するための手段】本発明は、上述の点に鑑
みなされたもので、ＳＥＣＡＭクロマ信号を処理するＳ
ＥＣＡＭクロマ信号処理回路とＰＡＬクロマ信号を処理
するＰＡＬクロマ信号処理回路とを備え、前記ＳＥＣＡ
Ｍクロマ信号処理回路内のＶＣＯの中心周波数を調整す
るクロマ信号処理装置であって、中心周波数がＳＥＣＡ
Ｍ方式のＢ−Ｙ信号のキャリア周波数とＲ−Ｙ信号のキ
ャリア周波数との間に設定される前記ＶＣＯを有し、前
記ＳＥＣＡＭクロマ信号をＦＭ復調するＰＬＬ型検波回
路と、該ＰＬＬ型検波回路にＳＥＣＡＭクロマ信号又は
前記ＰＡＬクロマ信号処理回路内の第１及び第２基準周
波数信号を選択的に印加する選択手段と、前記第１基準
周波数信号の選択時、前記ＰＬＬ型検波回路の出力信号
を保持する第１保持手段と、前記第２基準周波数信号の
選択時、前記ＰＬＬ型検波回路の出力信号を保持する第
２保持手段と、前記第１及び第２保持手段の２つの出力
電圧をむすぶ直線上に位置する電圧を取り出す電圧発生
回路とを備え、前記電圧発生回路の出力信号に応じて前
記ＶＣＯの中心周波数を調整することを特徴とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is an S for processing a SECAM chroma signal.
An ECAM chroma signal processing circuit and a PAL chroma signal processing circuit for processing a PAL chroma signal are provided.
A chroma signal processing device for adjusting the center frequency of a VCO in an M chroma signal processing circuit, wherein the center frequency is SECA.
PLL type detection circuit having the VCO set between the carrier frequency of the M-system BY signal and the carrier frequency of the RY signal, and performing FM demodulation of the SECAM chroma signal, and the PLL type detection circuit Select means for selectively applying the SECAM chroma signal or the first and second reference frequency signals in the PAL chroma signal processing circuit, and the output signal of the PLL type detection circuit when the first reference frequency signal is selected. When the first holding means for holding and the second reference frequency signal are selected, the second holding means for holding the output signal of the PLL type detection circuit and the two output voltages of the first and second holding means are formed. A voltage generating circuit for extracting a voltage located on a straight line, and adjusting the center frequency of the VCO according to an output signal of the voltage generating circuit.
【０００７】[0007]
【発明の実施の形態】図１は、本発明のクロマ信号処理
装置を示すもので、（１０）はＰＡＬクロマ信号を処理
するＰＡＬクロマ信号処理回路、（１１）はＳＥＣＡＭ
クロマ信号処理回路を示し、図１の前記ＰＡＬクロマ信
号処理回路（１０）以外のブロック、（１２）は中心周
波数がＳＥＣＡＭ方式のＢ−Ｙ信号のキャリア周波数と
Ｒ−Ｙ信号のキャリア周波数との間に設定されるＶＣＯ
（１３）、位相比較器（１４）、ＬＰＦ（１５）、Ｖ/
Ｉ（電圧電流変換）変換器（１６）、電流加算器（１
７）を有し、ＳＥＣＡＭクロマ信号をＦＭ復調するＰＬ
Ｌ型検波回路、（１８）はＰＡＬクロマ信号処理回路
（１０）内の４.４３ＭＨＺ及び４.０ＭＨＺの一定周波
数信号を選択的に出力するスイッチ、（１９）はＰＬＬ
型検波回路（１２）にＳＥＣＡＭクロマ信号又は前記ス
イッチ（１８）からの信号を選択的に印加するスイッ
チ、（２０）は４.０ＭＨＺの信号の選択時、前記ＰＬ
Ｌ型検波回路の出力信号を保持する第１保持手段、（２
１）は４.４３ＭＨＺの信号の選択時、前記ＰＬＬ型検
波回路（１２）の出力信号を保持する第２保持手段、
（２２）は前記第１及び第２保持手段（２０）（２１）
の２つの出力電圧をむすぶ直線上に位置する電圧を取り
出す手段として動作する分圧回路、（２３）は分圧回路
（２２）の出力電圧を電流変換するＶ/Ｉ（電圧電流変
換）変換器、（２４）はＰＬＬ型検波回路（１２）の検
波出力電圧と分圧回路（２２）の出力電圧との差電圧を
ＩＤ期間抽出する第１のコンパレータ、（２５）は第１
のコンパレータ（２４）の出力信号を直流電圧に変換す
るコンデンサ、（２６）はコンデンサ（２５）の出力電
圧と基準電源（２７）の基準電圧とを比較し、Ｂ−Ｙ信
号とＲ−Ｙ信号との識別を行う第２のコンパレータであ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a chroma signal processing device of the present invention, in which (10) is a PAL chroma signal processing circuit for processing a PAL chroma signal, and (11) is SECAM.
FIG. 2 shows a chroma signal processing circuit, and blocks (12) other than the PAL chroma signal processing circuit (10) in FIG. 1 have a center frequency of the SEAM type BY signal carrier frequency and the RY signal carrier frequency. VCO set between
(13), phase comparator (14), LPF (15), V /
I (voltage-current conversion) converter (16), current adder (1
PL having 7) and FM demodulating the SECAM chroma signal
L-type detection circuit, (18) is a switch for selectively outputting a constant frequency signal of 4.43 MHZ and 4.0 MHZ in the PAL chroma signal processing circuit (10), and (19) is a PLL
A switch for selectively applying the SECAM chroma signal or the signal from the switch (18) to the type detection circuit (12), and (20) is the PL when the signal of 4.0 MHZ is selected.
First holding means for holding the output signal of the L-type detection circuit, (2
1) is second holding means for holding the output signal of the PLL type detection circuit (12) when selecting a signal of 4.43 MHZ,
(22) is the first and second holding means (20) (21)
(23) is a V / I (voltage-current conversion) converter that converts the output voltage of the voltage dividing circuit (22) into current , (24) is a first comparator for extracting the difference voltage between the detection output voltage of the PLL type detection circuit (12) and the output voltage of the voltage dividing circuit (22) during the ID period, and (25) is the first comparator.
A capacitor for converting the output signal of the comparator (24) into a DC voltage, (26) compares the output voltage of the capacitor (25) with the reference voltage of the reference power supply (27), and outputs the BY signal and the RY signal. It is a second comparator that identifies the.
【０００８】まず、通常にＳＥＣＡＭクロマ信号を復調
している場合について説明する。スイッチ（１９）は、
図示のようにａ側に切り替わる。リミッタアンプ（２）
からのＳＥＣＡＭクロマ信号は、ＰＬＬ型検波回路（１
２）でＦＭ復調される。ここで、ＶＣＯ（１３）は、後
述される方法で正確に４.３３ＭＨＺになるように自動
調整されるので、出力端子（２８）に検波出力が得られ
る。First, a case where a SECAM chroma signal is normally demodulated will be described. The switch (19)
It switches to the a side as shown. Limiter amplifier (2)
The SECAM chroma signal from the PLL type detector circuit (1
FM demodulation is performed in 2). Here, since the VCO (13) is automatically adjusted to exactly 4.33 MHZ by the method described later, a detection output is obtained at the output terminal (28).
【０００９】次にＶＣＯ（１３）の自動調整について説
明する。ＶＣＯ（１３）の自動調整は、ＳＥＣＡＭクロ
マ信号が到来していない期間を利用して行う。例えば、
垂直ブランキング期間を利用する。垂直ブランキング期
間には、スイッチ（１９）をｂ側に切り換える。そし
て、ＰＡＬクロマ信号処理回路（１０）の端子（２９）
に得られる４.０ＭＨＺの一定周波数の信号と、端子
（３０）に得られる４.４３ＭＨＺの一定周波数の信号
とを前記期間中、スイッチ（１８）から発生させる。前
記２つの一定周波数の信号は、連続して発生している。Next, the automatic adjustment of the VCO (13) will be described. The automatic adjustment of the VCO (13) is performed by using the period when the SECAM chroma signal has not arrived. For example,
Use vertical blanking period. During the vertical blanking period, the switch (19) is switched to the b side. Then, the terminal (29) of the PAL chroma signal processing circuit (10)
The constant frequency signal of 4.0 MHZ obtained at 1) and the constant frequency signal of 4.43 MHZ obtained at the terminal (30) are generated from the switch (18) during the period. The two constant frequency signals are continuously generated.
【００１０】いま、スイッチ（１８）が図示のようにａ
側に切り替わっているとすると、４.０ＭＨＺの一定周
波数の信号が、ＰＬＬ型検波回路（１２）に印加され
る。すると、４.０ＭＨＺの周波数に応じた電圧が出力
端子（２８）に得られる。このとき、第１及び第２保持
手段（２０）（２１）のスイッチ（３１）（３２）は、
スイッチ（１８）（１９）を切り換えた信号に同期した
信号で切り替わる。この場合には、スイッチ（３１）が
閉じて、スイッチ（３２）が開く。すると、第１保持手
段（２０）のコンデンサ（３３）に検波信号が充電され
る。該充電電圧は、ＶＣＯ（１３）の４.０ＭＨＺの周
波数に正確に応じた電圧となる。例えば、図３に示す
１.０Ｖの電圧となる。Now, the switch (18) is a as shown in the figure.
If it is switched to the side, a signal with a constant frequency of 4.0 MHZ is applied to the PLL type detection circuit (12). Then, a voltage corresponding to the frequency of 4.0 MHZ is obtained at the output terminal (28). At this time, the switches (31) (32) of the first and second holding means (20) (21) are
Switching is performed by a signal synchronized with the signal obtained by switching the switches (18) and (19). In this case, the switch (31) is closed and the switch (32) is opened. Then, the detection signal is charged in the capacitor (33) of the first holding means (20). The charging voltage is a voltage that accurately corresponds to the frequency of 4.0 MHz of the VCO (13). For example, the voltage is 1.0 V shown in FIG.
【００１１】次に、スイッチ（１８）が図示と逆にｂ側
に切り替わっているとすると、４.４３ＭＨＺの一定周
波数の信号が、ＰＬＬ型検波回路（１２）に印加され
る。すると、４.４３ＭＨＺの周波数に応じた電圧が出
力端子（２８）に得られる。この場合には、スイッチ
（３１）を開き、スイッチ（３２）閉じる。すると、第
２保持手段（２１）のコンデンサ（３４）に検波信号が
充電される。該充電電圧は、ＶＣＯ（１３）の４.４３
ＭＨＺの周波数に正確に応じた電圧となる。例えば、図
３に示す５.０Ｖの電圧となる。Next, assuming that the switch (18) is switched to the b side, which is the opposite of that shown in the figure, a signal with a constant frequency of 4.43 MHZ is applied to the PLL type detection circuit (12). Then, a voltage corresponding to the frequency of 4.43MHZ is obtained at the output terminal (28). In this case, the switch (31) is opened and the switch (32) is closed. Then, the detection signal is charged in the capacitor (34) of the second holding means (21). The charging voltage is 4.43 of VCO (13).
The voltage accurately corresponds to the frequency of the MHZ. For example, the voltage is 5.0 V shown in FIG.
【００１２】このため、分圧回路（２２）の両端には、
ＶＣＯ（１３）の実際の制御電圧を示す電圧が印加され
る。そして、ＰＬＬ型検波回路（１２）の検波出力とし
て直線性がよい領域を使用する。すると、ＶＣＯ（１
３）の制御電圧と発振周波数との間には、図３の直線で
示す１：１の関係が生ずる。即ち、ある周波数を得たい
場合に印加すればよい制御電圧の値を正確に知ることが
できる。例えば、ＶＣＯ（１３）を中心周波数を４.３
３ＭＨＺに設定したければ、４.１Ｖを分圧回路（２
２）から得るようにすればよい。Ｖ/Ｉ変換器（２３）
の基準電圧は、ＶＣＯ（１３）の中心周波数に応じて設
定される。Ｖ/Ｉ変換器（２３）で電流変換された信号
は、電流加算器（１７）でＶ/Ｉ変換器（１６）の出力
電流と加算されてＶＣＯ（１３）に印加され、ＶＣＯ
（１３）の中心周波数を４.３３ＭＨＺに制御する。Therefore, at both ends of the voltage dividing circuit (22),
A voltage is applied which represents the actual control voltage of the VCO (13). Then, a region having good linearity is used as the detection output of the PLL type detection circuit (12). Then, VCO (1
There is a 1: 1 relationship indicated by the straight line in FIG. 3 between the control voltage of 3) and the oscillation frequency. That is, it is possible to accurately know the value of the control voltage that should be applied when it is desired to obtain a certain frequency. For example, VCO (13) with center frequency of 4.3
If you want to set to 3MHZ, 4.1V voltage divider (2
It should be obtained from 2). V / I converter (23)
The reference voltage of is set according to the center frequency of the VCO (13). The signal current-converted by the V / I converter (23) is added to the output current of the V / I converter (16) by the current adder (17) and applied to the VCO (13),
The center frequency of (13) is controlled to 4.33MHZ.
【００１３】この動作は、垂直ブランキング周期で定期
的に行われ、ＶＣＯ（１３）の中心周波数自動的に一定
に保つ。分圧回路（２２）の出力電圧は、ＶＣＯ（１
３）の中心周波数を正確に示すので、Ｂ−Ｙ信号とＲ−
Ｙ信号との識別にも利用できる。第１のコンパレータ
（２４）は、ＰＬＬ型検波回路（１２）の検波出力電圧
と分圧回路（２２）の出力電圧との差電圧をＩＤ期間抽
出する。ＩＤ期間とは、ＮＴＳＣのバーストゲート期間
に相当し、無彩色期間である。Ｂ−Ｙ信号時は、４.２
５ＭＨＺが、Ｒ−Ｙ信号時は、４.４０６ＭＨＺが発生
する。This operation is periodically performed in the vertical blanking cycle to automatically keep the center frequency of the VCO (13) constant. The output voltage of the voltage dividing circuit (22) is VCO (1
Since the center frequency of 3) is accurately shown, the BY signal and R-
It can also be used for discrimination from the Y signal. The first comparator (24) extracts the difference voltage between the detection output voltage of the PLL type detection circuit (12) and the output voltage of the voltage dividing circuit (22) in the ID period. The ID period corresponds to the burst gate period of NTSC and is an achromatic period. 4.2 for BY signal
When 5 MHZ is RY signal, 4.406 MHZ is generated.
【００１４】今、Ｂ−Ｙ信号が到来しているとすると、
ＰＬＬ型検波回路（１２）から図３の３.３Ｖが発生
し、第１のコンパレータ（２４）に印加される。する
と、第１のコンパレータ（２４）から「Ｌ」レベルの出
力信号が発生する。又、Ｒ−Ｙ信号が到来しているとす
ると、ＰＬＬ型検波回路（１２）から図３の４.６Ｖが
発生し、第１のコンパレータ（２４）に印加される。す
ると、第１のコンパレータ（２４）から「Ｈ」レベルの
出力信号が発生する。そこで、基準電源（２７）の基準
電圧を「Ｌ」と「Ｈ」の中間値に選んでおけば、第２の
コンパレータ（２６）の出力端より、Ｂ−Ｙ信号とＲ−
Ｙ信号の識別出力が得られる。Now, assuming that BY signals have arrived,
3.3V of FIG. 3 is generated from the PLL type detection circuit (12) and applied to the first comparator (24). Then, an output signal of "L" level is generated from the first comparator (24). Assuming that the RY signal has arrived, the PLL type detection circuit (12) generates 4.6 V in FIG. 3 and applies it to the first comparator (24). Then, the output signal of "H" level is generated from the first comparator (24). Therefore, if the reference voltage of the reference power supply (27) is selected to be an intermediate value between "L" and "H", the BY signal and the R- signal are output from the output terminal of the second comparator (26).
An identification output of the Y signal is obtained.
【００１５】図４は、図１のＰＡＬクロマ信号処理回路
（１０）の具体例を示すもので、入力端子（５０）には
ＰＡＬのクロマ信号が印加される。同期検波器（５１）
は、Ｂ−Ｙ信号とＲ−Ｙ信号とをＰＬＬを利用して同期
検波する。この同期検波に際して、４.４３ＭＨＺの発
振子（５２）を必要とする。発振子（５２）が存在すれ
ば、４.４３ＭＨＺで発振する信号を容易に端子（５
３）に得られる。FIG. 4 shows a specific example of the PAL chroma signal processing circuit (10) of FIG. 1, in which the PAL chroma signal is applied to the input terminal (50). Synchronous detector (51)
Detects synchronously the BY signal and the RY signal using the PLL. For this synchronous detection, a 4.43 MHZ oscillator (52) is required. If the oscillator (52) is present, a signal oscillating at 4.43 MHZ can be easily fed to the terminal (5
3).
【００１６】同期検波器（５１）からのＢ−Ｙ信号とＲ
−Ｙ信号とは、各々１Ｈ（１水平期間）遅延回路（５
４）（５５）に印加される。遅延された信号とされてい
ない信号の計４つの信号が処理回路（５６）に印加され
て、端子（５７）乃至（５９）に３つの色差信号が得ら
れる。ここで、遅延回路（５４）（５５）にはＣＣＤが
使用され、そのクロック信号として、４ＭＨＺの信号が
利用されている。該４ＭＨＺの信号は、端子（６０）か
らの水平同期信号ｆＨにロックするＰＬＬ回路（６１）
により作成されている。この信号も連続して一定周波数
を保っており、基準信号として利用できる。BY signal and R from the synchronous detector (51)
The -Y signal means a delay circuit (5
4) Applied to (55). A total of four signals, delayed signals and non-delayed signals, are applied to the processing circuit (56), and three color difference signals are obtained at the terminals (57) to (59). Here, a CCD is used for the delay circuits (54) and (55), and a 4MHZ signal is used as its clock signal. The 4MHZ signal is a PLL circuit (61) that locks to the horizontal synchronizing signal fH from the terminal (60).
It is created by This signal also maintains a constant frequency continuously and can be used as a reference signal.
【００１７】又、このほかにも、ＴＶ受像機の選局用マ
イコンにも４ＭＨＺの発振子が使用されており、これを
用いてもよい。In addition to this, a 4 MHZ oscillator is also used in the channel selection microcomputer of the TV receiver, and this may be used.
【００１８】[0018]
【発明の効果】以上述べた如く、本発明によれば、ＳＥ
ＣＡＭクロマ信号処理回路内のＶＣＯの中心周波数を自
動調整するクロマ信号処理装置が提供できる。又、本発
明によれば、Ｂ−Ｙ信号とＲ−Ｙ信号の正確な識別出力
が得られる。更に、本発明により得られるＶＣＯの制御
電圧は、絶対値は温度などにより変動するが、相対値は
常に一定なので、実質的に正確なレベル比較が可能とな
る。As described above, according to the present invention, SE
A chroma signal processing device for automatically adjusting the center frequency of a VCO in a CAM chroma signal processing circuit can be provided. Further, according to the present invention, an accurate discriminative output of the BY signal and the RY signal can be obtained. Further, the control voltage of the VCO obtained by the present invention has a relative value that is always constant although its absolute value fluctuates due to temperature and the like, so that a substantially accurate level comparison is possible.
【図１】本発明のクロマ信号処理装置を示すブロック図
である。FIG. 1 is a block diagram showing a chroma signal processing device of the present invention.
【図２】従来のクロマ信号処理装置を示すブロック図で
ある。FIG. 2 is a block diagram showing a conventional chroma signal processing device.
【図３】本発明のクロマ信号処理装置の特性説明をする
ための特性図である。FIG. 3 is a characteristic diagram for explaining characteristics of the chroma signal processing device of the present invention.
【図４】図１のＰＡＬクロマ信号処理回路（１０）の具
体例を示すブロック図である。FIG. 4 is a block diagram showing a specific example of a PAL chroma signal processing circuit (10) in FIG.
（１２） ＰＬＬ型検波回路 （１８） スイッチ （１９） スイッチ （２０） 第１保持手段 （２１） 第２保持手段 （２２） 分圧回路 (12) PLL type detection circuit (18) switch (19) switch (20) first holding means (21) second holding means (22) voltage dividing circuit
Claims (2)
ＡＭクロマ信号処理回路とＰＡＬクロマ信号を処理する
ＰＡＬクロマ信号処理回路とを備え、前記ＳＥＣＡＭク
ロマ信号処理回路内のＶＣＯの中心周波数を調整するク
ロマ信号処理装置であって、 中心周波数がＳＥＣＡＭ方式のＢ−Ｙ信号のキャリア周
波数とＲ−Ｙ信号のキャリア周波数との間に設定される
前記ＶＣＯを有し、前記ＳＥＣＡＭクロマ信号をＦＭ復
調するＰＬＬ型検波回路と、 該ＰＬＬ型検波回路にＳＥＣＡＭクロマ信号又は前記Ｐ
ＡＬクロマ信号処理回路内の第１及び第２基準周波数信
号を選択的に印加する選択手段と、 前記第１基準周波数信号の選択時、前記ＰＬＬ型検波回
路の出力信号を保持する第１保持手段と、 前記第２基準周波数信号の選択時、前記ＰＬＬ型検波回
路の出力信号を保持する第２保持手段と、 前記第１及び第２保持手段の２つの出力電圧をむすぶ直
線上に位置する電圧を取り出す電圧発生回路と、を備
え、前記電圧発生回路の出力信号に応じて前記ＶＣＯの
中心周波数を調整することを特徴とするクロマ信号処理
装置。1. A SEC for processing a SECAM chroma signal.
A chroma signal processing device, comprising an AM chroma signal processing circuit and a PAL chroma signal processing circuit for processing a PAL chroma signal, for adjusting the center frequency of a VCO in the SECAM chroma signal processing circuit, wherein the center frequency is a SECAM system. A PLL type detection circuit which has the VCO set between the carrier frequency of the BY signal and the carrier frequency of the RY signal and FM demodulates the SECAM chroma signal, and a SECAM chroma circuit for the PLL type detection circuit. Signal or P
Selecting means for selectively applying the first and second reference frequency signals in the AL chroma signal processing circuit; and first holding means for holding the output signal of the PLL type detection circuit when the first reference frequency signal is selected. A second holding means for holding the output signal of the PLL type detection circuit when the second reference frequency signal is selected, and a voltage located on a straight line connecting the two output voltages of the first and second holding means. And a voltage generating circuit for extracting the voltage, and adjusting the center frequency of the VCO according to the output signal of the voltage generating circuit.
ＡＭクロマ信号処理回路とＰＡＬクロマ信号を処理する
ＰＡＬクロマ信号処理回路とを備え、前記ＳＥＣＡＭク
ロマ信号処理回路内のＶＣＯの中心周波数を調整するク
ロマ信号処理装置であって、 中心周波数がＳＥＣＡＭ方式のＢ−Ｙ信号のキャリア周
波数とＲ−Ｙ信号のキャリア周波数との間に設定される
前記ＶＣＯを有し、前記ＳＥＣＡＭクロマ信号をＦＭ復
調するＰＬＬ型検波回路と、 該ＰＬＬ型検波回路にＳＥＣＡＭクロマ信号又は前記Ｐ
ＡＬクロマ信号処理回路内の第１及び第２基準周波数信
号を選択的に印加する選択手段と、 前記第１基準周波数信号の選択時、前記ＰＬＬ型検波回
路の出力信号を保持する第１保持手段と、 前記第２基準周波数信号の選択時、前記ＰＬＬ型検波回
路の出力信号を保持する第２保持手段と、 前記第１及び第２保持手段の２つの出力電圧をむすぶ直
線上に位置する電圧を取り出す電圧発生回路と、 該電圧発生回路の出力信号と前記ＰＬＬ型検波回路の出
力信号とを所定期間レベル比較する第１のコンパレータ
と、 該第１のコンパレータの出力電圧と基準電圧とをレベル
比較する第２のコンパレータと、を備え、前記電圧発生
回路の出力信号に応じて前記ＶＣＯの中心周波数を調整
するとともに前記第２のコンパレータよりＢ−Ｙ信号と
Ｒ−Ｙ信号との識別出力を得るようにしたことを特徴と
するクロマ信号処理装置。2. A SEC for processing a SECAM chroma signal.
A chroma signal processing device, comprising an AM chroma signal processing circuit and a PAL chroma signal processing circuit for processing a PAL chroma signal, for adjusting the center frequency of a VCO in the SECAM chroma signal processing circuit, wherein the center frequency is a SECAM system. A PLL type detection circuit having the VCO set between the carrier frequency of the BY signal and the carrier frequency of the RY signal, for performing FM demodulation of the SECAM chroma signal, and a SECAM chroma circuit for the PLL type detection circuit. Signal or P
Selecting means for selectively applying the first and second reference frequency signals in the AL chroma signal processing circuit; and first holding means for holding the output signal of the PLL type detection circuit when the first reference frequency signal is selected. A second holding means for holding the output signal of the PLL type detection circuit when the second reference frequency signal is selected, and a voltage located on a straight line connecting the two output voltages of the first and second holding means. , A first comparator for comparing the output signal of the voltage generation circuit and the output signal of the PLL type detection circuit for a predetermined period of time, and a level of the output voltage of the first comparator and the reference voltage. A second comparator for comparison, which adjusts the center frequency of the VCO according to the output signal of the voltage generating circuit, and outputs the BY signal and the RY signal from the second comparator. No. and chroma signal processing apparatus being characterized in that to obtain the identification output.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07217791A JP3118395B2 (en) | 1995-08-25 | 1995-08-25 | Chroma signal processor |
| CNB961224096A CN1147163C (en) | 1995-08-25 | 1996-08-23 | Colour signal processing apparatus |
| KR1019960035345A KR100231501B1 (en) | 1995-08-25 | 1996-08-24 | Chroma signal processing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07217791A JP3118395B2 (en) | 1995-08-25 | 1995-08-25 | Chroma signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0965356A true JPH0965356A (en) | 1997-03-07 |
| JP3118395B2 JP3118395B2 (en) | 2000-12-18 |
Family
ID=16709791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07217791A Expired - Fee Related JP3118395B2 (en) | 1995-08-25 | 1995-08-25 | Chroma signal processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3118395B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0932311A2 (en) * | 1998-01-20 | 1999-07-28 | Kabushiki Kaisha Toshiba | Secam system chrominance signal demodulator |
| EP0952740A1 (en) * | 1998-04-24 | 1999-10-27 | STMicroelectronics S.A. | Demodulator, in particular of SECAM chrominance signal, with double frequency tuning |
| FR2778053A1 (en) * | 1998-04-24 | 1999-10-29 | Sgs Thomson Microelectronics | Chrominance demodulator circuit for operation with SECAM television signals |
| JP2009111865A (en) * | 2007-10-31 | 2009-05-21 | Sanyo Electric Co Ltd | Color signal processing circuit |
-
1995
- 1995-08-25 JP JP07217791A patent/JP3118395B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0932311A2 (en) * | 1998-01-20 | 1999-07-28 | Kabushiki Kaisha Toshiba | Secam system chrominance signal demodulator |
| EP0932311A3 (en) * | 1998-01-20 | 2003-08-20 | Kabushiki Kaisha Toshiba | SECAM system chrominance signal demodulator |
| EP0952740A1 (en) * | 1998-04-24 | 1999-10-27 | STMicroelectronics S.A. | Demodulator, in particular of SECAM chrominance signal, with double frequency tuning |
| FR2778052A1 (en) * | 1998-04-24 | 1999-10-29 | Sgs Thomson Microelectronics | DEMODULATOR, IN PARTICULAR OF SECAM CHROMINANCE SIGNAL, WITH DOUBLE FREQUENCY ADJUSTMENT |
| FR2778053A1 (en) * | 1998-04-24 | 1999-10-29 | Sgs Thomson Microelectronics | Chrominance demodulator circuit for operation with SECAM television signals |
| US6151080A (en) * | 1998-04-24 | 2000-11-21 | Stmicroelectronics S.A. | Secam chrominance signal demodulator with two red-blue channels and a single oscillator |
| US6433837B1 (en) | 1998-04-24 | 2002-08-13 | Stmicroelectronics | Demodulator, particularly for a SECAM chrominance signal, with double frequency adjustment |
| JP2009111865A (en) * | 2007-10-31 | 2009-05-21 | Sanyo Electric Co Ltd | Color signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3118395B2 (en) | 2000-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5333054A (en) | Apparatus for reducing noise in a video signal by processing a luminance and chrominance component | |
| EP0472332A1 (en) | Circuit for generating a clock signal which is locked to a specific phase of a color burst signal in a color video signal | |
| CA2002555C (en) | Television receiver | |
| US6538702B1 (en) | Digital color signal reproducing circuit | |
| JP3118395B2 (en) | Chroma signal processor | |
| JP3133658B2 (en) | Chroma signal processor | |
| NL192177C (en) | Signal processing circuit for processing the chrominance signal component independently of an applied standard signal transmission mode. | |
| KR100406451B1 (en) | Signal processing circuit | |
| KR100231501B1 (en) | Chroma signal processing apparatus | |
| JP3263596B2 (en) | Color signal demodulation circuit | |
| EP0160531A2 (en) | Demodulator circuits for amplitude-modulated signals | |
| JP2823291B2 (en) | SECAM type line identification circuit | |
| JP2001094821A (en) | Sampling clock generation circuit | |
| JP3253482B2 (en) | Color signal demodulation circuit | |
| JP3123865B2 (en) | SECAM color signal demodulator | |
| JP3253361B2 (en) | SECAM demodulation circuit | |
| GB2223644A (en) | Chroma key signal generator for a video editing apparatus | |
| JPH05219522A (en) | Yc separator circuit | |
| KR910005363Y1 (en) | Chroma-key signal generator | |
| JPS646617Y2 (en) | ||
| JP3244398B2 (en) | PAL color signal demodulation circuit | |
| KR960010225Y1 (en) | External synchronization circuit | |
| JPH05130633A (en) | Circuit arrangement for demodulating chrominance signal | |
| JPH03205995A (en) | Jitter removing circuit for chroma signal and television receiver using the same | |
| JPH0410791A (en) | Circuit for matching delay time |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081006 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091006 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |