JPH027119A - Protecting circuit for inserting and extracting package in hot-line - Google Patents

Protecting circuit for inserting and extracting package in hot-line

Info

Publication number
JPH027119A
JPH027119A JP63156014A JP15601488A JPH027119A JP H027119 A JPH027119 A JP H027119A JP 63156014 A JP63156014 A JP 63156014A JP 15601488 A JP15601488 A JP 15601488A JP H027119 A JPH027119 A JP H027119A
Authority
JP
Japan
Prior art keywords
pkg
power source
package
buffer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63156014A
Other languages
Japanese (ja)
Inventor
Yasuyo Nishimura
安代 西村
Yoshiaki Suzuki
良明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63156014A priority Critical patent/JPH027119A/en
Publication of JPH027119A publication Critical patent/JPH027119A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent a malfunction due to the fact that a driver gives the bad influence to a system bus by making ineffective a buffer between a backboard and a package when the package is inserted and extracted. CONSTITUTION:When a package (PKG) is inserted in hot-line, the power source is supplied from an external supply power source 1 to the PKG beforehand, and thus, a power-on resetting signal is generated from a resetting circuit 3. Further, an external power source detecting circuit 2 detects that a power source 1 is connected and sends the power source detecting signal to a driver control 5. The control 5 controls a buffer 6 of a system bus 7 between the PKG and backboards and an ineffective signal is sent by a power source detecting signal from the circuit 2 to the buffer 6. After the PKG is inserted into the sub-rack, the power source 1 is removed, and after the PKG is initialized, the output of the buffer 6 is activated by the command from a CPU 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデータ伝送装置に用いられ、データ伝送装置内
にパッケージを挿入する際及びパッケージ抜取シの際、
 MUXバス・CPUバス等を保護するための保護回路
に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in a data transmission device, and when inserting a package into the data transmission device and removing the package,
This invention relates to a protection circuit for protecting MUX buses, CPU buses, etc.

〔従来の技術〕[Conventional technology]

従来、データ伝送装置にパッケージの挿抜等の活線挿抜
を行う際には、装置の保護として。
Conventionally, when hot-swapping, such as inserting and removing packages in data transmission equipment, it was used to protect the equipment.

パッケージ(以下PKGと略す。)のカードエツジコネ
クタ部の接触電極の長さを変え、GND(接地)、電源
、信号線の順にシステム側のバスに接続している。また
、電源ライン(PKG上)にコイルを挿入して、突入電
流の防止をする等の対策がなされている。
The length of the contact electrode of the card edge connector part of the package (hereinafter abbreviated as PKG) is changed, and the GND (ground), power supply, and signal lines are connected to the system bus in this order. Additionally, measures have been taken such as inserting a coil into the power supply line (on the PKG) to prevent rush current.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の装置保護の場合、PKGのカードエツジ
コネクタ部の接触電極の長さを変えてGND 、電源、
信号線の順にシステム側のバスと接続し、信号線、電源
、GNDの順にシステムバスと切離しているだけである
ので、PKGのドライバ出力が不定となシ、システムバ
スへ悪影響を及ぼすという問題点がある。′ 〔課題を解決するための手段〕 本発明によれば、パッケージを該パッケージを収容する
サブラックに挿抜する際に用いられ。
In the case of the conventional device protection described above, the length of the contact electrode of the card edge connector part of the PKG is changed to connect GND, power supply,
Since the signal lines are connected to the system bus in that order, and the signal lines, power supply, and GND are disconnected from the system bus in that order, the problem is that the PKG driver output is unstable and has a negative effect on the system bus. There is. [Means for Solving the Problems] According to the present invention, it is used when inserting and removing a package into and from a subrack that accommodates the package.

該パッケージに電源が接続されたことを検出する検出手
段と、該検出手段からの検出信号を受けるとシステムバ
スと接続されるドライバー手段を無効とするコントロー
ル手段とを有することを特徴とするパッケージ活線挿抜
用保護回路が得られる。
A package activity characterized by having a detection means for detecting that a power source is connected to the package, and a control means for disabling a driver means connected to a system bus upon receiving a detection signal from the detection means. A protection circuit for wire insertion/extraction is obtained.

〔実施例〕〔Example〕

次に本発明について実施例によって説明する。 Next, the present invention will be explained with reference to examples.

まず第1図及び第2図を参照して、PKGを活線挿入す
る場合、予め外部供給電源1よ、9PKGに電源を供給
する。これによって、リセット回路3からパワーオンリ
セット信号が発生する。
First, referring to FIGS. 1 and 2, when inserting a PKG into a hot line, external power supply 1 supplies power to PKG 9 in advance. As a result, a power-on reset signal is generated from the reset circuit 3.

さらに外部電源検出回路2により電源1が接続されてい
ることが検出され、ドライバーコントロール5に電源検
出信号が送られる。ドライバーコントロール5ではPK
G−バックボード間のシステムバスのバッファ6のコン
トロール手段っておシ、外部電源検出回路2からの電源
検出信号に基づいてバッファ6に無効(Disable
 )信号を送る。そして、 PKGをサブラックへ挿入
完了後、外部供給電源1を取りはずし、 PKGの初期
化を行った後、CPU4からコマンドをドライバーコン
トロール5に与え、バッファ6の出力をイネーブル(E
nable )にする。
Furthermore, the external power supply detection circuit 2 detects that the power supply 1 is connected, and sends a power supply detection signal to the driver control 5. PK in driver control 5
The control means for the buffer 6 of the system bus between the G and backboards is configured to disable the buffer 6 based on the power supply detection signal from the external power supply detection circuit 2.
) send a signal. After inserting the PKG into the subrack, remove the external power supply 1 and initialize the PKG. Then, the CPU 4 gives a command to the driver control 5 to enable the output of the buffer 6 (E
nable ).

同様にして、PKGを抜取る際にも、予め前面より電源
を供給しバッファ6をDisableにしPKGをサブ
ラックから抜取る。
Similarly, when removing a PKG, power is supplied from the front in advance, the buffer 6 is disabled, and the PKG is removed from the subrack.

次に第3図を参照して具体例について説明する(なお、
第3図には第1図のリセット回路3を示さず)。 外部
電源(図示せず)が前面電源端子10に接続されると、
インバーター8からレベル信号が出力され、この結果、
・フリップフロップ9にロウレベル信号が与えられて、
フリップフロップ9はロウレベルを出力する。これによ
って、アンドゲート11からロウレベルが出力され、バ
ッファ6が無効とされる。
Next, a specific example will be explained with reference to FIG.
(The reset circuit 3 of FIG. 1 is not shown in FIG. 3). When an external power source (not shown) is connected to the front power terminal 10,
A level signal is output from the inverter 8, and as a result,
- A low level signal is given to the flip-flop 9,
Flip-flop 9 outputs a low level. As a result, a low level is output from the AND gate 11, and the buffer 6 is made invalid.

一方、外部電源が前面電源端子lOからはずされると、
インバータ8からノ・イレペル信号が出力され、この結
果、フリップフロップ9からハイレベルが出力され、バ
ッファ6はイネーブルとなる。
On the other hand, when the external power supply is removed from the front power supply terminal lO,
The inverter 8 outputs the no-repel signal, and as a result, the flip-flop 9 outputs a high level signal, and the buffer 6 is enabled.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、PKGを挿抜する際に
外部から電源を供給しバックボードとPKG間のバッフ
ァをDisableとすることにより。
As explained above, in the present invention, when inserting and removing the PKG, power is supplied from the outside and the buffer between the backboard and the PKG is disabled.

ドライバがシステムバスへ悪影響を及ぼし、誤動作する
のを防止できるという効果がある。
This has the effect of preventing the driver from adversely affecting the system bus and causing malfunctions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本1発明による保護回路の一実施例を示すブロ
ック図である。第2図は第1図の保護回路の動作を説明
するための図、第3図は第1図の具体例を示す図である
。 l・・・外部供給電源、2・・・外部電源検出回路。 3・・・リセット回路、4・・・CPU、5・・・ドラ
イバーコントロール、6°°°バツフア、7システムバ
ス。 8・・・インバーター、9・・・フリップフロップ。 ■PKθ挿入時 Δ」(社)― 第2図 (−埋入(7733)弁理士池田麻保
FIG. 1 is a block diagram showing an embodiment of a protection circuit according to the first invention. FIG. 2 is a diagram for explaining the operation of the protection circuit of FIG. 1, and FIG. 3 is a diagram showing a specific example of FIG. 1. l...External power supply, 2...External power supply detection circuit. 3... Reset circuit, 4... CPU, 5... Driver control, 6°°° buffer, 7 system bus. 8...Inverter, 9...Flip-flop. ■Δ when inserting PKθ” (company) - Figure 2 (-embedding (7733) Patent attorney Asaho Ikeda

Claims (1)

【特許請求の範囲】[Claims] 1、パッケージを該パッケージを収容するサブラックに
挿抜する際に用いられ、該パッケージに電源が接続され
たことを検出する検出手段と、該検出手段からの検出信
号を受けるとシステムバスと接続されるドライバー手段
を無効とするコントロール手段とを有することを特徴と
するパッケージ活線挿抜用保護回路。
1. A detection means used when a package is inserted into or removed from a subrack that accommodates the package, and detects that a power supply is connected to the package, and a detection means that is connected to the system bus upon receiving a detection signal from the detection means. A protection circuit for package hot-swapping, characterized in that it has a control means for disabling a driver means.
JP63156014A 1988-06-25 1988-06-25 Protecting circuit for inserting and extracting package in hot-line Pending JPH027119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63156014A JPH027119A (en) 1988-06-25 1988-06-25 Protecting circuit for inserting and extracting package in hot-line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63156014A JPH027119A (en) 1988-06-25 1988-06-25 Protecting circuit for inserting and extracting package in hot-line

Publications (1)

Publication Number Publication Date
JPH027119A true JPH027119A (en) 1990-01-11

Family

ID=15618432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63156014A Pending JPH027119A (en) 1988-06-25 1988-06-25 Protecting circuit for inserting and extracting package in hot-line

Country Status (1)

Country Link
JP (1) JPH027119A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5488924A (en) * 1993-12-06 1996-02-06 Memc Electronic Materials Hopper for use in charging semiconductor source material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5488924A (en) * 1993-12-06 1996-02-06 Memc Electronic Materials Hopper for use in charging semiconductor source material

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