JP2980454B2 - State protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state protection system,
In particular, a first processing module which is physically removable in the apparatus and which is connected to the first processing module via a motherboard or directly connected to the first processing module, And at least one second processing module that is given an internal state protection command when the processing module is removed and receives an internal state protection release command when inserted. The present invention relates to a method for protecting the internal state of the second processing module at the time of insertion / removal.

[0001]

2. Description of the Related Art In recent years, various electronic communication devices and the like have been required to have a configuration in consideration of miniaturization, multi-functionality, and ease of repair in the event of a failure. For example, in a public system or the like, the above-mentioned demands are strongly demanded.

For example, in a relay transmission device such as a dedicated line for transmission communication, an internal configuration (package configuration, board configuration) for relaying signals of a plurality of dedicated lines tends to be complicated, and as a result, a failure occurs. Configuration that makes it easy to repair when there is a problem, or a certain part (package) in the relay transmission device
Therefore, there is a demand for a configuration in which this influence is less likely to affect other internal circuits (packages) when a failure occurs.

[0003] Hereinafter, while specifically showing the board configuration of the relay transmission unit in the relay transmission apparatus, this interface when a plurality of processing boards inside the unit and an interface board for interfacing with the outside of the unit fails will be described. A method for replacing a board will be described.

FIG. 2 is a functional block diagram of a certain relay transmission unit.

In FIG . 2, this relay transmission unit 50
Are interface boards 51, processing boards 53, 5
And 4. Interface board 51
Takes the data from the external control unit 61, and stored in the volatile memory 51, and supplies this memory 52 at some time in the processing board 53 reads the data, processing
The registers 55 and 56 in the processing boards 53 and 54 hold the data. This data held in these registers 55 and 56 are used for internal processing as needed.

[0006] The above processing board 53,5 4, for example, takes in the digital data of each signal transmission line, and clock extraction, synchronously frame by performing processes including each for performing channel exchange of the frame , And outputs the processed data to the control unit 61 through the interface board 51 again.

For example, if the interface board 51 fails for any reason, the connectors K8 and K9 of the interface board 51 must be removed from the connectors J8 and J9 of the unit 50. However, by extracting the interface board 51, the register 5 of the processing board 53, 54 on the load side is removed.
5, 56 data should not be disturbed. For this purpose, before the interface board 51 is extracted, a protect signal is given from the monitoring unit 62 to the interface board 51, and further a protect signal is given from the interface board 51 to each of the processing boards 53, 54. Puts the data in a protected state (a state in which the contents of the register are not changed). This protect signal
The, usually supplied at a low level for a predetermined time and supplies a high level when you want to protect.

After supplying the protect signal at a high level, the interface board 51 is connected to the connector J for the first time.
8. Remove from J9. Even if the interface board 51 is extracted in this manner, the data of the registers 55 and 56 of the processing boards 53 and 54 is not affected because the data of the processing boards 53 and 54 is protected.

Next, when inserting the interface board 51 into the connectors J8 and J9, the interface board 51 is inserted into the connectors J8 and J9 in the above-mentioned protected state. Next, the interface board 51 is
The normal data immediately before the protection state is obtained from the memory 52 and stored in the memory 52. The monitoring unit 62 changes the protect signal from the high level state to the low level state and supplies it to the interface board 51. The interface board 51 supplies the low-level non-protection signal to each of the processing boards 53 and 54 to supply an internal register 55,
56 is released to the non-protection state, and the state is updated by data supplied from the memory 52 of the interface board 51.

[0010]

However, before the interface board 51 is removed, the monitoring unit 6
2 to the interface board 51 to provide a high-level protect signal for bringing the board into the protect state.
By supplying, can be the data of the registers 55, 56 to the protection state, cut with be withdrawn first interface board 51 after this setting, there is troublesome.

When the interface board 51 is inserted, a low-level non-protection signal is supplied from the monitoring unit 62 to the interface board 51 from the inserted state, and further supplied to each of the processing boards 53 and 54. It is sufficient if the data in the registers 55 and 56 does not change until the state is released. However, there is a problem that an indeterminate state may be caused by the operation of the interface board 51.

Therefore, there has been a demand for a device which does not have the above-mentioned problems and which can easily extract and insert the interface board 51.

Resolving the above-mentioned problems has been an important issue for the interface board 51 which interfaces both signals of the respective processing boards 53 and 54 with the outside. In practice, the number of processing boards inside the relay transmission unit 50 is often increased, which is an increasingly important issue.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the data of the second processing module even if the first processing module such as an interface module is inserted or removed. Is to provide a state protection scheme in which the state of the device is not disturbed.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a first device which can be physically inserted into and removed from an apparatus.
And the first processing module is connected to the first processing module via the motherboard or directly connected to the first processing module, and when the first processing module is removed, an internal state protection command is given. And the first
One or more second processing modules that are given an internal state protection release command when the processing module is inserted ;
The second processing module via the first processing module;
And a signal transfer unit for transferring the Le signal, in a state protection method for internal protection of the second process module upon抜挿of the first processing module, as follows
It is characterized by having done. That is, the first processing module, when the first processing module is removed from the device, before the signal path to the second processing module is disconnected, Upon detecting removal from the device , when the first processing module is inserted into the device, the device of the first processing module is connected after a signal path to the second processing module is connected. Removal detection means for detecting insertion into
And, based on the signal detected by the insertion / removal detection means,
In controlling the internal protection for the second processing module
Section protection control means, wherein the insertion / removal detection means includes
Of the connector attached to the first processing module
It is shorter than the other connection pins,
Based on the attachment / detachment of the connection pin installed at the end, the first
Detection and removal of the processing module of
Connection of the signal path between the receiving unit and the first processing module.
The connection is made with a long connection pin, and the internal protection control means
The detection of disconnection of the short connection pin allows data and setting status to be detected.
The internal state Protection Directive for holding the internal state of the state such as provides protection of the internal state is given to the second processing module before the long connection pin is withdrawn, the internal retention
Protection control means detects the insertion of the short connection pin.
And inserting the first signal module into the signal transfer section.
At the same time as the signal release
Receiving the timing signal to release the protection signal,
The internal state protection release command for enabling the internal state to be updated is given to the second processing module to release the internal state protection.

[0016]

According to the present invention, the first processing module is provided with the insertion / removal detection means, and the signal from the first processing module is disconnected before the signal path to the second processing module is disconnected. Is detected, and the internal state protection command is given to the second processing module by this detection. Therefore, there is no fear that the removal of the first processing module causes disturbance to the second module.

Further, after the signal path to the second processing module is connected, the insertion of the first processing module into the device is detected, and an internal state protection release command is sent to the second processing module by this detection. This can be applied to release the protection of the internal state.

Therefore, there is no fear that the internal state of the second processing module is disturbed by the insertion / removal of the first processing module, and there is no complication due to the protection operation and the protection release operation as in the prior art. The internal state of the second processing module can be automatically and accurately protected.

Further, among the connection pins in the connector attached to the first processing module, the short connection pins are used for removal detection and insertion detection, and the long connection pins are used for signal lines, for example. When the first processing module is unplugged, the pin shorter than the long connection pin comes out earlier, so that the unplugging is detected before the signal path is disconnected. A protection order can be issued.

In addition, when inserting, a signal path is formed by connecting a long pin first, and then a short pin is inserted, this insertion is detected, and the internal state protection is released by this detection. It can be carried out.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment in which the state protection system of the present invention is applied to a relay transmission device will be described with reference to the drawings.

FIG. 1 is a functional block diagram of the relay transmission apparatus according to this embodiment.

In FIG. 1, this relay transmission device
For example, it is composed of a relay transmission unit 8 and a control unit 9. The control unit 9 exchanges data with the relay transmission unit 8, captures a startup request signal, outputs a startup request release signal, and the like. Relay transmission unit 8
Are the interface board 1, the processing boards 2, 3 ,
And a back board 4. Backboard 4
Is a board having a motherboard function, in which the interface board 1 and the processing boards 2 and 3 are mounted in a plug-in connector system.

[0024] backboard 4, have connector J3 is mounted, this connector J3 are connected to the connector P3, backboard 4 is connected to the control unit 9. Control unit 9 supplies the data to the backboard 4, the data
Are stored in the memory 11 of the interface board 1.

The interface board 1 has a memory 11
And a start request generation circuit 12 and connectors K1 and K2
It is composed of a. Memory 11, the control unit data is stored temporarily from 9 and the data inside the supplying to each processing board 2 if necessary registers 21,
31.

[0026] The interface board 1, for example, FIG. 3 (A), the connector K1, K2 as shown in (B) are mounted. FIG. 3A is a plan view of the interface board 1, and a connector K1 is attached to the upper left side of the board 1 in FIG. 3A . Further, a connector K2 is attached to the lower side on the left side. FIG. 3B shows a three-dimensional view of the mounting state of the connectors K1 and K2 of the interface board 1. The connectors K1 and K2 are 1
It is made up of pins from number n to number n. The first pin at the upper end of the upper connector K1 is a short pin, and the other pins are long pins. In the lower connector K2, the n-th pin at the lower end is a short pin, and the other pins are long pins.

The short pins and the long pins are used as described above when the interface board 1 is temporarily removed from the connectors J1 and J2 mounted on the back board 4 with the fulcrum A or the fulcrum B as the fulcrum. Pin or n
Pin No. detects the extraction state and backboard 4
This is for detecting an insertion state when the connector is inserted into the mounted connectors J1 and J2 . In other words, when one of the fulcrums is extracted as the center, the shortest pin or the shortest n-th pin is initially disconnected. When inserting, the 1st short pin or the nth short pin is finally connected.

While the first and nth short pins are being inserted, a connection / non-connection state detection signal is supplied to the rise request generation circuit 12 at a low level. Also, while the first or nth short pin is being extracted, the connection / non-connection state detection signal is supplied to the rise request generation circuit 12 at a high level.

[0029] The operation of the start-up request generation circuit 12 will be described in detail in the description with Figures 4 and 5 below.

The processing board 2 includes a register 21 having a buffer function and a connector K4.
The register 21 captures a connection state instruction signal (low level) from the output of the start-up request generation circuit 12 of the interface board 1 and captures and holds data from the memory 11. Note that the line of the connection state instruction signal is connected to the voltage Vcc in the processing board 2 via the resistor R1. Therefore, the interface board 1 is connected to the connector J1,
When it is extracted from J2, the connected / unconnected state indicating signal line is set to the high level, and the register 21 does not take in the data but holds the immediately preceding data.

Similarly to the processing board 2, the processing board 3 includes a register 31 having a buffer function and a connector K5.
Be composed of such control from the interface board 1 likewise are Na as the processing board 2.

Next, the operation of the relay transmission apparatus shown in FIG. 1 will be described. When the interface board 1 is inserted, connection / connection at a low level (level indicating connection) is performed.
The unconnected state detection signal is supplied to the start-up request generation circuit 12, and the start-up request release signal is set to a high level from the control unit 9.
Because it is supplied at (a level that does not instruct the cancellation of the start-up request), connected / unconnected state indication signal low (connected
, And the registers 21 and 31 of the processing boards 2 and 3 are updated with data supplied in the protection released state. Note that the start-up request signal from the start-up request generation circuit 12 is at a high level (meaning that no request is made).
(The taste level) , and the control unit 9 does not perform the startup processing.

When the interface board 1 is removed, the shortest pin or the nth short pin is removed first, so that a connection / non-connection state detection signal is supplied to the start request generation circuit 12 at a high level. is, connected / unconnected state instruction signal is output at a high level, the register 21 and 31 of the processing board 2 and 3 connected / unconnected state indication of the high level
The data is protected based on the signal .

When the interface board 1 is inserted, the data via the long pins can be supplied from the control unit 9 to the interface board 1 first, but temporarily supplied to the processing boards 2 and 3 from here. Even if the processing board 2,
Since 3 is in the protected state, the registers 21 and 31 are not updated. When only the long pin is connected, the connection / non-connection state detection signal is at a high level.
When the shortest pin is connected, the connection / non-connection state detection signal is supplied to the rise request generation circuit 12 at a low level. Then, the start-up request generation circuit 12 outputs the connection / non-connection state instruction signal at the high level, and outputs the start-up request signal to the low level and supplies it to the control unit 9, whereby the control unit 9 operates normally. Store data in memory 1
1 and at the same time, the start-up request release signal is set to a low level and supplied to the start-up request generation circuit 12. This supply, start-up request generator circuit 12 supplies the register 21 and 31 of the processing board 2 by the connection / non-connection state instruction signal to the B c levels. The registers 21 and 31 of the processing boards 2 and 3 release the data protection state because the connection / non-connection state instruction signal is at the low level, and
Update the retained data with the normal data supplied from 1.
To renew .

FIG. 4 is a functional block diagram of an example of the start-up request generation circuit of this embodiment. FIG. 5 is an operation timing chart of the start-up request generation circuit of this embodiment.

In FIG . 4, the rising request generation circuit includes a flip-flop FF1, a pulse generator (mono multivibrator) 121, and an OR (logical sum gate) 1.
And a NOT (inverter) 1. Connection / non-connection state detection signal (the connected state a low level, unconnected state shall be the high level.) Is supplied from the n-th short pin connector K2, the pulse generator 121 and OR1
Supplied to This connection / non-connection state detection signal line is connected to the voltage Vcc via the resistor R3.
When this line is released on the connector K2 side, it is naturally set to the high level state.

Then, a start request release signal (when the release
Low level when not released, high level when not releasedTossYou. )
Is supplied from the n-th short pin of the connector K1,
It is supplied to the reset (R) input of the flop FF1. Contact
Connected / unconnected state indication signal (for example, connection state indication is low
Level output, high level output for unconnected status indicationToss
You. ) Is output from OR1. Startup request signal (startup
Low level for start-up request, not for start-up request
High levelTossYou. ) Is output from NOT1.

Next, the operation of FIG. 4 will be described with reference to FIG.

When the interface board 1 is inserted (FIG. 5B), the pulse generator 12 and the O
A low level is applied to R1. In this state, the Q output of the flip-flop FF1 is at a low level (FIG. 5).
(G)), and this low level is supplied to OR1 and
A low level is output as the R1 output (connection / non-connection state instruction signal) (FIG. 5D). Accordingly, the processing boards 2 and 3 are set in the internal protection release state.

Next, when removing the interface board 1,
When the short pin 1 or n is disconnected first, the connection / non-connection state detection signal is supplied at a high level (FIG. 5B) and
One output is output at a high level, and an unconnection instruction signal is supplied to the processing boards 2 and 3 (FIG. 5D). Thereafter, the long pin is pulled out and the signal path is cut.

Next, when inserting the interface board 1, if the short pins 1 and n are connected after the long pins are connected, the connected / unconnected state detection signal line changes from the high level to the low level. In response to the change to the low level, the pulse generator 121 detects a change from the high level to the low level, generates a pulse, and supplies the pulse to the set (S) input of the flip-flop FF1 (FIG. )) To make the output Q high,
One output is set to a high level (FIG. 5 (G)).

On the other hand, at the same time when the output Q becomes high level, NOT1 outputs a rise request signal at low level (FIG. 5C). When the start request signal is supplied to the control unit 9 at the low level, the control unit 9 supplies the data to the memory 11, and then outputs a start request release signal with a low level pulse to output the flip-flop FF 1 of the start request generation circuit 12. (R) input of the
(E)), the Q output of the flip-flop FF1 is changed from the high level to the low level. By the low level Q output, the OR1 output is also changed from the high level to the low level, and the registers 21 and 31 of the processing boards 2 and 3 are changed.
(FIG. 5D), the protection is released, and the data can be updated by the data supplied from the memory 11.

The operation of the start-up request generation circuit 12 as an example has been described above.

According to the above-described embodiment, the connection pins of the connectors K1 and K2 of the interface board 1 are assigned to the long connection pins and the short connection pins, and the short pins are connected / unconnected to the respective processing boards 2, 3. Used for
Allocate long pin for transmission of other data, connection / non-connection status indication signal, start request signal, start request release signal, etc., and disconnect while detecting data removal from short pin while transmitting data from long pin Since the state indication signal is generated and the registers 21 and 31 of each of the processing boards 2 and 3 are protected and the data lines are disconnected, data is normally protected.

Further, when the interface board 1 is inserted is longer pin is inserted before a short pin by being inserted later startup request generating circuit 12
Supplies a start-up request to the control unit 9, and the control unit 9 stores normal data in the memory 1 of the interface board 1.
1 and the data is supplied from the memory 11 to each of the processing boards 2 and 3. After that, the control unit 9 automatically issues a start request release signal to the start request generating circuit 12. Thus, the connection state indication signal is supplied to the registers 21 and 31 of the processing boards 2 and 3 to release the protection state, and the register 2 is supplied by the supplied data.
It is possible to make the contents of 1, 31 updatable,
There is no need to worry about setting indefinite data as in the past.

Therefore, it is possible to realize a device that protects the data of the other processing boards 2 and 3 even if the interface board 1 is inserted or removed with a simple configuration.

In the above embodiment, the relay transmission device has been described as an example, but the present invention is not limited to this. For example,
The present invention can be applied to a computer device or another dedicated device . Also, in the interface board 1 having the above embodiment, although the connector has been described two examples, it may be one, and may be even for three or more to apply same manner as described above .

In the above embodiment, the board type is described, but the present invention is not limited to this. For example, the present invention can be applied to a module other than the board type, and the connector type has been described using a square connector as an example, but a round connector may be used.

In the above-described embodiment, an example has been described in which the interface board 1 and the processing boards 2 and 3 are connected via the printed wiring pattern of the back board 4. However, the present invention is not limited to this. Absent. For example, the interface board 1 and the processing boards 2, 3
The present invention can be applied to a configuration in which is connected.

In the above embodiment, data protection is described as an example, but the present invention is not limited to this. For example, the present invention may be applied to protection of a setting state or the like.

In the above embodiment, the start-up request generation circuit is not limited to the configuration shown in FIGS.

[0052]

As described above, according to the present invention, the first
The second processing module is provided with an insertion / removal detection means for detecting the removal of the internal state to protect the internal state by detecting the removal of the second module. Since the protection of the internal state is given to the module to release the protection, the internal state can be automatically and accurately protected with a simple configuration without performing a special operation.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an embodiment when the present invention is applied to a relay transmission device.

FIG. 2 is a functional block diagram of a conventional example.

FIG. 3 is a diagram illustrating an example of mounting a connector on an interface board according to an embodiment;

FIG. 4 is a functional block diagram of a start-up request generation circuit according to one embodiment;

FIG. 5 is an operation timing chart of the start-up request generation circuit of one embodiment.

[Explanation of symbols]

1: Interface board, 2, 3: Processing board, 4:
Backboard (motherboard), 9 ... control unit, 1 2 ... launch request generation circuit, J1, J2, K1, K2 ... connector.

Claims (1)

(57) [Claims] 1. A first processing module which is physically insertable and removable in an apparatus, and which is connected to the first processing module via a motherboard or directly connected to the first processing module, given the internal state protection Directive in the first processing module is withdrawn, the first treatment
And one or more second processing module provided an internal state protection release command is when the module is inserted, the first
And the second processing module via the processing module
And a signal transfer unit for transferring the signals, among the second processing module during抜挿of the first processing module
In the state protection method for performing protection of a unit , the first processing module may be configured such that when the first processing module is removed from the device, before the signal path to the second processing module is disconnected. When the removal of the first processing module from the apparatus is detected , and when the first processing module is inserted into the apparatus, the signal path to the second processing module is connected after the first processing module is connected to the apparatus. Insertion / removal detection means for detecting insertion of the first processing module into the device, and the second detection module based on a signal detected by the insertion / removal detection means .
Internal protection that controls internal protection for
Protection control means, wherein the insertion / removal detection means is installed in the first processing module.
Longer than other connection pins in the attached connector
The connection pins are short and are located at both ends of the row of connection pins.
Insertion and removal of the first processing module based on
Detection, and the signal transfer unit and the first processing module.
The connection of the signal path to the module is performed by a long connection pin, and the internal protection control means causes the internal state such as data and setting state to be held by detecting the removal of the short connection pin.
Disconnect the internal state protection command because the long connection pins
Before being removed, it is given to the second processing module to protect the internal state, and the internal protection control means detects the insertion of the short connection pin.
The first signal module is supplied to the signal transmitting / receiving section by the output.
Notification of the insertion of the
Timing for receiving protection signal
And giving the internal state protection release command to the second processing module so that the internal state can be updated to release the internal state protection.