JPH0294271A - Interface package - Google Patents

Abstract

PURPOSE:To surely prevent an adverse effect on a data bus by using pins with two kinds of lengths, long and short, and setting the data bus output to an open high level. CONSTITUTION:Upper pins 15 and lower pins 17 of an interface package(IP) are set to long pins, and intermediate pins 16 and 18 are set to short pins. A specific pin of the long pins 15 and 17 is assigned as a power terminal 3, it is first brought into contact when the IP is inserted, and it is last separated when the IP is removed. The long pins are adapted for a power cutoff detecting IC 2 and a buffer IC 1. When the IP is inserted, the IC 2 is operated as soon as the terminal 8 is brought into contact with the IP, a power-on CLR signal (a) is made L, end the output of the IC 1 is set to open H. When a CHPLS signal (b) is H, an output (d) is outputted more than the output of a data bus. The power source is subsequently connected to other ICs, and data are sent to the time slot position controlled by the signal (b).

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to a time division multiplexing device that accommodates various different media. In particular, it relates to the circuit configuration of a portion of the device that outputs digital data signals from various interface boards onto a data bus.

〔overview〕

The present invention provides an interface package that is included in a time division multiplexing device, has means for outputting data in predetermined time slots, and is hot-swappable to/from a bus, with two types of pin lengths, long and short, and data bus output. By setting the oven to high level, it is possible to reliably prevent any negative impact on the data bus.

[Conventional technology]

In this type of time-division multiplexing equipment, when expanding or reducing the number of systems, it is common practice to insert and remove various interface panels while the equipment is powered on (hereinafter referred to as hot-swapping). must not cause data errors on other interface boards. Conventionally, the methods for achieving these have been to install a power switch on each interface panel itself and turn it on and off each time a package is inserted or removed, or to change the length of the connector pins instead of installing a switch on each interface panel. Another method was to make contact in the order of ground, power, and signals when inserting a package, thereby making hot insertion and removal possible.

[Problem that the invention seeks to solve]

In such a conventional method, in the former case, if the switch is operated incorrectly when inserting or removing the package, not only will it adversely affect the data bus and cause a data error, but there is also a risk that the IC will be damaged. In addition, in the latter case, it is necessary to differentiate the connector pin lengths in three stages (long pins, semi-long pins, and regular pins), and due to constraints on the mating surface with the back wiring board, the pin lengths of various pins must be different. Because the pins cannot be made large enough and there is unavoidable play in the structure, the contact order of various pins cannot be maintained when the package is inserted or removed, and data may not be transmitted to other interface packages on the bus. There are drawbacks where errors can occur. Furthermore, since three types of sequential pin lengths are added to the connector,
The disadvantage is that the cost of the connector is high.

SUMMARY OF THE INVENTION The present invention aims to eliminate these drawbacks and provides an interface package that has a simple pin structure and does not cause operational errors.

[Means for solving problems]

The present invention has an integrated circuit structure which has a pin that is attached to and removed from a socket provided on a back wiring board having a data bus, and which supplies data with a defined time slot position to the data bus via this pin. An interface package for a time division multiplexing device having a buffer, comprising power failure detection means of an integrated circuit configuration for providing a signal to put the buffer in an open collector output state when the power is connected, and the pin is connected to the first pin of a predetermined pin length. It is composed of one pin group and a second pin group having a pin length longer than the pin length of the first pin group, and a specific pin of this second pin group detects the buffer and the power supply cutoff when it comes into contact with the outlet. The device is characterized in that it forms a part of a path between the means and the power source.

[Effect]

The connector has a structure with two types of sequentials, long and short, which ensures a reliable contact order compared to a connector with three types of sequentials. One specific long pin is assigned to the power supply terminal for the power failure detection IC and buffer IC, and the other long pins are assigned to the ground terminal for all ICs in the package, and the short pins are assigned to the other pins. Assign to power and signal lines. Furthermore, the output to the data bus is an open collector output. This suppresses adverse effects on the data bus and prevents data errors from occurring in other interface packages.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. This embodiment shows a case where an interface package with two connectors mounted thereon is hot inserted and removed.

1 to 3 are external views showing the structure of the contact portion of this embodiment. As shown in FIG. 1, two connectors 11 and 12 are mounted on the interface package 10, and are hot-wired into and out of the back wiring board 20. FIG. 2(A) is a side view of the inside of the connector 11, and FIG. 2(B) is a back view. Here, three rows of connections are shown as an example. 3(A) is a side view of the inside of the connector 10, and FIG. 3(B) is a back view thereof. The interface package 10 is inserted or removed by contacting or detaching from the upper or lower part, and the interface package 1
The pins at the top 15 and bottom 17 of 0 are set as long pins, one each for the power supply of a specific IC,
The other part is assigned for grounding, and the middle part 16.18
The short pins are allocated for power and signals of other ICs.

FIG. 4 shows the circuit configuration of a portion of the interface package 10 that outputs onto the data bus.

That is, this embodiment includes a bin that is attached to and detached from a socket provided in a back wiring board 20 having a data bus, and an integrated circuit that supplies data with a defined time slot position to the data bus via the bin. The bin is equipped with a buffer ICI which is a buffer having a circuit configuration, and a power failure detection IC2 which is a power failure detection means having an integrated circuit configuration that provides a signal to set the buffer to an open collector output state when the power is connected. It is composed of a first bin group with a pin length and a second bin group with a pin length longer than the pin length of the first bin group, and the specific bin of the second bin group is configured to be connected to the buffer and the pin length when it comes into contact with the outlet. This configuration forms a path between the power-off detection means and the power supply.

Next, the operation of this embodiment will be explained.

A specific long pin is assigned as the power supply terminal 3, and is the first to be contacted when the interface package 10 is inserted, and the last to be removed when the interface package 10 is removed. This long pin is applied to the power-off detection IC2 and the buffer ICI. Furthermore, when the power supply terminal 3 contacts the interface package 10 when the interface package 10 is inserted, the power failure detection IC 2
operates, the POWERONCLR signal a becomes a low level signal, and sets the output of the buffer ICI to an open high level. The CHPLS signal is a signal that controls the time slot position at which this interface package 10 outputs data to the data bus, and is supplied as a signal with a specific width and period depending on conditions such as the type and speed of various interface boards. When the CHPLS signal is at high level, the data bus output data d is output on the data bus.
Output. That is, the interface package 10
At the time of insertion, the power is first connected to the power-off detection IC2 and the buffer ICI, the data bus output data d is set to oven high level, and the data is output from the other interface packages to specific time slot positions. This prevents any negative impact on the data bus. After that, the power supply is connected to the pond IC, and the CHPLS
Data is sent out in time slot positions controlled by signals.

Furthermore, when the interface package 10 is removed, the power terminal 3 is removed last, so the power is connected to the buffer IC 1 and the power-off detection IC 2 until the end, and the data bus output data d, which is the output to the data bus, is connected to the oven. It is kept at a high level and does not adversely affect the data bus.

〔Effect of the invention〕

As explained above, the present invention uses a connector on the package side of the part that connects the interface package and the back wiring board with two types of sequential connectors, long and short, with a reliable contact order, and 1 pin is assigned as the power supply terminal for the power failure detection IC and open collector output buffer IC, the other long pins are assigned for grounding, and the short pins are used for the power supply and signal of the IC. When an interface package is inserted, a signal will flow to the data bus after the data bus output is set to open high level, and when the package is removed, the data bus output will remain set to open high level. This has the effect that it does not have an adverse effect on the data bus and does not cause data errors in other interface packages when hot-swapping the package. Furthermore, since the connector is sequential in two stages, the contact order is reliable, there is no risk of IC damage, and there is an effect of lowering costs.

[Brief explanation of the drawing]

FIG. 1 is an overall external view of an embodiment of the present invention. 2 and 3 are structural diagrams of a connector according to an embodiment of the present invention. FIG. 4 is a connection diagram showing the circuit configuration of the embodiment of the present invention.

Claims (1)

[Claims] 1. It has a pin that can be attached to and removed from a socket provided on a back wiring board having a data bus, and data with a determined time slot position is transmitted to the data bus via this pin. an interface package for a time division multiplexing device having a buffer having an integrated circuit configuration, comprising: a power-off detection means having an integrated circuit configuration that provides a signal to cause the buffer to be in an open collector output state when the power is connected; It consists of a first pin group with a pin length of and an interface package configured to form a path between the power-off detection means and a power source.