JPH0294271A - Interface package - Google Patents

Interface package

Info

Publication number
JPH0294271A
JPH0294271A JP63245548A JP24554888A JPH0294271A JP H0294271 A JPH0294271 A JP H0294271A JP 63245548 A JP63245548 A JP 63245548A JP 24554888 A JP24554888 A JP 24554888A JP H0294271 A JPH0294271 A JP H0294271A
Authority
JP
Japan
Prior art keywords
pins
ip
output
ic
long
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63245548A
Inventor
Hideaki Funae
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP63245548A priority Critical patent/JPH0294271A/en
Publication of JPH0294271A publication Critical patent/JPH0294271A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To surely prevent an adverse effect on a data bus by using pins with two kinds of lengths, long and short, and setting the data bus output to an open high level.
CONSTITUTION: Upper pins 15 and lower pins 17 of an interface package(IP) are set to long pins, and intermediate pins 16 and 18 are set to short pins. A specific pin of the long pins 15 and 17 is assigned as a power terminal 3, it is first brought into contact when the IP is inserted, and it is last separated when the IP is removed. The long pins are adapted for a power cutoff detecting IC 2 and a buffer IC 1. When the IP is inserted, the IC 2 is operated as soon as the terminal 8 is brought into contact with the IP, a power-on CLR signal (a) is made L, end the output of the IC 1 is set to open H. When a CHPLS signal (b) is H, an output (d) is outputted more than the output of a data bus. The power source is subsequently connected to other ICs, and data are sent to the time slot position controlled by the signal (b).
COPYRIGHT: (C)1990,JPO&Japio
JP63245548A 1988-09-28 1988-09-28 Interface package Pending JPH0294271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63245548A JPH0294271A (en) 1988-09-28 1988-09-28 Interface package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63245548A JPH0294271A (en) 1988-09-28 1988-09-28 Interface package

Publications (1)

Publication Number Publication Date
JPH0294271A true JPH0294271A (en) 1990-04-05

Family

ID=17135339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63245548A Pending JPH0294271A (en) 1988-09-28 1988-09-28 Interface package

Country Status (1)

Country Link
JP (1) JPH0294271A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964855A (en) * 1997-04-07 1999-10-12 International Business Machines Corporation Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5964855A (en) * 1997-04-07 1999-10-12 International Business Machines Corporation Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system
US6041375A (en) * 1997-04-07 2000-03-21 International Business Machines Corporation Method and system for enabling nondisruptive live insertion and removal of feature cards in a computer system

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