JPH08234869A - Hot line inserting/ejecting system - Google Patents

Abstract

PURPOSE: To accelerate a bus while keeping the operation guarantee of a system due to hot line insertion/ejection. CONSTITUTION: A control PKG 110 and PKG 111 -11n to be controlled are connected through a bus signal line 121 of a first system and a bus signal line 122 of a second system. A long pin PL/short pin PS1 is provided to perform connecting in order of bus signal line 121 /bus signal line 122 in the case of inserting and connecting the PKG 111 -11n to be controlled to connectors 151 -15n for connecting the PKG 111 -11n to the bus signal lines 121 and 122 so as to insert and eject them. The PKG 111 -11n are provided with bus signal line latch circuits 1103 -11n3 for latching bus signals passed through the bus signal lines 121 and 122 through transceivers 1102 -11n2 and exclusive OR circuits 1104 -11n4 for exclusively ORing those latched bus signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hot-swap system in a system in which a control package (hereinafter, the package is referred to as PKG) and a controlled PKG are connected via a bus signal line.

[0002]

2. Description of the Related Art A conventional hot-swap system will be described with reference to FIG. In the figure, 1 ₀ control PKG, ₁ 1 ~
1 _n is a controlled PKG, 2 is a bus signal line, 3 is a transceiver control line, 4 is a backplane, 5 _{0 to} 5 _n are connectors, and S 1 to Sn are switches. Control PKG1 ₀ is C
It has a PU circuit ₁₀₁ , a transceiver ₁₀₂ and a filter ₁₀₃ . The controlled PKGs _{1 1} to 1 _n are internal circuits 1 ₁₁ to
1 _n1 , transceivers 1 ₁₂ to 1 _n2 and filters 1 ₁₃ to 1
equipped with _n3 .

[0003] bus signal line 2 from the CPU circuit 1 ₀₁ of the control PKG1 ₀ includes a transceiver 1 _02, the filter 1 _03, through a connector 5 ₀ are connected to the backplane 4 side bus signal line 2. Bus signal line 2 on the backplane 4 side
It is passed through the connector 5 ₁ to 5 _n, the controlled PKG1 ₁ to 1 _n
It is connected to the. In the controlled PKG1 ₁ to 1 _n ,
The bus signal line 2 passes through the filters 1 ₁₃ to 1 _n3 and then is connected to the internal circuits 1 ₁₁ to 1 _n1 via the transceivers 1 ₁₂ to 1 _n2 . The bus signals passing through the transceivers 1 ₁₂ to 1 _n2 are taken into the internal circuits 1 ₁₁ to 1 _n1 by the clock ck. Further, the transceiver control line 3 from the CPU circuit 1 ₀₁ includes a transceiver 1 _02, the connector 5 _0, backplane 4, connector 5 ₁ to 5 _n, through a switch S1 to Sn, the transceiver 1 of the controlled PKG1 ₁ to 1 _{n 12} to 1
It is connected to the control terminal of _n2 .

PKG failure, PKG function change, or
Insertion / extraction of PKG by addition of PKG may be performed without stopping the operation of the apparatus. In other words, in the power supply state, the operation of the system must be guaranteed even by hot-plugging and unplugging the PKG. There are the following problems when the PKG is hot-swapped. The hot-swap PKG transceiver operates erratically and gives an erroneous signal to the bus signal line. The noise generated by the connector capacity, wiring capacity, and transceiver input / output capacity of the hot-swap PKG is superimposed on the bus signal line, and the operating PKG malfunctions.

In order to prevent the above problem, that is, prevent the unstable operation of the transceiver when the PKG is hot-swapped, the following measures are taken. Taking the controlled PKG1 ₁ as an example, as shown in the control timing chart of FIG. 4, when the controlled PKG1 ₁ is inserted and connected to the bus signal line 2 on the backplane 4 side through the connector 5 ₁ (see FIG. 4), that is, when the bus signal line of the controlled PKG1 ₁ and the power supply are connected to the backplane 4, until the transceiver 1 ₁₂ and the internal circuit 1 ₁₁ become stable (point t2 in FIG. 4), the switch By turning off S1, the operation of the transceiver 1 ₁₂ is stopped and an erroneous signal is prevented from being superimposed on the bus signal line 2.

[0006] When removing the controlled PKG1 ₁ makes the switches S1 and off at a predetermined timing immediately before the controlled PKG1 ₁ is withdrawn cleavage of backplane 4 side bus signal line 2 via the connector 5 ₁ ( After the operation of the transceiver 1 ₁₂ is stopped, the controlled P
By removing KG1 ₁ (t4 point shown in FIG. 4),
That is, by disconnecting the bus signal line and the power source of the controlled PKG1 ₁ from the backplane 4, it is possible to prevent an erroneous signal from being superimposed on the bus signal line 2.

As another measure for preventing the unstable operation of the transceiver when the PKG is hot-swapped, a method without using the switches S1 to Sn has been considered. In FIG. 5, in place of the switches S1 to Sn, connectors 6 _{1 to} 6 _n having long pins PL and short pins PS are used to prevent unstable operation of the transceivers 1 ₁₂ to 1 _n2 . The controlled PKG1 ₁ will be described as an example. As shown in the control timing chart of FIG. 6, when the controlled PKG1 ₁ is inserted and connected, the long pin PL of the connector 6 ₁ is connected to the bus signal line 2 on the backplane 4 side. First, the bus signal line of the controlled PKG1 ₁ housed in the long pin PL and the power source are connected to each other (point t1 shown in FIG. 6) and connected to the backplane 4.

The short pin PS contacts the bus signal line 2 on the backplane 4 side at t2 when a sufficient time has passed until the transceiver 1 ₁₂ and the internal circuit 1 ₁₁ are stabilized,
The transceiver control line of the controlled PKG1 ₁ housed in the short pin PS is connected to the backplane 4. Thus, transceiver 1 _12, until the time t2 to short pin PS contacts, keep the operation stop state. Controlled P
When the KG1 ₁ is removed, the short pin PS and the long pin PL are in a non-contact state in this order (points t3 and t4 shown in FIG. 6), and the controlled PKG is held while the operation of the transceiver 1 ₁₂ is stopped.
The bus signal line 11 ₁ and the power supply are disconnected from the backplane 4.

The above-mentioned problem, that is, the hot-swap PKG
Connector capacity, wiring capacity, transceiver input / output capacity
The noise generated by the amount will be superimposed on the bus signal line.
For the problem, see Figure 3 and Figure 5.
And filter 1₀₃~ 1_n3Noise by inserting
It is absorbing. Controlled PKG1₁Take as an example
Then, the noise removal timing at the time of hot-plugging and unplugging is shown in FIG.
As shown, the controlled PKG1₁When inserting and removing the connector
Noise on the bus signal line 2 due to pin chattering
Occur. Don't capture this noise as a bus signal
Sea urchin control PKG1₀, Controlled PKG1₂~
1_nFilter that noise 1₀₃, 1_{twenty three}~ 1_n3Through
To remove. Control PKG1₀ CPU circuit 1₀₁, Controlled
PKG1₂~ 1_nInternal circuit 1_{twenty one}~ 1_n1Denoising
Subsequent bus signals are sent to transceiver 1₀₂, 1_{twenty two}~ 1_n2Through
Then, the clock ck is captured at the punching timing.

[0010]

However, according to the above-mentioned conventional method, noise is absorbed through the filter in order to solve the above problem, so that the system is limited to a system having a relatively low bus signal speed. As the bus signal speed becomes faster, the time width of the bus signal becomes narrower and approaches the noise width. Therefore, the bus cannot be speeded up to a speed at which the bus signal and the noise cannot be distinguished. That is, the PKG failure, the PKG function change, or the PKG extension due to the PKG's hot-swap frequency and hot-swap time is a short time compared to the operating life of the system. In the conventional method, the bus cannot be speeded up.

The present invention has been made to solve such a problem, and an object of the present invention is to maintain hot-swap system operation guarantee and to increase the bus speed. To provide a method.

[0012]

In order to achieve such an object, the first invention (the invention according to claim 1) includes a control package and first to Nth controlled packages in a first system and It is assumed that the connection is made by the second system bus signal line, and the first
~ The first to Nth connectors for connecting the Nth controlled package to the bus signal lines of the first system and the second system in a removable manner, and the first system of the first to Nth controlled packages and At the time of insertion connection to the bus signal line of the second system, the first pin / second pin contacting in order of the bus signal line of the first system / the bus signal line of the second system is provided, and the control package and the first to Nth Controlled package includes first system and second system
A bus signal line latch circuit for latching a bus signal via a system bus signal line via a transceiver, and an exclusive OR circuit for taking an exclusive OR of the bus signals latched by this bus signal line latch circuit. It is provided.

The second invention (the invention according to claim 2) is the first invention.
In the invention, the operation of the transceiver in the first to Nth controlled packages is started at a predetermined timing after the first to Nth controlled packages are inserted and connected to the bus signal line of the second system. , The first to Nth controlled packages are stopped at a predetermined timing immediately before they are removed and disconnected from the bus signal line of the second system.

According to a third invention (an invention according to claim 3), the control package and the first to Nth controlled packages are connected by the bus signal lines of the first system and the second system.
A control signal is sent from the control package to the transceivers of the 1st to Nth controlled packages, and the 1st to Nth controlled packages are removably connected to the bus signal lines of the 1st and 2nd systems. To the 1st to Nth connectors
When the first to Nth controlled packages are inserted and connected to the first and second system bus signal lines and the control signal lines, the first system bus signal line / the second system bus signal line /
A first pin / a second pin / a third pin that come in contact with the control signal lines in order are provided, and a bus signal via the bus signal lines of the first system and the second system is provided to the control package and the first to Nth controlled packages. Is provided with a bus signal line latch circuit for latching the bus signal via a transceiver, and an exclusive OR circuit for taking an exclusive OR of the bus signals latched by the bus signal line latch circuit.

[0015]

Therefore, according to the present invention, in the first invention,
For example, when the first controlled package is hot-swapped, the contact time of the first pin and the second pin of the first connector with respect to the bus signal lines of the first system and the second system is displaced,
The generation timing of the noise superimposed on the first system bus signal line and the second system bus signal line is different,
When the bus signals of both systems do not match, the output of the exclusive OR circuit in the other package becomes "1" level, and the occurrence of noise can be detected based on the output of this exclusive OR circuit.

In the second invention, in addition to the operation of the first invention,
For example, when the first controlled package is hot-swapped, the transceiver in the first controlled package starts its operation at a predetermined timing after being inserted and connected to the bus signal line of the second system, The operation is stopped at a predetermined timing immediately before the disconnection and disconnection of the bus signal line of the second system.

In the third invention, in addition to the operation of the first invention,
For example, when the first controlled package is hot-swapped, the transceiver in the first controlled package causes the second pin to be connected to the control signal line of the third pin after the second pin is connected to the bus signal line of the second system. The operation is started by the contact, and the second
The operation is stopped by disconnecting the third pin from the control signal line before the pin is disconnected from the bus signal line of the second system.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the hot-swap system according to the present invention will be described with reference to FIG. In the figure, 11 ₀ is a control PKG, 11 _{1 to} 11 _n are controlled PKGs, 12 ₁ and 12 ₂ are bus signal lines for the first and second systems, 13 is a transceiver control line, 14 is a backplane, and 15 is a backplane. ₀ ~
15 _n is a connector, and S1 to Sn are switches. The control PKG11 ₀ is a CPU circuit 11 ₀₁ and a transceiver 1
It has a bus ₁₀₂ , a bus signal latch circuit _1103, and an exclusive OR circuit ₁₁₀₄ . The controlled PKGs 11 _{1 to} 11 _n include internal circuits 11 _{11 to} 11 _n1 and transceivers 11 ₁₂ to 1.
1 _n2 , bus signal latch circuits 11 _{13 to} 11 _n3 and exclusive OR circuits 11 _{14 to} 11 _n4 . Connector 15
₁ to 15 _n have long pins PL and short pins PS ₁ and PS ₂ .

The bus signal lines 12 ₁ and 12 ₂ from the CPU circuit 11 ₀₁ of the control PKG11 _0, the bus signal latch circuit 11 _03, transceiver 11 _02, through the connector 15 _0, the backplane 4 side of the bus signal lines 12 ₁ And 12
Connected to ₂ . The bus signal lines 12 ₁ and 12 ₂ on the backplane 4 side are connected to the long pins PL and the short pins PS ₁ of the connectors 15 ₁ to 15 _n . Controlled P
In the KG11 _{1 to} 11 _n , the bus signal lines 12 ₁ and 12 ₂ pass through the transceivers 11 _{12 to} 11 _n2 , the bus signal latch circuits 11 _{13 to} 11 _n3 , and the internal circuit 11 ₁₁ to.
11 _n1 .

Signals (first and _second) from the bus signal lines 12 ₁ and 12 ₂ passing through the transceivers 11 _{12 to} 11 _n2 .
Bus signal) is latched by the bus signal latch circuits 11 _{13 to} 11 _n3 by the clock ck. The first and second bus signals latched by the bus signal latch circuits 11 _{13 to} 11 _n3 are given to the exclusive OR circuits 11 _{14 to} 11 _n4 , and at the same time, the internal circuits 11 ₁₁ to 1 by the clock ck.
Incorporated into 1 _n1 . Exclusive OR circuit 11 _{14 to} 11 _n4
Is connected to the internal circuits 11 _{11 to} 11 _n1 .
Further, the transceiver control lines from the CPU circuit 11 ₀₁ 13
It includes a transceiver 11 _02, the connector 15 _0, backplane 14, the short pin PS ₂ of the connector 15 ₁ to 15 _n, through a switch S1 to Sn, the controlled PKG11 ₁ ~11 _n
Connected to the control terminals of the transceivers 11 _{12 to} 11 _n2 . In this embodiment, the connectors 15 ₁ to 15
The short pins PS ₁ and PS ₂ in _n have the same length.

FIG. 2 shows a noise occurrence detection timing (error detection timing) when the PKG is hot-swapped. For example, it is assumed that the controlled PKG11 ₁ is hot-plugged now. In this case, first, the long pin PL of the connector 15 ₁ contacts the first-system bus signal line 12 ₁ on the backplane 14 side (point t1 shown in FIG. 2). At this time, the bus signal line 12 ₁ on the backplane 14 side, which the long pin PL contacts,
The chattering of the long pin PL causes noise to be superimposed. This noise is transmitted to the control PKG11 ₀ and the controlled PKG11 _{2 to} 11 _n in operation, and when it coincides with the punching timing of the clock ck, the C bus is output as an erroneous bus signal.
It is taken into the PU circuit 11 ₀₁ and the internal circuits 11 _{21 to} 11 _n1 .

[0022] At this time, of the controlled PKG11 ₁ connector 1
Since the short pin PS ₁ of 5 ₁ is not yet in contact with the second-system bus signal line 12 ₂ on the backplane 14 side, noise is not superimposed on the bus signal line 12 ₂ on the backplane 14 side. The bus signal of the first system bus signal line 12 ₁ (first bus signal) is different from the bus signal of the second system bus signal line 12 ₂ (second bus signal). First
Bus signal and the second bus signal are latched by the bus signal latch circuits 11 ₀₃ , 11 _{23 to} 11 _n3 . First signal latched by the bus signal latch circuits 11 ₀₃ , 11 _{23 to} 11 _n3
Of the exclusive bus circuit and the second bus signal of the exclusive OR circuit 1
1 ₀₄ , 11 _{24 to} 11 _n4 .

In this case, since the first bus signal and the second bus signal are different, the exclusive OR circuit 1
The output of the 1 _04, 11 ₂₄ ~11 _n4 becomes "1" level. This "1" level signal is sent to the CPU circuit 11 ₀₁ and the internal circuit 1
1 _{21 to} 11 _n1 . When the CPU circuit 11 ₀₁ and the internal circuits 11 _{21 to} 11 _n1 detect the “1” level signal from the exclusive OR circuits 11 ₀₄ and 11 _{24 to} 11 _n4 at the timing of punching the clock ck, noise is generated. That is, the error is detected, and the Q output of the internal flip-flop (F / F: not shown) is set to "1" level. As a result, the CPU circuit 11 ₀₁ and the internal circuits 11 _{21 to} 11 _n1 perform error processing after error detection.

That is, in the present embodiment, the controlled PKG1
When hot plugging and unplugging 1 _{1 to} 11 _n , bus signal lines 12 ₁ and 12 of the long pins PL and short pins PS ₁ of the connectors 15 ₁ to 15 _n
Since the contact time for ₂ shifts (t1 point shown in Fig. 2,
(t2 point), the generation timings of the noises superimposed on the bus signal lines 12 ₁ and 12 ₂ are different, and if a mismatch occurs between the bus signals of both systems, the exclusive OR circuit 11 ₀₄
~ 11 _n4 output goes to "1" level and circuit 11 ₀₁ ~
11 _n1 and error processing is performed.

In other words, in this embodiment, if there is no mismatch between the bus signals of both systems, the exclusive OR circuit 11 ₀₄
~ 11 _n4 output does not go to "1" level and circuit 11 ₀₁ ~
11 _n1 receives the bus signal from the pulse signal latch circuit 11 ₀₃ to 11 _n3, performs normal processing. Therefore, according to the present embodiment, even if the bus is operated at high speed, the bus signal is not mistaken as noise unless the bus signals of both systems are inconsistent.

[Second Invention] In this embodiment,
In order to prevent the unstable operation of the transceiver at the time of hot plugging and unplugging, the same measures as those described with reference to FIG. 4 are taken. That is, the transceivers 11 ₁₂ in the controlled PKGs 11 _{1 to} 11 _n are operated by operating the switches S1 to Sn.
The operation of to 11 _n2, the controlled PKG11 ₁ ~11 _n second
It starts at a predetermined timing after being inserted and connected to the bus signal line 12 _{2 of the} system, and the controlled PKGs 11 _{1 to} 11 _n are started.
Is stopped at a predetermined timing immediately before being disconnected from the second system bus signal line 12 ₂ .

[Third Invention] As a measure for preventing the unstable operation of the transceiver at the time of hot plugging and unplugging, it is conceivable to take the same measure as described with reference to FIG. That is, in FIG. 1, the short pins P in the connectors 15 ₁ to 15 _n
The S ₂ shorter than the short pin PS _1, control PKG11 transceiver control line 13 from ₀ without using the switches S1 to Sn, the connector 15 ₁ to 15 _n of the short pin PS ₂ directly via the transceiver 11 ₁₂ To 11 _n2 .

Further, in the present embodiment, the connector 15
While the pins P1, P2, P3 in ₀ are the same length, as with the connector 15 ₁ to 15 _n, the long pin PL, may be the short pins PS _1, PS _2.

[0029]

As is apparent from the above description, according to the present invention, in the first invention, for example, when the first controlled package is hot-swapped, the first pin and the second pin of the first connector are removed. Since the contact time with respect to the bus signal lines of the first system and the second system of is shifted, the generation timing of the noise superimposed on the bus signal line of the first system and the bus signal line of the second system will be different, and When the bus signals do not match, the output of the exclusive OR circuit in the other package becomes "1" level, and the noise occurrence can be detected based on the output of the exclusive OR circuit. As a result, even if the bus speed is increased, the bus signals will not be mistaken as noise unless the bus signals of both systems are mismatched, the system operation is guaranteed by hot-swap, and the bus speed is increased. Will be able to.

That is, the number of hot-plugging / unplugging operations and the hot-plugging / unplugging time of the PKG are slightly shorter than the operating life of the system, and the processing deterioration itself when an error occurs (when noise occurs) is not a serious problem. The problem is that the system stops or malfunctions, or that correction processing cannot be performed when incorrect data is received. The hot-swap method of the present invention is capable of surely detecting an error and performing error processing during hot-swap, and in normal operation other than hot-swap, the high speed of the device is effectively utilized.
It will be possible to provide bus speedup.

In the second invention, for example, when the first controlled package is hot-swapped, the transceiver in the first controlled package is inserted into and connected to the bus signal line of the second system in a predetermined manner. The operation is started at a timing, and the operation is stopped at a predetermined timing immediately before disconnection and disconnection with respect to the bus signal line of the second system. In addition to the effect of the first invention, when the PKG is hot-swapped Unstable operation of the transceiver can be prevented.

In the third invention, for example, when the first controlled package is hot-swapped, the transceiver in the first controlled package has the second pin after the second pin is connected to the bus signal line of the second system. The operation is started by contacting the control signal line of pin 3 and the operation is stopped by disconnecting the third pin from the control signal line before the second pin is disconnected from the bus signal line of the second system. In addition to the effects of the first invention, it is possible to prevent the unstable operation of the transceiver when the PKG is hot-swapped.

[Brief description of drawings]

FIG. 1 is a system configuration diagram for explaining an embodiment of a hot-swap system according to the present invention.

FIG. 2 is a timing chart of noise occurrence detection when the PKG in FIG. 1 is hot-swapped.

FIG. 3 is a system configuration diagram for explaining an example of a conventional hot-swap system.

FIG. 4 is a control timing diagram for explaining a measure for preventing unstable operation of the transceiver when the PKG in FIG. 3 is hot-swapped.

FIG. 5 is a system configuration diagram for explaining another example of a conventional hot-swap system.

FIG. 6 is a control timing diagram for explaining a measure for preventing unstable operation of the transceiver when the PKG in FIG. 5 is hot-swapped.

FIG. 7 is a noise removal timing chart when the PKG in FIGS. 3 and 5 is hot-swapped.

[Explanation of Codes] 11 ₀ ... Control PKG, 11 _{1 to} 11 _n ... Controlled PKG,
12 ₁ ... bus signal lines of the first system, 12 ₂ ... bus signal lines of the second system, 13 ... transceiver control line, 14 ... backplane, 15 ₀ to 15 _n ... connector, S1 to Sn ... switch, 11 ₀₁ ... CPU circuit, 11 ₀₂ ... Transceiver, 1
1 ₀₃ ... bus signal latch circuit, 11 ₀₄ ... exclusive OR circuit, ₁₁ 11 to 11 _n1 ... internal circuit, 11 ₁₂ to 11 _n2 ... transceiver, 11 ₁₃ to 11 _n3 ... bus signal latch circuit, 11
_{14 to} 11 _n4 ... Exclusive OR circuit, PL ... Long pin, P
S ₁ , PS ₂ ... Short pins.

Claims (3)

[Claims] 1. A bus signal line of a first system and a second system for connecting a control package and first to Nth controlled packages, and the first to Nth controlled packages to the first system.
A first to Nth connector connectable to the bus signal lines of the second system and the second system so as to be insertable and removable, wherein the first to Nth connectors are the first to Nth controlled packages. When inserting / connecting to the bus signal lines of the first system and the second system, the bus signal line of the first system / the second system
A bus having a first pin / a second pin contacting in order of bus signal lines of the system, and the control package and the first to Nth controlled packages are buses through the bus signal lines of the first system and the second system. A live line having a bus signal line latch circuit for latching a signal via a transceiver and an exclusive OR circuit for exclusive ORing the bus signals latched by the bus signal line latch circuit. Insertion / extraction method. 2. The transceiver in each of the first to Nth controlled packages according to claim 1, wherein the first to Nth controlled packages are predetermined after being inserted and connected to a bus signal line of a second system. The operation is started at a timing of, and the operation is stopped at a predetermined timing before the first to Nth controlled packages are removed and disconnected from the bus signal line of the second system. Hot-swap method. 3. A bus signal line of a first system and a second system for connecting a control package and first to Nth controlled packages, and a transceiver of the first to Nth controlled packages from the control package. To a control signal line for sending a control signal to the first to Nth controlled packages so as to be connectable to and removable from the bus signal lines of the first and second systems and the control signal line. N connectors, wherein the first to Nth connectors are connected to the first to Nth controlled system bus signal lines and control signal lines of the first to Nth controlled packages, 1st system bus signal line / 2nd system bus signal line / control signal line has 1st pin / 2nd pin / 3rd pin contacting in order, said control package and said 1st-Nth controlled The package is the above A bus signal line latch circuit for latching a bus signal via the bus signal lines of the first system and the second system via a transceiver, and an exclusive logical sum of the bus signals latched by the bus signal line latch circuit A hot-swap system having an OR circuit.