JP3270392B2 - Hot-swap protection - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hot-swap protection method, and more particularly, to a hot-swap detection and protection circuit in an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors. Regarding the protection method.

[0002]

2. Description of the Related Art In an information processing apparatus in which a plurality of electronic circuit packages are mounted on a backboard by connectors,
As a conventional technique of a hot-swap protection method for inserting and removing an electronic circuit package without turning off a power supply, for example, FIG.
(Hereinafter, referred to as a first conventional technique).

FIG. 6 is a block diagram showing a configuration of a first conventional technique, and includes electronic circuit packages 301 to 30n.
Are connected by connectors to buses (bidirectional signal lines) provided on a back board 40 such as a motherboard. Each of the electronic circuit packages 301 to 30 n includes a bus control unit 31. .

[0004] Any electronic circuit package 301
In the case of inserting / removing ｎ30n, a maintenance person instructs the diagnosis control unit 32 to start repairing by a switch provided in the information processing device in advance or by input from a terminal device. Upon receiving the repair start instruction, the diagnosis control unit 32 outputs a bus access inhibition signal to all the electronic circuit packages 301 to 30n connected to the bus, and the electronic circuit packages 301 to 30n stop accessing the bus. I do.

[0005] On the other hand, the power supply module 33 is provided with an electronic circuit package 30 to be repaired according to an instruction from the diagnosis control unit 32.
1 is turned off, and malfunction in the process of inserting and removing the electronic circuit package 301 to be repaired is forcibly suppressed. During this time, the electronic circuit package 301 to be repaired is removed or inserted. When the repair is completed, a repair end instruction is given to the diagnostic control unit 32 again by the switch or by an input from the terminal device.
The malfunction was prevented by releasing the bus access suppression signal and turning on the electric signal.

Next, another conventional technique (hereinafter, referred to as a second conventional technique) will be described with reference to FIGS. 7 and 8. FIG. FIG. 7 is a block diagram showing a configuration of a second conventional technique, and FIG. 8 is a diagram showing details of a connector pin in the second conventional technique.

In this system, as shown in FIG.
The length of the pins in the insertion / removal direction is changed with respect to the connector of the back board 41, so that the connection with the electronic circuit packages 501 to 50n has a sequence. Then, a time difference detection circuit for giving a time difference to each signal and detecting the time difference, and a bus access suppression signal generation circuit for generating a bus access suppression signal based on the output of the time difference detection circuit, are connected to the diagnosis control unit 51.
, A bus access suppression signal is transmitted to all the electronic circuit packages 501 to 50n connected to the bus.

On the other hand, each of the electronic circuit packages 501 to 50
For n, a reset signal generation circuit that detects a certain power supply voltage and outputs a reset signal for a certain time is provided, and resetting the electronic circuit package to be repaired prevents malfunction due to noise at the time of insertion and removal. Was.

Further, as another conventional technique (hereinafter, referred to as a third conventional technique), a hot-swap protection method disclosed in Japanese Patent Application Laid-Open No. 4-107614 discloses a system control package which is inserted and removed from each electronic circuit package. It describes that a signal is received to prohibit the CPU from accessing the control bus and to send a signal to all packages to ignore the control command from the control bus.

[0010]

The first prior art described above has the following problems.

The first problem is that a diagnostic control unit for suppressing bus access in response to a repair start / end instruction from a maintenance person and a power supply module for generating an electric signal are required. It is to increase.

A second problem is that the maintenance staff intervenes in addition to the package insertion / removal work, so that the occurrence rate of malfunctions due to erroneous procedures is high.

[0013] The third problem is that the processing suspension time is long because the time for stopping the bus is long, and if the information processing apparatus is used for business or the like, the business may be hindered. It is.

The second conventional technique has the following problem.

A first problem is that a time difference detection circuit and a bus access suppression signal generation circuit for all electronic circuit packages are provided in the package of the diagnostic control unit, and resetting at the time of insertion is performed in each electronic circuit package. In this case, a complicated circuit or component such as a voltage detection type reset signal generation circuit is provided, and a large number of pins are required, which increases the cost.

A second problem is to insert a signal pin after the transition period of the current of the package is completed in a state where the power supply pin is inserted into the package being inserted or removed in order to suppress the power supply voltage fluctuation of the entire device. In the case of such an online repair method, since the reset signal of this prior art reset circuit is output only for a fixed time after power-on, the reset signal is not already output when the signal pin is inserted, and chattering noise generated on the signal line is generated. This causes the package to malfunction.

In the third prior art, a dedicated system control package is provided to prohibit the CPU from accessing the control bus at the time of insertion / removal and to cause all packages to ignore the control command from the control bus. Yes,
In addition to the cost, the system cannot be controlled when the system control package fails.

An object of the present invention is to provide a hot-swap protection method which solves the above problems.

[0019]

[0020]

A first hot-swap protection method according to the present invention is a hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors. A reset signal indicating that an electronic circuit package is being inserted / removed is input, and when at least one of the electronic circuit packages is being inserted / removed by the reset signal, a bus access inhibition signal for inhibiting bus access is transmitted to all electronic circuits. An OR circuit for sending out to a circuit package is provided on the back board.

[0021]

A second hot-swap protection method according to the present invention is a hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors.
A connector provided with four pins each having a longer length in the order of a ground pin, a power pin / reset pin / bus access inhibition pin, a signal pin, and an insertion state detection pin; An electronic circuit package that continuously resets its own package to an initial state during the insertion / removal time difference and sends a reset signal to the backboard via the reset pin, and an OR circuit that receives the reset signal as an input. And a back board that sends a bus access inhibition signal for inhibiting bus access to all the electronic circuit packages via the bus access inhibition pin when the electronic circuit package is being inserted or removed. I do.

The third hot-swap protection method of the present invention comprises a plurality of
Electronic circuit package on the backboard by connector
A hot-swap protection method for an attached information processing device,
Ground pin, power pin, reset pin / bus access suppression
Pin, signal pin, insertion state detection pin
A connector having a pin length, the conductive during insertion and removal
During the insertion / removal time difference between the source pin and the insertion state detection pin,
Continue to reset the package to its initial state and
Reset signal to the backboard via the reset pin.
And the reset signal.
Equipped with an OR circuit as a force, at least one of the electronic circuits
Bus access when the road package is being
Prohibit bus access suppression signals from all electronic circuit packages.
Message via the bus access inhibit pin
And a back board .

According to a fourth hot-swap protection method of the present invention, in the second or third hot-swap protection method of the present invention, the reset signal in the electronic circuit package is generated via the insertion state detection pin. The ground signal from the backboard is used as an input, and the reset is performed by a reset signal generation unit including a Schmitt trigger buffer pulled up by a resistor in parallel with the input, and a time difference between the insertion and removal of the power supply pin and the insertion state detection pin at the time of insertion and removal. During this period, the reset signal is generated at a high level.

According to a fifth hot-swap protection method of the present invention, in the second or third hot-swap protection method of the present invention, the reset signal in the electronic circuit package is generated via the insertion state detection pin. The power supply from the backboard is used as an input, and the reset is performed by a reset signal generation unit including a Schmitt trigger buffer that is pulled down by a resistor in parallel with the input. , Wherein the reset signal is generated at a low level.

A sixth hot-swap protection method according to the present invention is a hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors.
The electronic circuit package detects insertion / removal of the self-package based on a difference in length between specific pins of the connector, generates a reset signal, and continuously resets the self-package to an initial state by the reset signal. A reset signal generating unit for transmitting the bus, and a bus control unit for receiving a bus access inhibition signal from the backboard to inhibit an access operation to a bus, wherein the backboard is transmitted from the bus and the electronic circuit package. An OR circuit that receives a reset signal and sends a bus access inhibition signal to all electronic circuit packages when the reset signal is received from at least one of the electronic circuit packages.

The seventh hot-swap protection method according to the present invention is the hot-swap protection method according to any one of the second to sixth hot-swap protection methods according to the present invention, wherein the generation of the bus access suppression signal on the backboard is performed by each electronic circuit. The reset signal from the package is input, and further, a circuit pulled down by a resistor is connected in parallel to each of the inputs, and when any of the reset signals is at a high level, the bus access suppression signal as an output is set to a high level. Alternatively, it is performed by an OR circuit which is set to a low level.

An eighth hot-swap protection method according to the present invention is the hot-swap protection method according to any one of the second to sixth hot-swap protection methods according to the present invention, wherein the generation of the bus access suppression signal on the backboard is performed by each electronic circuit. The reset signal from the package is input, and a circuit pulled up by a resistor is connected in parallel to each of the inputs. When any of the reset signals is at a low level, the bus access suppression signal as an output is set to a low level. Alternatively, a high level AND circuit is used.

A ninth hot-swap protection method according to the present invention is a hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors.
The connector has four pins having a longer length in the order of a ground pin, a power pin / bus access control pin, a signal pin, and an insertion state detection pin, and the electronic circuit package is connected via the insertion state detection pin. Further comprising a Schmitt trigger buffer which receives ground from the backboard as an input and is further pulled up by a resistor in parallel with the input, and wherein the Schmitt trigger is provided during an insertion / extraction time difference between the power supply pin and the insertion state detection pin at the time of insertion / extraction. A reset signal generating unit for generating a high-level reset signal as an output of the buffer to continuously reset the own package to an initial state and inputting the reset signal to an open drain buffer; An open drain buffer that sends the high-level reset signal to the board, A bus control unit connected to the bus access control pin and prohibiting bus access by the high-level reset signal, wherein the backboard is connected to all electronic circuit packages via the bus access control pin. It has a pull-up open drain bus.

[0030]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing details of connector pins.

Referring to FIG. 1, the back board 20 is provided with a bus for logically connecting the electronic circuit packages 101 to 10n. The bus and the electronic circuit packages 101 to 10n are connected via a connector. Connected. The lengths of the pins (electrodes) of the connector are set to four types as shown in FIG.

That is, 23a is GND (ground electrode).
The pin 23b is a Vcc pin for supplying power and is shorter than the GND pin 23a. 23c and 23d are pins set to have the same length as the Vcc pin 23b, and are used for transmitting and receiving signals for instructing suppression of access to the bus of each electronic circuit package. Reference numeral 23c denotes a bus access inhibiting pin for receiving a bus access inhibiting signal, and reference numeral 23d denotes a reset pin for transmitting a reset signal. 23e is a pin set shorter than the bus access suppression pin 23c, and is a signal pin used for transmitting and receiving a bus signal. 23f is a pin set shortest and is a package insertion state detection pin for detecting that the electronic circuit packages 101 to 10n have been securely inserted into the backboard 20.

The reset pin 23d includes resistors 211 to 21 corresponding to the electronic circuit packages 101 to 10n, respectively.
The signal is pulled down by n, and the OR logic is taken by the OR circuit 22. The output of the OR circuit 22 is applied to all the electronic circuit packages 101 to 10n with the bus access inhibiting pin 23c.
Is distributed through. Here, the pull-down by the resistors 211 to 21n is performed when the bus access suppression pin 23c is in the open state, that is, when the electronic circuit package is not inserted.
This is for guaranteeing the input of the R circuit 22 to a low level.

The reset signal generator 11 of each of the electronic circuit packages 101 to 10n has the following configuration.

The package insertion state detection pin 23f is grounded on the back board 20, and is pulled up by the resistor 15 on the electronic circuit packages 101 to 10n and input to the Schmitt trigger buffer 12. The output of the Schmitt trigger buffer 12 is output from the reset signal generator 11 as a package reset signal, and is used for resetting the electronic circuit package to an initial state.

Thus, when the back board 20 and the electronic circuit packages 101 to 10n are connected by the package insertion state detection pin 23f, the package reset signal becomes low level, and the package insertion state detection pin 23f
Is at a high level when is not connected and Vcc pin 23b is in a connected state.

The output of the Schmitt trigger buffer 12 is output to the pack panel 20 via the reset pin 23d. The Schmitt trigger buffer 12 is for removing chattering noise generated in the signal line when the package insertion state detection pin 23f is connected / disconnected.

The parts other than the package reset signal generator 11 of the electronic circuit packages 101 to 10n have the following configuration.

The bus access suppression pin 23c is input to the Schmitt trigger buffer 13, and the output signal of the bus access suppression pin 23c is input to the bus control unit 14.
The bus control unit 14 controls input / output of data to / from the bus, and has a function of suppressing an access operation to the bus while the bus access suppression signal is at a high level. The Schmitt trigger buffer 13 is for removing chattering noise generated on the signal line when the bus access suppression pin 23c is connected / disconnected.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. FIG. 3 is a time chart showing the operation when the electronic circuit package is inserted, and FIG. 4 is a time chart showing the operation when the electronic circuit package is removed.

First, the electronic circuit packages 101 to 10
A case where an arbitrary one of n electronic circuit packages is inserted will be described with reference to FIGS. 1, 2 and 3. FIG. Here, a case where the electronic circuit package 101 is inserted will be described.

First, when the electronic circuit package 101 is inserted from a state where the connector pins are not connected at all, the difference between the lengths of the respective connector pins as shown in FIG. Pin 23b,
Bus access inhibit pin 23c and reset pin 23d
Are connected to the backboard 20. In this state, power is supplied to the electronic circuit package 101, and Vcc rises and stabilizes at the rated value.

The input voltage of the Schmitt trigger buffer 12 rises and stabilizes as Vcc rises and stabilizes, the package reset signal goes from low to high level, and the electronic circuit package 101 is resetting.

When the reset pin 23 d is connected, chattering noise is generated in the bus access suppression pin 23 c of the electronic circuit packages 101 to 10 n in the initial stage, but is eliminated by the Schmitt trigger buffer 13. And the electronic circuit package 1 other than the insertion electronic circuit
Although the output of the Schmitt trigger buffer 13 of 02 to 10n remains at the low level, the insertion electronic package 1
01 becomes high level and the bus access suppression pin 23c becomes stable at high level.
The output of the Schmitt trigger buffer 13 of each of the electronic circuit packages 102 to 10n becomes a high level, and the bus access is being suppressed as shown in FIG.

Next, when the signal pin 23e is connected, chattering noise is generated in the bus at the initial stage. At this time, the inserted electronic circuit package 101 is reset to the initial state so as to cover the noise generation time zone. And all the electronic circuit packages 101 to 10n are under bus access suppression.
No. 01 does not malfunction due to noise from the bus, and the other electronic circuit packages 102 to 10n do not illegally access the bus.

Finally, when the shortest connector pin, the package insertion state detection pin 23f, is connected, chattering noise occurs at the input of the Schmitt trigger buffer 12 of the insertion electronic circuit package 101 in the initial stage. The package reset signal of the electronic circuit package 101 is removed by the buffer 12 and remains high.

Thereafter, when the input of the Schmitt trigger buffer 12 of the inserted electronic circuit package 101 is determined to be low, the package reset signal becomes low, the reset state is released, and all the electronic circuit packages 101 to 101 are reset via the reset pin 23d. The bus access inhibition pin 23c of 10n and the output of the Schmitt trigger buffer 13 (bus access inhibition signal) also become low level, the bus access inhibition state is released, and the bus operation after the electronic circuit package 101 is inserted is enabled.

Next, the electronic circuit packages 101 to 10n
The case of removing any one of the electronic circuit packages will be described with reference to FIGS. 1, 2 and 4. FIG. Here, a case where the electronic circuit package 101 is removed will be described.

First, when the electronic circuit package 101 is removed from the state where it is securely inserted into the back board 20, first, the package insertion state detection pin 23f
Is disconnected. At this time, as shown in FIG. 4, chattering noise occurs in the input of the Schmitt trigger buffer 12 of the removed electronic circuit package 101 in the initial stage, but is removed by the Schmitt trigger buffer 12, and the package reset signal remains at the low level. is there. Thereafter, when the input of the Schmitt trigger buffer 12 is determined to be at the high level, the package reset signal of the electronic circuit package 101 becomes at the high level, and all the electronic circuit packages 101 to 10n are connected via the reset pin 23d.
The bus access inhibition pin 23c and the output of the Schmitt trigger buffer 13 become high level, and the bus access is inhibited.

Next, when the signal pin 23e is disconnected, chattering noise is generated in the bus at the initial stage. At this time, the bus of all the electronic circuit packages 101 to 10n is covered in a manner that covers the noise generation time zone. Since access is being suppressed, no unauthorized access to the bus occurs.

Subsequently, when the Vcc pin 23b, the bus access inhibiting pin 23c, and the reset pin 23d are disconnected,
In the initial stage, the electronic circuit packages 102 to 10n
Although chattering noise occurs in the bus access suppression pin 23c, the noise is removed by the Schmitt trigger buffer 13, and the bus access suppression signal remains at the high level.

Thereafter, since the reset pin 23d of the removed electronic circuit package 101 is opened, the pack panel 20 is pulled down by the pull-down resistor 211 of the back board 20.
Electronic circuit package 101 for OR circuit 22
Is fixed to a low level. Accordingly, electronic circuit packages 1 other than the withdrawn electronic circuit package 101
The bus access suppression pins 23c and the output of the Schmitt trigger buffer 13 become low level, the bus access suppression state is released, and the electronic circuit package 10
1 The operation of the bus after the removal is enabled.

The embodiment of the present invention has been described above. Next, another embodiment of the present invention will be described.

First, the pull-up / pull-down in the embodiment shown in FIG.
By changing the OR logic of 0 to AND logic, the same effect as in the first embodiment can be obtained even if control is performed by negative logic.

Second, in one embodiment, as shown in FIG. 2, a pin having the same length as the Vcc (power supply) pin 23b is used as the reset pin 23d. Any length is possible as long as it is longer than the pin 23e. Also, as for the bus access inhibiting pin 23c, the same effect can be obtained by using a pin having a length equal to or less than the Vcc pin 23b and equal to or greater than the signal pin 23e.

Third, as shown in FIG. 5, an open-drain buffer is used for the OR logic portion (portion connected to the Vcc pin 23c and the reset pin 23d) of the backboard 20 in one embodiment. Similar effects can be obtained by replacing the circuit. In this embodiment, Vcc pin 23c and reset pin 23 in FIG.
d is unified as one pin as a bus access control pin 23g, the output of the reset signal generation unit 11 is connected to the input side of the open drain buffer 16, and the output of the open drain buffer 16 is connected to the input side of the Schmitt trigger buffer 13. Connect and bus access control pin 23g
Also connected. Then, the bus access control pin 23
g is connected to an open drain bus provided on the backboard 20.

In such a configuration, when a high-level reset signal is output from the reset signal generation unit 11, the self-package is continuously reset to the initial state, and at the same time, through the open drain buffer 16 and the Schmitt trigger buffer 13. The bus access suppression signal is sent to the bus control unit 14, and the bus control unit 14 suppresses the bus access from the own package. At the same time, a high-level bus access suppression signal via the open drain buffer 16 is input to the open drain bus provided on the backboard 20 via the bus access control pin 23g, and the bus is also supplied to other electronic circuit packages. An access suppression signal is sent. This embodiment has a new effect that the number of connector pins for each electronic circuit package can be reduced by one, and the mounting of a logic component on the backboard 20 becomes unnecessary.

Fourth, the Schmitt trigger buffer 12 of the embodiment is replaced with a normal buffer, and a logic circuit is added to pick up the output when the output is stabilized at the same level for a certain period of time. The effect of is obtained.

Fifth, the transmission time of the package reset signal and the bus access suppression signal is limited to the above-described embodiment as long as it is a timing that guards the noise generation period when connecting / disconnecting the bus signal pins. Not done.

Sixth, the reset signal generator 11 does not necessarily need to be the same circuit as the embodiment of FIG. 1 as long as the logic is equivalent.

Seventh, the electronic circuit packages 101 to 10
n does not need to be the same circuit, but may be the same as those of the components of the hot-swap protection system of the present invention, such as the reset signal generation unit and the circuit for receiving the bus access suppression signal.

[0063]

According to the first effect of the present invention, the insertion state is automatically detected inside the electronic circuit package.
Since a reset signal is generated by a simple circuit to notify the bus access suppression signal to all other electronic circuit packages, it is not necessary to separately provide a complicated control unit and a power supply module for controlling the electronic circuit packages. As a result, the cost can be reduced, and there is no need for the maintenance worker to instruct the start and end of insertion / removal. As a result, it is possible to prevent malfunction from occurring due to a work error.

The second effect is that the electronic circuit package is kept reset until the electronic circuit package is completely inserted after the power supply pin is turned on, so that chattering noise occurs when the signal pins are connected. In addition, a malfunction of the electronic circuit package triggered by the trigger can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing details of a connector pin.

FIG. 3 is a time chart illustrating an operation when an electronic circuit package is inserted.

FIG. 4 is a time chart showing an operation at the time of removing an electronic circuit package.

FIG. 5 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a first conventional technique.

FIG. 7 is a block diagram showing a configuration of a second conventional technique.

FIG. 8 is a diagram showing details of a connector pin according to a second conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Reset signal generation part 12, 13 Schmitt trigger buffer 14 Bus control part 15, Resistance 16 Open drain buffer 101-10n Electronic circuit package 20 Backboard 22 OR circuit 23a GND pin 23b Vcc pin 23c Bus access suppression pin 23d Reset pin 23e Signal Pin 23f Package insertion state detection pin 23g Bus access control pin 211-21n Resistance

Claims (9)

(57) [Claims] 1. A hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a backboard by connectors, wherein a reset signal indicating that each electronic circuit package is being inserted and removed is input, When at least one of the electronic circuit packages is being inserted or removed by the reset signal, the backboard has an OR circuit that sends a bus access inhibition signal for inhibiting bus access to all the electronic circuit packages. Features a hot-swap protection method. 2. A hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors, wherein a ground pin, a power pin / reset pin / bus access inhibition pin, a signal pin, A connector having pins of four lengths longer in the order of the insertion state detection pins, and a resetting of the self-package to an initial state during the insertion / removal time difference between the power supply pins and the insertion state detection pins at the time of insertion / removal. An electronic circuit package that sends a reset signal to the backboard via a pin; and an OR circuit that receives the reset signal as input, and prohibits bus access when at least one of the electronic circuit packages is being inserted or removed. A bus access inhibition signal is sent to all electronic circuit packages via the bus access inhibition pin. A hot-swap protection method, comprising: 3. A hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors, wherein a ground pin, a power pin, a reset pin, and bus access suppression are provided.
Pin, signal pin, insertion state detection pin
A connector having a pin having a length, the power supply pin at the time of insertion and extraction, and the insertion state detection pin;
The package to the initial state during the insertion / extraction time difference
And reset the battery through the reset pin.
An electronic circuit package that sends a reset signal to the board, and an OR circuit that receives the reset signal as an input.
If one of the electronic circuit packages is being
The bus access inhibit signal that prohibits bus access.
Bus access suppression for all electronic circuit packages
A hot-swap protection method , comprising: a back board that sends out the signal via a stop pin . 4. A method of generating a reset signal in the electronic circuit package, wherein the ground signal from the backboard is input through the insertion state detection pin, and a Schmitt trigger buffer pulled up by a resistor in parallel with the input is provided. 4. The hot-swap operation according to claim 2 , wherein the reset signal is generated at a high level during an insertion / extraction time difference between the power supply pin and the insertion state detection pin at the time of insertion / extraction. Protection scheme. 5. A method for generating a reset signal in the electronic circuit package, comprising: inputting power from the back board via the insertion state detection pin; and providing a Schmitt trigger buffer pulled down by a resistor in parallel with the input. 4. The hot-swap protection method according to claim 2 , wherein the reset signal is generated by a reset signal generation unit, and the reset signal is generated at a low level during a time difference between the power supply pin and the insertion state detection pin at the time of insertion / removal. 6. A hot-swap protection method for an information processing device in which a plurality of electronic circuit packages are mounted on a back board by connectors, wherein the electronic circuit package inserts and removes its own package between specific pins of the connector. A reset signal generation unit that detects a difference in length to generate a reset signal, continuously resets its own package to an initial state by the reset signal, and sends the reset signal to the backboard; and receives a bus access inhibition signal from the backboard. A bus control unit for suppressing an access operation to a bus, wherein the backboard receives the reset signal sent from the bus and the electronic circuit package as an input, and receives the reset signal from at least one of the electronic circuit packages. Bus access suppression signal for all electronic circuit packages Live insertion protection method characterized by having an OR circuit for delivering. 7. The method of generating a bus access suppression signal on the backboard includes receiving the reset signal from each electronic circuit package as an input, further connecting a circuit pulled down by a resistor to each of the inputs in parallel, and OR that sets the bus access suppression signal as an output to a high or low level when any of the signals is at a high level
7. The method according to claim 2, which is performed by a circuit.
The hot-swap protection method according to claim 1. 8. The method of generating a bus access suppression signal in the backboard, wherein the reset signal from each electronic circuit package is input, and a circuit pulled up by a resistor is connected to each of the inputs in parallel. When one of the reset signals is at a low level, the bus access suppression signal as an output is set to a low or high level.
7. The method according to claim 2, which is performed by a D circuit.
The hot-swap protection method according to claim 1. 9. A hot-swap protection method for an information processing apparatus in which a plurality of electronic circuit packages are mounted on a back board by connectors, wherein the connectors include a ground pin, a power pin / bus access control pin, and a signal pin. The electronic circuit package receives ground from the back board via the insertion state detection pin, and furthermore, in parallel with the input. A Schmitt trigger buffer pulled up by a resistor is provided, and during the insertion / removal time difference between the power supply pin and the insertion state detection pin at the time of insertion / removal, a high-level reset signal is generated as an output of the Schmitt trigger buffer to initialize the own package. And a reset signal generating circuit for inputting the reset signal to an open drain buffer. An open drain buffer that sends the high-level reset signal to the backboard via the bus access control pin; and a bus control unit that is connected to the bus access control pin and prohibits bus access with the high-level reset signal. Wherein the backboard has a pull-up open drain bus connected to all electronic circuit packages via the bus access control pins.