JPH0269686A - Method for testing semiconductor storage device - Google Patents

Abstract

PURPOSE:To invert a memory which is unstable in data holding characteristics and to surely detect a defective cell by inputting a short-period inverse digit signal which cannot be written in the normal state in a state where a holding current is reduced. CONSTITUTION:A memory Mij is selected with an address signal in a state where a high-order voltage Vcc is grounded and a low-order voltage VEE is VEE=-4.5V and data signals are supplied to digit lines Dj and the inverse of Dj during a normal writing period TWP. Then the voltage VEE is reduced to VEE=-3.5V while the voltage Vcc is maintained at the same state and a holding current IH is set to a value which is about the lower distribution limit value of the memory Mij. Then the data signals are inverted and write pulses of the shortest writing period Tnwp which is shorter than the normally writable minimum pulse width are given to the inverted data signals. In the case of a defective memory cell, the memory cell is inverted at a prescribed point of time P during the period Tnwp while the potential difference between contact voltages VA and VB is small. Since the memory cell from which inversion is detected is defective, a test can be completed with several tens mus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing semiconductor memory devices, and more particularly to a method for testing static memories.

[Conventional technology]

-m Static memory uses a transistor flip-flop circuit with a load cell such as a bipolar transistor or Schottky barrier diode as a memory cell.
Connected to the circuit power supply via a constant current circuit.

FIG. 3 is a circuit diagram of an example of a semiconductor memory device under test.

Memory cell M1. in the i-th row and j-th column to be tested. is PNP
) transistor-loaded transistor-loaded ith emitter-follower transistor Q+ and word line W, and the ith constant-current transistor Q+, the control emitters of the pair being inserted between the first row of digit lines, and the word line W, respectively. It is connected.

A circuit power supply is commonly connected to all memory cells between terminals of a high voltage VCC and a low voltage VEε.

Normally, ■cc is the ground potential.

A holding current I)1 determined by the base voltage (I)8 and the resistor R always flows between the memory cells.

Conventionally, the following three methods have been used to detect defective cells whose write characteristics are unstable due to the large leakage current of the memory cell under test.

(1) After a data digit signal is written under normal voltage conditions, it is held for a long time of 300 to 500 μs, and then the cell data is read out to check whether it has been held.

(2) Forcibly applying an external potential to the base voltage vn of the constant current transistor that sets the holding current of the memory cell,
For example, from 1.2V to 1. There is also a method of reducing the holding current by switching to OV and detecting a memory cell that is insufficiently holding data, that is, is inverted, as a defective cell.

(3) After performing normal data writing, reduce the voltage of the circuit power supply and, for example, in the case of a PNP load cell, reduce the holding current of the memory cell by switching from several tens of μA to several μA, and detect the data inversion cell. do.

[Problems to be Solved by the Invention] In the conventional semiconductor device testing method described above, in the first case, a normal holding current is flowing, so in order to detect cells with poor holding, several hundred This method requires a holding state for a long time of μs, and has the disadvantage that it takes an excessively long time to test all ICs on a wafer, which is several tens of seconds.

In the second case, regarding the packaged product,
The drawback was that it was extremely difficult to apply an internal potential from the outside.

Furthermore, in the third case, since the ability to retain data when the power supply voltage is reduced varies depending on the product, it is difficult to optimally determine the reduced voltage value to distinguish between good cells and defective cells. .

For example, if the settings are too strict, there is a risk that even good cells will be regarded as defective cells.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for testing a semiconductor memory device that requires a short test time and can reliably detect the data retention characteristics of a memory cell.

[Means to solve the problem]

The method for testing a semiconductor memory device of the present invention involves testing the write state by supplying a power supply voltage to a plurality of memory cells under test that are connected to a word line, a digit line, and a holding current circuit to hold write data. In a test method for semiconductor memory devices, after writing a digit signal with a normal pulse width,
The value of the holding current is set to be reduced to near the lower limit value of the holding current distribution of the same manufacturing rod as the memory cell under test by reducing the power supply voltage, and the digit signal is inverted, and then the width of the write pulse is set. is set to a shorter time than the normal pulse width, and then detects whether or not the inverted data is written in the memory cell under test.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a third diagram for explaining the operation of one embodiment of the present invention.
FIG. 2 is a timing diagram of signals of each part of the circuit shown in the figure, and FIG. 2 is a voltage waveform diagram of nodes A and B of the circuit of FIG.

As shown in FIG. 1, while the high voltage VCC remains unchanged at the ground potential, the low voltages V and P are first set to the normal -4 and 5 V, and the memory cell under test MIj is controlled by the address signal Sll. At time t1, data signal Sd is applied to digit lines and as digit signals SO and Sτ during a normal write time TwP of 1 Qns of write pulse WE.

Next, with the high potential voltage VCC unchanged, the low potential voltage VER is switched to -3.5V at time t2 to reduce the power supply voltage, and the holding current IH is reduced from 15 μA to a value close to the lower limit value of the holding current distribution of the memory cell MIJ. For example, the reduction is set to about 0.5 μA.

Next, at time t3, the data signal S is inverted, and then the shortest write time T is shorter than 3 ns, which is the minimum pulse width that can be written normally. Write pulse WE of wp2.5ns at time t
Supply from 4.

As shown by the solid line in Figure 2, in the case of a good memory cell, the voltages ■ and ■8 at nodes A and B are stable with a potential difference of about 0.5 V before time t4, so they are not affected to some extent. However, it does not reverse.

As shown by the dotted line, in the case of a defective memory cell with leakage current, etc., the potential difference between the node voltages Va and Vb before time t4 is small and unstable, resulting in high sensitivity, and the shortest write time T nwp is shorter than normal. It reverses at point P during 2.5 rl S.

Therefore, a memory cell in which inverted data is detected can be determined to be a defective cell with large leakage current and unstable data retention.
Moreover, the test time is only several tens of microseconds per cell.

〔Effect of the invention〕

As explained above, the present invention is capable of inverting a memory cell with unstable data retention characteristics by inputting a reverse digit signal of such a short period that normally writing is impossible while the retention current is reduced. Therefore, defective cells can be detected reliably, and the test time can be reduced to about one-tenth of the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a third diagram for explaining the operation of one embodiment of the present invention.
FIG. 2 is a timing diagram of signals of various parts of the circuit shown in the figure, FIG. 2 is a voltage waveform diagram at nodes A and B of the circuit of FIG. 3, and FIG. 3 is a circuit diagram of an example of a semiconductor memory device under test. D, ,D, . . . digit line, 1. ...Holding current,
MIJ...memory cell in the i-th row and j-th column, Ql...constant current transistor in the i-th row, So...digit signal, T wp...normal write time, Tnwp...shortest write time write time, VCC...high voltage, VCC...local voltage, wg...write pulse, WI...word line of i-th row, to...voltage switching time, VA, V,...・A node voltage, VB, Vb...8 node voltage.

Claims (1)

[Claims] In a semiconductor memory device test method that tests the write state by supplying power supply voltage to multiple memory cells under test that connect to word lines, digit lines, and holding current circuits and hold write data, a normal pulse After writing the digit signal of the width, the power supply voltage is reduced to set the value of the holding current to near the lower limit value of the holding current distribution of the rod manufactured in the same manner as the memory cell under test, and the digit signal is inverted. , Next, the width of the write pulse is set to be shorter than the normal pulse width, and then the presence or absence of writing of the inverted data in the memory cell under test is detected. Method.