JPH03278399A - Testing method for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a test method for a semiconductor device capable of detecting a defective cell by performing write simultaneously with the switching of a word line after setting the width of a write pulse less than ordinary pulse width, and detecting the presence/absence of write of inversion data in a memory cell to be tested. CONSTITUTION:When the memory cell is a good product, potential difference of around 0.4V exists between the potential VA and VB of nodes A and B at a time t5 even when an inverse write signal is supplied, and it is stably operated, therefore, no inversion occurs through influence to some extent is given. When the memory cell is a defective one in which leakage current, etc., occurs, the potential difference between the potential Va and Vb is small even before the time t5, and the potential difference goes down further after the time t5, there fore, a more unstable state is generated, and the inversion occurs at a point P during the minimum write time less than ordinary write time. In such a way, it is possible to obtain the testing method for a semiconductor memory device in which the defective cell can be surely detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing a semiconductor memory device, and more particularly to a method for testing a static memory.

[Prior Art] Generally, a static memory uses a flip-flop circuit of a transistor as a load cell such as a bipolar transistor or a Schottky barrier diode as a memory cell, and is connected to a circuit power supply via a constant current circuit.

FIG. 4 is a circuit diagram of an example of a semiconductor memory device under test.

The memory cell MIJ in the i-th row and J-th column to be tested is PNP.
It is a transistor load type, and is inserted between the i-th transistor Q and word line Wl and the i-th constant current transistor Q1, and a pair of emitters are connected to the 5th column digit line DJ and R, respectively. . A circuit power supply is commonly connected to all memory cells between the terminals of the highest potential voltage VCC and the lowest potential voltage VEE. Normally, VCC
is the ground potential. A holding current I8 determined by the base potential (2) and the resistor Rc always flows through the memory cell M1.

Conventionally, the following methods have been used to detect defective cells with unstable write characteristics due to large leakage current in memory cells under test. To explain using figures, FIG. 5 is a timing diagram of signals of each part of the circuit of FIG. 4 to explain the operation of the conventional example, and FIG. 6 is a voltage waveform diagram of nodes A and B of the circuit of FIG. 4. It is.

As shown in FIG. 5, the highest potential voltage V. C remains unchanged at the ground point potential, and the lowest potential voltage v0 is first set to the normal -4,
5V, select the memory cell under test MIJ with the address signal SIJ, and send the data signal S at time t11.
The normal write time Twp (I
0 ns), the data write signal plane and WC are supplied to the digit line and the island.

Next, leave the highest potential voltage VCC as it is at time t1□
Then, Vo is switched to -3.6 V to lower the power supply voltage, and the holding current IH is set from, for example, 15 μA to about 05 μ8, which is below the lower limit of the distribution of the holding current of the memory cell M1.

Next, at time L's, the data write signals WC and WC are inverted, and then the normal writeable minimum pulse width of 6n
The shortest writing time T is shorter than s. 1 (e.g. 5 ns)
A write pulse WE is supplied from time t4.

As shown by the solid line in FIG. 6, in the case of a good memory cell, the potentials VIA * VIB at nodes A and B are at time t14.
Previously, there was a potential difference of about 0.5V and it was stable, so although it would be affected to some extent, it would not reverse.

As shown by the dotted line, in the case of a defective memory cell with leakage current, etc., before time 1+<, the node potentials Vl11 and V
The potential difference at l is small and unstable, resulting in high sensitivity, and is reversed at point PI during the shortest write time T, which is 5 ns, which is shorter than usual.

Therefore, a memory cell in which inverted data is detected can be determined to be a defective cell with large leakage current and unstable data retention, and the test time can be a few μs per cell.

[Problems to be Solved by the Invention] The drawbacks of the conventional semiconductor device testing method described above will be explained with reference to the drawings. Figure 7 shows (7) W when switching the word line.
Ll+11 Tort=L0) Nodes A, B (7) A waveform diagram of potentials VA, VB is shown. In the conventional test method, the memory cell is completely selected, at time t in the figure.
12 and later uses a method of writing reverse data.

However, during the operation of the circuit, especially at the time t when the word line switches
Between el and t2□, the potentials v,, ve are in a transient state, and the potential difference ■, is smaller than when completely selected.

As described above, the conventional testing method has the drawback that a defective cell to the extent that the margin between vA and (2) disappears during the transition of cell selection cannot be detected.

An object of the present invention is to provide a semiconductor device testing method capable of detecting defective cells in which the margin between (1)6 and (6) disappears during cell selection transition.

[Means for Solving the Problems] A semiconductor memory device testing method of the present invention applies a power supply voltage to a plurality of memory cells under test that are connected to a word line, a digit line, and a holding current circuit to hold write data. A test method for a semiconductor memory device in which a write state is tested by supplying a data write signal with a normal pulse width, the power supply voltage is lowered, and the value of the holding current is set to the value of the memory cell under test. Set to below the lower limit value of the holding current distribution of the same manufactured rod, then invert the data write signal, set the write pulse width to a shorter time than the normal pulse width, and then switch the word line. At the same time, writing is performed to detect whether or not the inverted data has been written in the memory cell under test.

[Function] In the case of a good memory cell, there is a potential difference of about 0.4 V even if a reverse write signal is supplied at the time of word line switching, and the potentials ■ and vI are stable, so this will not be affected to some extent. In the case of a defective memory cell that does not invert, but has leakage current, etc., the potential difference between potentials V and ■ is small even before the word line is switched, and the potential difference becomes even smaller after the word line is switched. It becomes increasingly unstable and reverses during a shorter than normal write time.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

1 is a timing diagram of various signals in the circuit of FIG. 4 for explaining the operation of an embodiment of the present invention, and FIG. 2 is a timing diagram of nodes A, B and word lines of the circuit of FIG. 4, W++ or,)
FIG.

As shown in Figure 1, the highest potential voltage VCC remains unchanged at the ground potential, and the lowest potential voltage
2, select the memory cell under test MIJ with the address signal SIJ, and use the data signal S6 as the data write signals WC and WC from time t1 to the normal write time T, p (10 ns) of the write pulse WE. digit line, and supply to the island. After writing, at time t2, the address signal SIJ is switched to change the selected word line from one end Wl to W++. Switch to I. Next, VEE is switched to -3.6V at time t3 while leaving VCC unchanged to lower the power supply voltage, resulting in a holding current (■). For example, from 1.5μA to 05μA below the lower limit of the distribution of the holding current of the memory cell MIJ.
Set to a certain degree. Next, at time t4, the data signal S is inverted, and at the same time, the selected word line is again switched from WN, etc. to wl using the address signal SIJ. This LL
The shortest write time T is shorter than 6 ns, which is the minimum pulse width that can normally be written, from the time point ts at which wI and wI switch. write pulse WE of wp (e.g. 5 ns)
supply.

As shown in FIG. 2, a write pulse of Tnwp is supplied at time t when the word lines W1 and WN+11 are switched, but in the case of a good memory cell, the potentials of nodes A and B are
and ■, even if a reverse write signal is supplied at time t, there is a potential difference of about 0.4 V and it is stable, so it will be affected to some extent but will not be reversed. However, as shown by the dotted line, in the case of a defective memory cell with leakage current, etc., the potential difference between the node potentials v1 and ■ is small even before time t, and even more so at time t and after when one word line is switched. becomes smaller, resulting in an increasingly unstable state, and is reversed at point P during the shortest writing time Tnwp (5 ns), which is shorter than normal.

FIG. 3 is a timing chart of signals of each part of the circuit of FIG. 4 for explaining the operation of the second embodiment of the present invention.

In this embodiment, the width of one write pulse is jwp and t,
The address signal and data signal are switched within the pulse. The effect on the internal levels V- and Vb of the defective cell is the same as in the first embodiment, but since only one write pulse and one address switch are required, the test time is halved compared to the first embodiment. It has the advantage of being shortened to

[Effects of the Invention] As explained above, the present invention has the advantage of inputting a reverse data write signal of such a short period that it is impossible to write to a normal cell at the same time as the word line is switched in a state where the holding current is reduced. By inverting the data of cells with unstable data retention characteristics during operation, defective cells can be reliably detected and the test time can be reduced to several microseconds per cell.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram of signals of each part of the circuit of FIG. 4, which is used to explain the operation of the first embodiment of the present invention, and FIG.
Nodes A, B and W, , W, of the present invention in the circuit shown in the figure. 1
FIG. 4 is a circuit diagram of an example of a semiconductor memory device under test, and FIG. 3 is a timing diagram of a second embodiment. 5 is a timing diagram of signals of various parts of the circuit of FIG. 4 to explain the operation of the conventional example, FIG. 6 is a voltage waveform diagram of the conventional node AB of the circuit of FIG. 4, and FIG. 7 is a beam, L4+ and node A
It is a voltage waveform diagram of B.

Claims (1)

[Claims] 1. Testing the write state by supplying a power supply voltage to a plurality of memory cells under test that are connected to a word line, a digit line, and a holding current circuit and hold write data;
A test method for a semiconductor memory device, wherein after writing with a data write signal of a normal pulse width, the power supply voltage is lowered and the value of the holding current is set to the lower limit of the holding current distribution of the same manufacturing rod as the memory cell under test. Then, the data write signal is inverted, the width of the write pulse is set to be shorter than the normal pulse width, and writing is performed simultaneously with the switching of the word line, and then the data write signal is A method for testing a semiconductor memory device, which detects whether or not the inverted data is written in a test memory cell.