JPH0266679A - Field memory - Google Patents

Abstract

PURPOSE:To allow each block which is divided in the line direction to have a different delay quantity by using that which consists of one set of data transfer address generating counter, an arithmetic circuit and a data transfer address distributing circuit, as a data transfer address generating circuit. CONSTITUTION:A data transfer address corresponding to a data transfer object line of a memory cell array at the time of executing a data transfer is outputted from an arithmetic circuit 117, and said address is generated by adding '0' to a counter value of a write data transfer address generating counter 114 at the time of transferring write data, and adding 4, 4 and 3, when a serial read line is in an (A) blocking, at the time of (B) blocking and at the time of (C) blocking, respectively to the counter value of the write data transfer address generating counter 114 at the time of transferring read-out data. Also, it is transferred to line selectors 107, 108 or 109 through a data transfer address distributing circuit 113, and the only line that becomes on object of the data transfer is activated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field memory used for storing television image signal data.

[Conventional technology]

The conventional technology will be explained using FIG. 3, FIG. 4, and FIG. 5.

Conventional synchronous field memories can be used as a delay line for the memory capacity by simultaneously writing and reading data in synchronization with a serial clock.

Figure 3 is a block diagram of a conventional field memory.
5 is a memory cell array for storing data; 1 and 2 are for taking in and storing data corresponding to the dividing line from the outside;
10.11 is a read data register that receives and stores the divided line data stored in the memory cell array in a batch transfer, and outputs it to the outside; 14 is a write data register; A write data transfer address generation counter that generates an address corresponding to the data transfer target line of the memory cell array when data is transferred in bulk between the memory cell arrays, and 15 is a counter for generating a write data transfer address when data is transferred in bulk between the read data register and the memory cell array. 7.8 is a line selector that activates the data transfer target line of the memory cell array when data is transferred in bulk. 13 is a plurality of data transfer addresses. A data transfer address selection and distribution circuit selects the counter value output from the generation counter (14.degree. 15) and distributes it to the line selector 7.8; 16 is a write data register;

This is a controller that controls the read data register, the data transfer address generation counter, and the data transfer address selection and distribution circuit.

The operation of this field memory will be explained using FIG.

FIG. 4 is a timing diagram for explaining the operation of this field memory. In the figure, the serial write line is the line to be written when writing data to the field memory, CLK is the serial clock, and Din is the line for writing data to the field memory. The data string, Dout is the data string of data read from the field memory, the WDT counter is the content of the write data transfer address generation counter 14, the RDT counter is the content of the read data transfer address generation counter 15, and the WDT counter is the write data transfer address. The contents of the raw counter 14, the RDT counter is the counter 1 for reading and output data transfer address generation.
5, WDT indicates the execution timing of write data transfer, and RDT indicates the execution timing of read data transfer.

When the CLK, D in and D out portions are enlarged, they look like FIG. 5. Further, K(A) is shown in the portions of Din and Dout in FIG.

K+1 (B), etc. indicate the line (block) of the cell array where the data string is to be stored, and K (A), K+1 (B), etc. shown in the WDT and RDT portions indicate the data transfer target line (block) of the cell array. ) is shown.

(Blocks are blocks (A) and (B) that are divided into data registers, cell arrays, etc.) This field memory write and read operation is
The description will be made using the +2 portion of either the serial write line or the serial read line in the figure.

As a write operation, first, the data input to the data terminal Din (indicated by K (A) of Din) is sent to the write data register (indicated by K (A) of Din) in synchronization with the serial clock CLK.
A) (here, this operation is called serial write). When the write data register (A) is full of input data, continue writing to the write data register (B).
Serial write to (DinL7) K (B))
. At this time, the write data register (A) is full.
All data of the memory cell array (A) is transferred to the line of the memory cell array (A) at once (indicated by K (A) of the WDT).

As serial writing continues further, the write data register (B) becomes full. When it is full, select Din to transfer the serial write to the write data register (A).
(represented by +1 (A)), all the data in the full write data register (B) is transferred all at once to the line of the memory cell array (B) (represented by K (B) of the WDT).

For read operation, read data register (A)
data is output from the data output terminal in synchronization with the serial clock CLK. Here, this operation is called a serial read (indicated by +2 (A) in Dout: the data in the +2 line of the memory cell array (A) has already been read and transferred to the data register (A)). During a serial read of +2 (A) to this data string, read data transfer of +2 (B) to the next data string to be read (read all the data of +2 lines to the memory cell array (B) and - to the data register (B)) Perform bulk transfer) (indicated by +2 (B) on RDT).

8. When the serial read of the selling data register (A) is completed, the process continues to the serial read of the read data register (B) (indicated by +2 (B) in Dout). During a serial read of +2 (B) to this data string, read data transfer of +3 (A) to the next data string to be read (read all the data on the K +3 line of the memory cell array (A) and transfer it to the data register (A) - Batch transfer) (RDT +3 (indicated by
Perform this after the WDT in B) is completed).

As the data transfer address corresponding to the data transfer target line of the memory cell array when performing these data transfers, the counter value of the write data transfer address generation counter 14 is used during write data transfer, and the read data transfer address is used during read data transfer. The counter value of the data transfer address generation counter 15 is used. In other words, when transferring write data, the counter value of the write data transfer address generation counter 14 is set, and when transferring read data, the counter value of the read data transfer address generation counter 15 is sent to the line via the data transfer address selection distribution circuit 13. The data is transferred to selector 7 or 8, and the only line targeted for data transfer is activated. These controls are performed by the controller 16.

As described above, serial write/read and write/read data transfer are performed alternately and continuously to realize uninterrupted serial access.

Further, in the operation diagram shown in FIG. 4, the serial read line precedes the serial write line by two lines (writing to the line of the field memory and reading from the +2 line are performed at the same time).

As a result, if the number of lines of this field memory is N lines (indicated by 1 to N in the figure), it will operate as a delay line for N-2 lines. In other words, N in the membrane.
When there is a line field memory and the serial read line is ahead of the serial write line by R line,
The field memory becomes the delay line of the NR line.

[Problem to be solved by the invention]

The conventional field memory described above has two data transfer address generation counters, one for write data transfer and one for read data transfer, and the counter value is used as is as the address used during data transfer. , the serial read line is uniquely determined according to the operation of the counter (counter value), and when this field memory is used as a delay line, all pixels in one line (individual pixels making up each line of the field memory) Therefore, each block divided in the line direction cannot have a different delay amount.

(2) Periodically synchronize the two counters in case one or both of the two counters malfunctions due to noise coming from outside the field memory via the power supply, ground, etc. It is necessary to take measures such as taking appropriate measures.

There is a drawback.

In high-definition television systems that use communication satellites that are currently under development, it is necessary to use different amounts of delay for each line or divided line, but conventional systems have not been able to accommodate this type of use. Can not.

An object of the present invention is to provide a field memory that can vary the amount of delay for each line or divided line.

[Means to solve the problem]

The field memory of the present invention includes a memory cell array that stores data, and a write data register that takes in data corresponding to one line or divided lines of the memory cell array from the outside, stores it, and transfers it all at once to the memory cell array. , receiving data for one line or divided lines accumulated in the memory cell array in a batch transfer;
a plurality of blocks each comprising a set of read data registers for storing and outputting to the outside, line selectors for activating lines to be transferred of data in the memory cell array when transferring the data in a batch; and a counter for generating a write data transfer address; Data transfer comprising an arithmetic circuit that adds a predetermined value to the contents of the write data transfer address generation counter, and a data transfer address distribution circuit that supplies the contents of the arithmetic circuit to each line selector as the address of the data transfer target line. The controller includes an address generation circuit and a controller that controls each of the blocks and the data transfer address generation circuit, and sequentially transfers data to each of the memory cell arrays in a batch, and transfers data to each of the memory cell arrays with a predetermined delay amount. The data is sequentially output in batch transfer from the beginning.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
, 105, 10.6 are memory cell arrays that store data; 101, 102, and 103 are write registers that take in data corresponding to the dividing line from the outside into the memory cell array, store it, and transfer it all at once to the memory cell array; 110, 111, and 112 are read data registers that receive, store, and output the divided line data accumulated in the memory cell array in a batch transfer, and 114 is a read data register that is used to transfer data in batches between the write data register and the memory cell array. A write data transfer address generation counter that generates an address corresponding to the data transfer target line of the memory cell array. 115 is an operation that adds the value output from the write data transfer address generation counter and the added value output from the controller. circuit, 107.1
08, 109 is a line selector that activates the data transfer target line of the memory cell array when data is transferred in bulk, 1
13 is a data transfer address distribution circuit that distributes the operation result (data transfer address) output from the arithmetic circuit to the line selector; 116 is a write data register, a read data register, a counter for generating a write data transfer address, an arithmetic circuit, and a data transfer circuit; This is a controller that controls the address distribution circuit.

The memory cell arrays 104, 105, 106, write data registers 101, 102, 103, and read data registers 110, 111, 112 are each divided into O pixels, P pixels, and Q pixels in the line direction. Each division unit is block (A), block (B)
Let it be block (C).

The operation of this embodiment will be explained using FIG. 2.

Figure 2 is a timing diagram to explain the operation of this field memory. The serial write line in the figure is the line to be written when writing data to the field memory.
The serial read line is the line to be read when reading data from the field memory, CLK is the serial clock, Din is the data string of data to be written to the field memory, D out is the data string of data to be read from the field memory, and the WDT counter is the write line. The contents of the data transfer address generation counter value 114, the operand is the addition value that is added to the output value of the write data transfer address generation counter 114 to generate the data transfer address used during write/read data transfer, and the WDT is Write data transfer execution timing, R
DT indicates the execution timing of read data transfer.

The CLK, Din, and Dout portions are shown in FIG. 5 when enlarged. In addition, K (A), +1 (B), etc. shown in the DinDout part in FIG. ■gu (A)
, +1 (B) indicates a line (block) to which data is transferred in the cell array.

This field memory write and read operation is
Serial write line or serial read line in the figure +2. +3. This will be explained using the +4 part.

As a write operation, first, the data (DinL near) input to the data input terminal Din (indicated by K(A)) is input to the write data register (A) in synchronization with the serial clock CLK (here, this operation is referred to as serial write). ). When the write data register (A) is full of input data, continue writing to the write data register (B).
) (indicated by DIN K (B))
.

At this time, the full write data register (A) is transferred all at once to the line (indicated by K(A) of the WDT).

As serial writing continues further, the write data register (B) becomes full. When it is full, select Din to transfer the serial write to the write data register (C).
When the write data register (B) is full, all data in the write data register (B) is transferred to the line of the memory cell array (B) at once (represented by K (B) in the WDT).

As serial writing continues further, the write data register (C) becomes full. When it is full, select Din to transfer the serial write to the write data register (A).
(displayed as +1 (A)), all data in the full write data register (C) is transferred to the memory cell array (C).
(Displayed by K (C) in WDT)
.

For read operation, read data register (A)
data is output from the data output terminal in synchronization with the serial clock CLK. Here, this operation is called a serial read (displayed as +2 (A) in Dout: the data in the +2 line of the cell array (A>) has already been read and transferred to the data register (A)).
During the serial read of 2 (A), +3 (B) read data transfer to the next data string to be read (memory cell (B)
However, read out all the data on the +3 line and store it in the data register (
(B) - Batch transfer) (+3 to RDT (B)
).

When the serial read of the read data register (A) is completed, it continues to the serial read of the read data register (B) (K + 3'(B of Dout)
). During the serial read of this data string K+3 (B), read data transfer of +4 (C) to the next data string to be read (all data of +4 lines is read from the memory cell (C) and is transferred to the data register (C) - Perform bulk transfer) (indicated by +4 (C) on RDT).

When the serial read of the read data register (B) is completed, the process continues to the serial read of the read data register (C) (indicated by +4 (C) in Dout). During a serial read of +4 (C) to this data string, read data transfer of +3 (A) to the next data string to be read (all the data of the K + 3 line of the memory cell (A) is combined with the read data (A)). Transfer) (RD
+3 (indicated by A)). However, these read data transfers are performed after the write data transfer is completed (for example, the RDT of K+3 (B) is performed after the WDT of -1 (C) is completed).

When performing these data transfers, the data transfer address corresponding to the data transfer target line of the memory cell array is output from the arithmetic circuit 115, but during write data transfer, the counter value of the write data transfer address generation counter 114 is During read data transfer, the counter value of the write data transfer address generation counter 114 is 4 degrees when the serial read line is in (A) block and 4 degrees when in (B) block. (C) When blocking, generate by adding 3. (Here, the addition value is 4.4.3 because the number of lines preceding the serial write line of the serial read line of each block is (A), and the block is 2. (B)
This is because the block is 3° (C) and the block is 4. ) In other words, in both write data transfer and read data transfer, the counter value of the write data transfer address generation counter 114 and the added value output from the controller 116 are added together in the arithmetic circuit 115, and the data transfer address distribution circuit 113 The data is transferred to the line selector 107°1, 08, or 109 via the line selector 107, and the only line targeted for data transfer is activated. These con 1
~The controller 116 performs the roll.

As described above, serial write/read and write/read data transfer are performed alternately and continuously to realize uninterrupted serial access.

In addition, in the timing diagram of Fig. 2, each block ((A)
The serial read line of the block is the first O pixel, (B) block is the following P pixel, (C) block is the last Q pixel), and the serial read line is 2 lines, 3 lines, and 4 lines ahead of the serial read line, respectively. 12 lines in block (A) and +3 lines in block (B).

(C) Block is simultaneously reading from +4 lines). As a result, if the number of lines of this field memory is N lines (indicated by 1 to N in the figure), each block operates as a delay line for N-2, N-3, and N-4 lines, respectively. Become.

In other words, generally speaking, in a field memory with N lines in which the data register and memory cell array are divided into three in the line direction, if the serial read line of each block is advanced from the serial write line by R, S, and T lines, The first 0 pixel of the field memory has a delay amount of NR lines, the following P pixels have a delay amount of NS lines, and the last Q pixel has a delay amount of NT lines.

〔Effect of the invention〕

As explained above, the present invention provides a write data register,
The read data register and memory cell array are divided in the line direction into multiple pixels with the same amount of delay, and the data transfer address generation circuit includes one data transfer address generation counter, an arithmetic circuit, and data transfer address distribution. By using circuits, (1) each block divided in the line direction can have a different amount of delay.

(2) It can fundamentally solve the problem caused by noise coming from outside the field memory via the power supply, ground, etc. when there are multiple counters (this problem occurs because there is only one counter) There is no room).

There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional field memory.
FIG. 4 is a timing diagram for explaining the operation of a conventional field memory, and FIG. 5 is a timing diagram for explaining the operation of a conventional field memory.
FIG. 3 is a timing diagram showing details of in and Dout. Second
．． The serial write line in Figure 4 is the line to be written when writing data to the field memory, the serial read line is the line to be read when reading data from the field memory, and the serial read line is the line to be read when reading data from the field memory. The target line, CLK is the serial clock, Din is the data string of data to be written to the field memory, Dout is the data string of data to be read from the field memory, WDT counter is the counter value for generating the write data transfer address, and the operand is the write/read data transfer. R
DT counter indicates the contents of a read data transfer address generation counter, WDT indicates execution timing of write data transfer, and RDT indicates execution timing of read data transfer. In addition, K (A), +1 (B), etc. shown in the Din and Dout portions in FIGS. 2 and 4 indicate lines (blocks) of the memory cell array in which data strings are to be stored, and , K (A) shown in the RDT part,
, +1 (B), etc. indicate lines (blocks) to which data is transferred in the memory cell array. 1.101, 2, 102, 103...Write register, 4,104,5,105,106...Memory cell array, 7,107,8,108°109...Line selector, 10,110, 11゜111.1.12...
- Read data register, 13... Data transfer address selection distribution circuit, 113... Data transfer address distribution circuit, 14, 114... Counter for generating write data transfer address, 15... For generating read data transfer address Counter, 16.116...Controller, 117...Arithmetic circuit.

Claims (1)

[Claims] A memory cell array that stores data; a write data register that takes in data corresponding to one line or divided lines of the memory cell array from the outside, stores it, and transfers it all at once to the memory cell array; and a write data register that stores data in the memory cell array. a read data register that receives data for one line or divided lines in a batch transfer, stores it, and outputs it to the outside; and a line selector that activates a line to which data is transferred in the memory cell array when transferring the data in batches. a write data transfer address generation counter, an arithmetic circuit that adds a predetermined value to the contents of the write data transfer address generation counter, and a calculation circuit that adds the contents of the arithmetic circuit to the address of the data transfer target line. a data transfer address generation circuit consisting of a data transfer address distribution circuit that supplies data to each line selector, and a controller that controls each block and the data transfer address generation circuit, and sequentially supplies data to each memory cell array. What is claimed is: 1. A field memory characterized in that data is transferred in batches, and data is sequentially outputted from each memory cell array in batch transfer with a predetermined amount of delay.