JP2001142775A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor by which a high data transfer rate and the efficient usage of a memory are realized even when a variety of picture formats are adopted. SOLUTION: The processor is provided with a main memory 20 for storing frame data when a plurality kind of frame data with different data length in pixel data by format are processed and is provided with a processing element 343 and a memory control circuit 341, by which the transmission pattern of pixel data is decided to transmit pixel data by using the whole data widths of internal buses 347 and 348 even when data with any kind of format are processed in the case of performing access to the main memory 20 via the internal buses 347 and 348 and by which at least one kind of pixel data are divided as necessary and transmitted by different timings via the internal buses 347 and 348.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device with memory access.

[0002]

2. Description of the Related Art Conventionally, a system LSI (Large Scale) has been used.
Integration) processor, controller,
Image processing is performed using a data processing device such as a DSP (Digital Signal Processor). Further, an image processing apparatus used in a system capable of supporting both displays of a consumer television and a computer is required to handle image data of various formats.

[0003]

However, in the above-described data processing apparatus, since the amount of image data to be handled is enormous, access between the data processing apparatus and a system memory (main memory) is not possible. There is a problem that a sufficient data width (bandwidth) cannot be secured.
In particular, the bandwidth problem described above is serious in an online system used for image communication or broadcasting where real-time processing is required, or in an image processing device used for a system in which the time of a synchronous system is determined. It is a bottleneck in improving performance.

In an image processing apparatus that handles image data of various formats as described above, if hardware corresponding to each format is individually designed,
There is a problem that the system becomes larger. Further, the storage format of image data in the system memory that stores data processed by the image processing device is various,
Since the bandwidth of access to the system memory is fixed, there is a problem that memory access using a sufficient bandwidth cannot be performed depending on an image format, and sufficient performance cannot be obtained.

For example, as shown in FIG. 11, consider a case where the bandwidth of access to the system memory is 64 bits, and pixel data of one pixel handles image data of a 24-bit format. Conventionally, the system memory is accessed in units of 48-bit image data composed of two pieces of pixel data, and stored in the system memory in units of the 48-bit image data. However, in the case shown in FIG. 11, valid data 150 is stored in only 48 bits out of 64 bits in each row of the storage area in the system memory, and invalid data 151 is stored in the remaining 16 bits. You. Therefore, there is a problem that the use efficiency of the system memory is reduced, and an unnecessarily large capacity of the system memory is required. Also, in the data transfer between the system memory and the image processing apparatus, since only 48 bits of valid data are transferred in spite of the 64 bits of bandwidth, when data valid for all of the 64 bits of bandwidth is transferred. In this case, the number of times of data transfer increases, and it is difficult to improve the access speed to the system memory.

For example, one frame widely used in the field of computers is 1024 pixels (horizontal) × 768.
In image data that displays pixels (vertical) and employs an XGA (eXtended Graphics Array) format in which one pixel data is 24 bits, the data amount of one horizontal line is 24576 bits (= 24 bits × 1024).
Pixels). When such image data of the XGA format is stored in the system memory by the data transfer of a 64-bit bandwidth in the method shown in FIG. 11, the image data is transferred 512 times (= 24576/48) in the system memory. The data is written to the storage area of 512 rows. However, image data of 24576 bits for one frame in the XGA format is, for example,
If all of the 64-bit bandwidth is used effectively,
By 384 data transfers, 38
The data can be stored in four rows of storage areas. In the above-described example, the data transfer rate is lower by about 33% and the storage area is about 1.3 times higher than in this case. The above-described problem occurs in a data processing device that handles data of a plurality of formats, which is data including a plurality of modules having a predetermined data length and differs in the predetermined data length depending on a format, in addition to a data processing device that handles image data. Occurs similarly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has a data processing apparatus capable of realizing a high data transfer rate and efficiently using a storage area of a memory even when various image formats are adopted. The purpose is to provide. Further, the present invention can realize a high data transfer rate even when handling data of a plurality of formats having a plurality of modules having a predetermined data length and having the predetermined data length different depending on the format, and furthermore, can realize a high data transfer rate. An object of the present invention is to provide a data processing device capable of efficiently using a storage area.

[0008]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a data processing apparatus according to a first aspect of the present invention comprises a plurality of modules each having a predetermined data length. A data processing device that handles data of a plurality of formats, wherein the predetermined data length is different depending on the format, comprising: a storage circuit, a data transmission path, and accessing the storage circuit via the data transmission path. When performing the data of any one of the plurality of formats, the transmission pattern of the plurality of modules is determined so that the data is transmitted using the entire data width of the data transmission path. And a control circuit that divides at least one of the modules according to the timing and transmits the divided modules via the data transmission path at different timings.

The operation of the data processing apparatus according to the first aspect of the present invention is as follows. For example, when the data width of the data transmission path can be completely used by one or more modules without dividing the module, the transmission of the data can be performed in units of the one or more modules under the control of the control circuit. Access is made to the storage circuit via the path. When it is necessary to divide at least one module in order to perform transmission using the entire data width of the data transmission path, at least one module is divided under the control of the control circuit, and obtained by the division. The storage circuit is accessed via the data transmission path by using the entire data width of the data transmission path in units of a combination of the module and the other single or plural modules as necessary. In this case, access to the storage circuit for a plurality of data obtained by dividing one module is performed via data transmission paths at different timings under the control of the control circuit. Thus, by accessing the storage circuit using the entire data width of the data transmission path, the data transfer rate when accessing the storage circuit can be increased.

[0010] A data processing apparatus according to a first aspect of the present invention comprises:
Preferably, the data width of the data transmission path is the same as the data width of the storage circuit.

Further, in the data processing apparatus according to the first aspect of the present invention, preferably, the control circuit performs an access to the storage circuit by a burst having the data in a DRAM via the data transmission path. This is performed using the transfer mode.

Further, a data processing apparatus according to a second aspect of the present invention is a data processing apparatus comprising: a plurality of frame data comprising a plurality of pixel data having a predetermined data length; Or a data processing device that handles field data, a storage circuit that stores the frame data or field data, a data transmission path, and when accessing the storage circuit via the data transmission path, Regardless of the data format,
The transmission pattern of the plurality of pixel data is determined so that the pixel data is transmitted using the entire data width of the data transmission path, and at least one of the pixel data is divided at different timings as necessary. And a control circuit for transmitting the data via a data transmission path.

The operation of the data processing device according to the second aspect of the present invention is as follows. For example, if the data width of the data transmission path can be completely used by the single or multiple pixel data without dividing the pixel data, the single or multiple pixel data can be unitized by the control of the control circuit. And the storage circuit is accessed via the data transmission path. Also, when it is necessary to divide at least one pixel data in order to perform transmission using the entire data width of the data transmission path,
Under the control of the control circuit, at least one pixel data is divided, and in a unit obtained by combining the pixel data obtained by the division and other single or plural pixel data as necessary, via the data transmission path. The storage circuit is accessed using the entire data width of the data transmission path. In this case, access to the storage circuit for a plurality of data obtained by dividing one pixel data is performed via the data transmission path at different timings under the control of the control circuit.

Further, in the data processing apparatus according to the second aspect of the present invention, preferably, the control circuit stores the pixel data at the head of each line of an image corresponding to the frame data or the field data once. The data is stored in the storage circuit at address intervals corresponding to an integral multiple of the amount of data transferred by the burst transfer.

Preferably, the data processing apparatus according to the second aspect of the present invention, when reading out the pixel data of a partial area of an image corresponding to frame data or field data from the storage circuit, The circuit is
The pixel data of a plurality of lines including all of the partial area are sequentially read from the storage circuit and transmitted via the data transmission path.

In the data processing apparatus according to the second aspect of the present invention, preferably, the one or more of the pixel data of the plurality of lines read from the storage circuit input through the data transmission path are included. And a processing circuit for selecting and processing pixel data corresponding to the region of the section.

Further, a data processing apparatus according to a third aspect of the present invention is a data processing apparatus for handling data of a plurality of formats, each of which comprises a plurality of modules having a predetermined data length, wherein the predetermined data length differs depending on the format. A first storage circuit which stores the plurality of modules as a plurality of line data having a common data width, and reads out the stored line data in a writing order;
In the case of handling data in any of the plurality of formats, the line data containing the module is written into the first storage circuit so as to use up the entire data width of the line data, and at least one A processing circuit for dividing the module into different line data and writing the divided data into the first storage circuit, a data transmission path having the same data width as the first storage circuit, a second storage circuit, A storage control circuit for writing the line data read from the first storage circuit to the second storage circuit.

The operation of the data processing device according to the third aspect of the present invention is as follows. In the case where data of any one of a plurality of formats is handled by the processing circuit, the line data including the module is written into the first storage circuit so as to use up the entire data width of the line data, and if necessary, at least, One of the modules is divided into different line data and written into the first storage circuit. Then, under the control of the storage control circuit, the line data is read from the first storage circuit in the order of writing, and the read line data is written to the second storage circuit.

In a data processing apparatus according to a third aspect of the present invention, preferably, the second storage circuit has the same data width as the first storage circuit, and the storage control circuit includes the second storage circuit. The line data read from the first storage circuit is directly written to the second storage circuit via the data transmission path. By doing so, the storage area of the second storage circuit can be used efficiently, and the storage capacity required for the second storage circuit can be reduced.

Further, a data processing apparatus according to a fourth aspect of the present invention is a data processing apparatus, comprising: frame data or field data comprising a plurality of pixel data having a predetermined data length, wherein the predetermined data length is different depending on the format. A data processing device that handles frame data or field data, a first storage circuit that stores the plurality of pixel data as a plurality of line data having a common data width, and reads the stored line data in a writing order; When handling frame data or field data of any of the plurality of formats,
The line data containing the pixel data is written into the first storage circuit so as to use up the entire data width of the line data, and if necessary, at least one of the pixel data is divided into different line data. A processing circuit for inserting and writing into the first storage circuit; a data transmission path having the same data width as the first storage circuit; a second storage circuit; and the line data read from the first storage circuit To the second storage circuit.

The operation of the data processor according to the fourth aspect of the present invention is as follows. In the case where data of any of a plurality of formats is handled by the processing circuit, the line data containing the pixel data is written into the first storage circuit so as to use up the entire data width of the line data, and if necessary, At least one piece of the pixel data is divided into different pieces of line data and written into the first storage circuit. Then, under the control of the storage control circuit, the line data is read from the first storage circuit in the order of writing, and the read line data is written to the second storage circuit.

In a data processing apparatus according to a fourth aspect of the present invention, preferably, the second storage circuit has the same data width as the first storage circuit, and the storage control circuit includes the second storage circuit. The line data read from the first storage circuit is directly written to the second storage circuit via the data transmission path.

In the data processing apparatus according to a fourth aspect of the present invention, preferably, the storage control circuit stores the pixel data at the head of each line of an image corresponding to the frame data or the field data as 1 Data is written to the second storage circuit at address intervals corresponding to an integral multiple of the amount of data transferred by the burst transfer.

The data processing apparatus according to the fourth aspect of the present invention is preferably arranged such that the pixel data of a partial area of an image corresponding to frame data or field data is read from the second storage circuit. The storage control circuit sequentially reads out the pixel data of a plurality of lines including the entirety of the partial area from the second storage circuit and transmits the read data via the data transmission path.

In the data processing apparatus according to a fourth aspect of the present invention, it is preferable that the pixel data of the plurality of lines read from the second storage circuit input via the data transmission path be read. And a processing circuit for selecting and processing pixel data corresponding to the partial area.

A data processing apparatus according to a fifth aspect of the present invention is a data processing apparatus that handles frame data or field data composed of a plurality of pixel data each having a data length of 16 bits. A first storage circuit that stores a plurality of line data having a width and reads out the stored line data in a writing order, and a processing circuit that writes the line data including the four pieces of pixel data into the first storage circuit And a data transmission path having a data width of 64 bits, a second storage circuit, and the line data read out from the first storage circuit via the data transmission path as it is in the second storage circuit. And a storage control circuit for writing data to the memory.

A data processing apparatus according to a sixth aspect of the present invention is a data processing apparatus for handling frame data or field data composed of a plurality of pixel data each having a data length of 24 bits. A first storage circuit that stores a plurality of line data having a width and reads out the stored line data in the order of writing, and writes the line data containing 8/3 of the pixel data into the first storage circuit Processing circuit, 6
A data transmission path having a data width of 4 bits, a second storage circuit, and the line data read from the first storage circuit are written to the second storage circuit as it is via the data transmission path. A storage control circuit.

[0028]

FIG. 1 is a configuration diagram of a multiprocessor system 100 according to the present embodiment. As shown in FIG. 1, the multiprocessor system 100 has, for example, a multiprocessor 30 and a main memory 20. The multiprocessor 30 includes a memory control circuit 341, an internal bus control circuit 342, a processing element 34
_{3 1, 343 2, 343 3} , FIFO circuit 344 _1, 3
44 ₂ , 344 ₃ , 344 ₄ , memory I / F circuit 14
5, system I / F circuit 246 and internal bus 347,
348 in one chip. Here, the FIFO circuit 3
44 _{1-344 4} corresponds to the first memory circuit of the present invention,
The processing elements 343 ₁ and 343 ₃ correspond to the control circuit and the processing circuit of the present invention, and the internal bus 347,
Reference numeral 348 corresponds to the data transmission path of the present invention, and the main memory 20 corresponds to the storage circuit and the second storage circuit of the present invention.

Here, internal buses 347 and 348, memory I / F circuit 145 and FIFO circuits 344 _{1 to} 344 are provided.
The data width of ₄ is 64 bits. Here, the data width indicates the number of bits of data transmitted or accessed by one clock cycle or one access. For example, FIFO circuits 344 _{1 to} 344 ₄
The data width indicates the number of bits of data that can be transferred by one access when viewed from the internal bus 347.

In the present embodiment, as an example, in the multiprocessor 30, the image data processing circuits 21 ₁ and 21 ₁
An example in which predetermined image processing is performed while image data is input / output to / from the PC ₂ in real time will be described. Further, the image data processing circuits 21 ₁ and 21 ₂ include, for example, a horizontal synchronization signal Hsync and a pixel clock signal PC.
Image processing is performed based on.

[0031] In the multiprocessor system 100, as shown in FIG. 2, with respect to FIFO circuit 344 _1, 344 _4, the processing elements 343 _1, 343 ₂ located at the left side in FIG. 2, the real-time real-time processing is required The processing system 330 is configured. In the multiprocessor system 100, as shown in FIG.
For the FO circuits 344 _{1 to} 344 ₄ , the memory control circuit 341 and the internal bus control circuit 3 located on the right side in FIG.
42 constitutes a non-real-time (sequential) processing system 331 that does not require real-time processing. In the present embodiment, the FIFO circuits 344 ₁ and 344 ₄ provide
Real-time processing system 330 and non-real-time processing system 33
The difference in processing timing between the two is absorbed. In addition,
Processing element 343 _3, may be carried out either real-time processing and non-real time processing.

The memory control circuit 341 writes data to the main memory 20 by the processing elements 343 ₁ , 343 ₂ , and 343 ₃ and stores the data in the main memory 2.
Controls reading of data from 0. At this time, the access operation to the main memory 20 by the memory control circuit 341 is performed based on the control signal S342a from the internal bus control circuit 342.

Main memory by the memory control circuit 341
Access to the 20 is efficient memory access
From this point of view, as described later,
It is desirable to perform this in units of data. In this case,
The access speed to the memory 20 depends on the processor
G element 343₁~ 343_ThreeProcessing speed, FIFO
Circuit 344₁~ 344_FourData width and number of stages, internal buffer
347 data transfer rate, and the main memory 20
SDRAM (Synchronous Dynamic Random Access M
emory) is used during the refresh operation.
The processing element 343 ₁, 34
3_TwoTo guarantee real-time processing
There is a need.

As a memory access to the main memory 20, for example, a 16-time burst memory access method (burst transfer) is employed. The burst memory access method is performed based on the control of the memory control circuit 341 and the internal bus control circuit 342. After the memory control circuit 341 designates an address to be accessed in the main memory 20 once, the burst access method in the main memory 20 is performed. A total of 16 accesses are continuously made to the specified address and an address continuous to the specified address. In image processing and the like, accesses to consecutive addresses in the main memory 20 often occur continuously. By adopting such a burst memory access, the access efficiency to the main memory 20 is reduced. Can be greatly increased.

As the main memory 20, for example, as shown in FIG. 1, a memory in which four SDRAMs each having a data width (bus band width) of 16 bits are connected in parallel is used. The method of realizing the main memory 20 is arbitrary, and in addition, an SDRAM having a data width of 32 bits
May be connected in parallel. The storage area 150 in the main memory 20 shown in FIG.
44 _{1-344 4} data storage capacity of per one are stored.

Processing elements 343 ₁ , 34
3 ₂ is connected in real time to the external terminals 246a ₁ and 246a ₂ of the system I / F circuit 246, and between the image data processing circuits 21 ₁ and 21 ₂ connected to the external terminals 246a ₁ and 246a ₂ respectively. Executes the assigned process (task) while inputting and outputting data. In this embodiment, the external terminals 246a ₁ and 246a 2
To 46a _2, the image data processing circuit 21 _1, 21 ₂ is described as an example a case where it is connected. Each of the processing elements 343 ₁ and 343 ₂ performs processing on each pixel within a predetermined period based on the horizontal synchronization signal Hsync and the pixel clock signal PC input from a signal generator (not shown). Here, the pixel clock signal PC is a signal synchronized with the horizontal synchronization signal Hsync, and one cycle of the horizontal synchronization signal Hsync includes the pixel clock signal PC for P (P is an integer) cycles.

The processing element 34
3 ₁ and 343 ₂ transmit data to be output to other processing elements as needed, to FIFO circuits 344 ₁ and 344 ₂ .
In addition to the output to the 344 ₄ , data from other processing elements are input from the FIFO circuits 344 ₁ and 344 ₄ . Thereby, the processing element 3
In 43 _{1-343 3,} it can be carried out in cooperation predetermined processing while communicating with each other.

The processing element 34
3 ₁ and 343 ₂ output data to be written to the main memory 20 to the FIFO circuits 344 ₁ and 344 ₄ as needed, and input data read from the main memory 20 from the FIFO circuits 344 ₁ and 344 _{2 as} necessary. That is, the processing elements 343 ₁ , 343
₄ is for inputting data necessary for the processing read from the main memory 20 and for writing the data resulting from the processing to the main memory 20 in a FIFO manner.
Output to the circuits 344 ₁ and 344 ₄ .

The processing element 343 ₃ is not connected to the system I / F circuit 246, unlike the processing elements 343 ₁ and 343 ₂ .
The processing element 343 ₃ is a FIFO circuit 3
While inputting and outputting data in real time or non-real-time (sequential) between 44 _2, 344 ₃ and the main memory 20, it processes the data in real time or non-real-time.

The processing element 343 ₁
As 343 ₃ , for example, a CPU or DSP having an advanced intelligent function is used. Also,
The processing capabilities and configurations of the processing elements 343 _{1 to} 343 ₃ may be the same or different.

The FIFO circuits 344 _{1 to} 344 ₄ correspond to FIG.
As shown in (1), 1 has a data width (buffer width) of 64 bits and is a unit of data transfer to the main memory 20.
It has a storage capacity that is an integer (positive integer) times, preferably twice or more, 024 (64 × 16) bits of data.
Note that the data width of the FIFO circuits 344 _{1 to} 344 ₄ is
It does not depend on the width of the data unit handled by the processing elements 343 _{1 to} 343 ₃ .

Data is read from the FIFO circuits 344 ₁ , 344 ₃ to the internal bus 347,
Data from 7 to FIFO circuit 344 _2, 344 ₄ write is performed the data of 1024 bits is a unit of data transfer to the main memory 20 (burst transfer) as a unit.

The FIFO circuits 344 ₁ , 344
₃ are processing elements 343 ₁ , 34 at timings controlled by the read instruction signals S365 ₁ , S365 ₃ from the internal bus control circuit 342, respectively.
3 ₃ input from the (written) of 64-bit data S
364 ₁ and S364 ₃ (line data of the present invention) are output (read) to the internal bus 347 in the input order.

The FIFO circuits 344 ₂ and 344
₄ is a timing controlled by the write instruction signal S365 _2, S365 ₄ from the internal bus control circuit 342, respectively, (written) input from the internal bus 347 64-bit data S367 _2, S367 ₄ in input order of, Processing elements 343 ₃ , 3 respectively
43 and outputs ₂ (read). Note that the processing elements 343 _{1 to} 343 ₂ are
Unit of data to be input and output between _{1-344 4} is independent of the operation of the internal bus 347, for example, a few bits and several hundred bits.

The FIFO circuits 344 ₁ , 344
₃ monitors the remaining capacity indicating the storage capacity of the storage area in which data is not stored in the storage area, and outputs remaining capacity notification signals S366 ₁ and S366 ₃ indicating the remaining capacity to the internal bus control circuit 342. Further, the FIFO circuits 344 ₂ and 344 ₄ monitor the remaining capacity indicating the storage capacity of the storage area in which the data is already stored in the storage area, and output remaining capacity notification signals S366 ₂ and S366 ₄ indicating the remaining capacity. Output to the internal bus control circuit 342.

In this embodiment, the FIFO circuit 34
4 _{1-344 4} remaining amount, the processing element 3
43 _{1-343 3} assumes the case of performing real-time processing, the non-storage area where the data in the storage unit for FIFO circuit 344 _1, 344 ₃ for inputting data from the processing element 343 _1, 343 ₃ is not stored Indicates the capacity, the processing element 343 ₃ ,
FIFO circuit 344 ₂ , 3 for outputting data to 343 ₂
For 44 ₄ show the capacity of the storage area where the data in the storage unit has already been.

The internal bus control circuit 342 generates remaining amount notification signals S366 ₁ to S366 from the FIFO circuits 344 _{1 to} 344 _4.
FIFO circuits 344 _{1 to} 344 ₄ based on 366 ₄
Among these, the FIFO circuits 344 _{1 to} 344 ₄ having the smallest remaining amount among those having the predetermined thresholds below the predetermined threshold value are determined as targets to be controlled next. Internal bus control circuit 342
When the FIFO circuits 344 ₁ and 344 ₃ are determined as targets to be controlled next, the read instruction signal S36 is sent to the determined FIFO circuits 344 ₁ and 344 ₃ .
5 _1. S365 ₃ is output. The internal bus control circuit 342, as determined as an object to be next control FIFO circuit 344 _2, 344 _4, and the determined FI
Write instruction signal S365 ₂ with respect to FO circuit 344 _2, 344 _4. S365 ₄ is output.

The memory I / F circuit 145 is connected to the external terminal 14
5a, the external terminal 145a is connected to the memory control circuit 341 via the internal bus 348, and the main memory 20 is connected to the external terminal 145a.

The system I / F circuit 246 has an external terminal 2
46a _1, has 246a _2, the external terminal 246a _1, 2
46a ₂ are processing elements 34, respectively.
3 ₁ and 343 ₂ .

The processing of the multiprocessor system 100 when handling image data of various image formats will be described below. [Case of 16-bit image data format] A case where one pixel (pixel) has a data length of 16 bits will be described. In this case, the FIFO circuits 344 _{1 to} 344 ₄ shown in FIGS. 1 and 3 store four pixel data in one row (= 64 bits) of the storage area, as shown in FIG. There is no unstored area in each row.
The pixel data is stored in order from the head address in each of the FIFO circuits 344 _{1 to} 344 ₄ under the control of the processing elements 343 ₁ and 343 ₃ , for example. The FIFO circuit 34 is controlled by the memory control circuit 341 and the internal bus control circuit 342.
4 _1, 344 image data read from the ₃ via the internal bus 347, 348 with a 64-bit data width, and written into the main memory 20 as it is formatted. That is, the storage format of the image data in the main memory 20 is also as shown in FIG. Further, under the control of the memory control circuit 341, the image data read from the main memory 20 is transferred to the FIFO circuits 344 ₂ and 344 ₄ in the same format via the internal buses 347 and 348 having a data width of 64 bits. Written.

[Case of 24-bit Image Data Format] A case where one pixel (pixel) has a data length of 24 bits will be described. In this case, the FIFO circuit 344 _{1 to 344 4} shown in FIGS. 1 and 3, the as shown in FIG. 5, one row of the storage area (= 64 bits) 8
/ 3 pixel data are stored. However, as shown in FIG. 5, the first row can store the entire pixel data of the first pixel and the second pixel, but the pixel data of the third pixel stores only 16 bits on the MSB (Most Significant Bit) side. Can not. The 8 bits on the LSB (Least Significant Bit) side of the pixel data of the third pixel are stored in the second row. The second row stores the LSB side 8 bits of the pixel data of the third pixel, the entire pixel data of the 4th and 5th pixels, and the 8 bits of the MSB side of the 6th pixel data. . In the third row, the L of the pixel data of the sixth pixel is
The 16 bits on the SB side and the entire pixel data of the seventh and eighth pixels are stored. In the fourth and subsequent rows, the pixel data of the ninth and subsequent pixels include
It is stored in the same manner as in the third row.

The above-described FIFO circuits 344 _{1 to} 344 ₄
The storage pattern of the pixel data within is determined when the pixel data is written from the processing elements 343 ₁ and 343 ₃ to the FIFO circuits 344 ₁ and 344 ₃ . The FIFO circuits 344 ₁ and 344 are controlled by the memory control circuit 341 and the internal bus control circuit 342.
_The image data read from ₃ is written to the main memory 20 in the same format via the internal buses 347 and 348 having a data width of 64 bits. That is, the storage format of the image data in the main memory 20 is also as shown in FIG. Further, the image data read from the main memory 20 is passed through the internal buses 347 and 348 having a data width of 64 bits and the FIFO circuits 344 ₂ and 344 _{4 in} the same format.
Is written to.

As described above, in the case of the 24-bit image data format, the storage area for three rows is completely used for every eight pixel data. Thus, the pixel data in the format shown in FIG. 5 FIFO circuits 344 ₁ to
344 to be stored in the _4, counting modulo 8 (count)
Requires a circuit to perform. However, the FIFO circuits 344 _1-
344 ₄ and the storage format of the pixel data to the main memory 20, the multiprocessor 30 shown in FIG. 1
, The processing elements 343 ₁ , 34
Since it is determined by the writing operation to the FIFO circuits 344 ₁ and 344 ₄ by 3 ₃ , the circuit that calculates the remainder of 8 and determines the storage pattern of the pixel data according to the result of the remainder is a processing element 343 ₁ ,
343 ₃ . The function of these circuits is
It may be realized by software. Therefore, it is possible to prevent the circuits of the memory control circuit 341 and the internal bus control circuit 342 from becoming complicated.

[One Frame Storage Method] A format for storing one frame of image data for displaying one image image in the FIFO circuits 344 _{1 to} 344 ₄ and the main memory 20 will be described in detail below.
The image data of the image data format of, for example, 16 bits or 24 bits shown in FIGS. 4 and 5 described above is stored in the main memory 20 in order from the head address, which is equivalent to one line of one image image. (For one row extending in the horizontal direction). That is, when one line (row) of one image is stored in the main memory 20, the head of the line is always aligned with a 1024-bit address. This is because the FIFO circuits 344 _{1 to} 34 ₁
4 ₄ and the unit of data transfer between the main memory 20 (1
(The amount of data transferred by one transfer instruction) is an integral multiple of the memory reference unit of the main memory 20 (the amount of data handled in one access to the main memory 20, 1024 bits in this embodiment). It can be realized automatically by setting as follows.

Access to the main memory 20 is performed by burst transfer in which data transfer of 64 bits each is performed 16 times in succession, and data access of 1024 bits is performed by one burst transfer.
Performed on 0.

When the pixel data of the last pixel of one line (the rightmost pixel of each line of one image image) is written to the FIFO circuits 344 _{1 to} 344 ₄ , the pixel data is not necessarily equivalent to one unit of memory reference. Writing of the image data is not always completed. This is because, as described above, the data amount for one line may not be an integral multiple of the unit of memory reference. For example, in the 16-bit image data format shown in FIG. 4, when one line consists of 720 pixels, one line is transferred between the FIFO circuits 344 _{1 to} 344 ₄ and the main memory 20 as shown in FIG. To transfer the data of
After transferring 11,264-bit image data (image data for 704 pixels) 400 by one burst transfer, 256-bit image data (image data for 16 pixels) 401 is transferred by one burst transfer. In this case, all data becomes valid data 402 in the first 11 burst transfers, but in the subsequent one burst transfer, image data for 16 pixels is valid data 402 but the rest is invalid. It becomes data 403.

In the present embodiment, invalid data 403 is
The data is written to the FIFO circuits 344 _{1 to} 344 ₄ and the main memory 20 as they are. That is, in this embodiment, one line of image data is handled as a memory reference of 12 units. Therefore, as shown in FIG. 7, image data for 12 transfers is stored in the main memory 20 using all 64 bits in the row direction. However, as shown in FIG.
The main memory 20 stores 11 lines for each line of one frame.
Following the 520-bit valid data 402, 768-bit invalid data 403 is stored. In this manner, in the main memory 20, the head of the next line of one image is automatically stored at an address of a multiple of 1024 bits. Therefore, it is not necessary to recalculate the address in the main memory 20, and the main memory 20 can be simplified and downsized. Also, the memory control circuit 341 does not need to perform the control of stopping the burst transfer halfway, so that the memory control circuit 341 does not need to perform the control.
Can be simplified and downsized. Note that the SDRAM has a characteristic access method called a burst transfer method. In the method of the present invention, the number of accesses is set to 16 so that the access efficiency is maximized. Is the number of burst accesses.
Although it is efficient because data is accessed continuously, even if the transfer operation is continued without stopping the transfer in the middle, the influence on the consumed clock cycle is small. In the multiprocessor system 100, for example, various processes including generation of a memory address of the main memory 20 are pipelined inside the chip. Therefore, when the burst transfer is stopped, these pipeline processes are stopped. As a result, a new memory cycle is generated, which is not desirable from the viewpoint of efficient processing.

Meanwhile, the 24-bit image data format shown in FIG. 5, when one line is composed of 1024 pixels, as shown in FIG. 8, FIFO circuit 344 ₁
～344 ₄ and to transfer data of one line to and from the main memory 20, 2 by burst transfer 24 times
4576-bit image data (image data for 1024 pixels) 410 is transferred. In this case, only valid data 411 is transferred in all of the 24 burst transfers, and invalid data is not transferred.

[Read Operation from Main Memory 20]
FIG. 9 illustrates the operation of the multiprocessor system 100 when processing image data corresponding to a partial area in one image represented by one frame of image data stored in the main memory 20. FIG. For example, in the image format in which one pixel data is 16 bits as described with reference to FIGS.
The case where image data corresponding to the area 221 in one frame of the image image of 720 pixels (horizontal) × 256 pixels (vertical) shown in FIG. Area 2
Reference numeral 21 denotes, for example, a rectangular area displayed by pixels positioned at the 200th to 400th pixels from the left end in the horizontal direction among the pixels at the Mth to Nth lines in the vertical direction in one frame shown in FIG. is there. Here, in the main memory 20, image data corresponding to the area 221 in one frame is stored in a storage area 550 that is discretely located as indicated by oblique lines in FIG.

As shown in FIG. 9, the image data corresponding to the area 221 in one frame stored in the main memory 20 is read out to the internal bus 347 by the control of the memory control circuit 341 as described below. By the control of the internal bus control circuit 342, for example, the FIFO circuit 344 ₂
Or written to 344 _4. That is, as shown in FIG. 10, the memory control circuit 341 includes the head pixel (the leftmost pixel in the figure) of the Mth line in units of 1024-bit image data which is data for one burst transfer. In order from 1024-bit image data,
1024-bit image data including the last pixel on the M-th line (the rightmost pixel in the figure) is sequentially read from the main memory 20. Thus, the image data of M-th line is read from the main memory 20, the read image data is written into the FIFO circuit 344 ₂ or 344 ₄ via the internal bus 347 under the control of the internal bus control circuit 342 .

Thereafter, similarly, the image data of the (M + 1) th line to the Nth line in one frame stored in the main memory 20 are sequentially read out, and the internal bus 347 is controlled by the internal bus control circuit 342. FIFO via
The data is written to the circuit 344 ₂ or 344 ₄ . Thus, in the present embodiment, the unit of burst transfer, 10
Since image data is read from the main memory 20 in units of 24 bits, the image data 51 corresponding to the area 221 to be read in one frame shown in FIG.
1, image data 510 not to be read
It is also read out to the FIFO circuit 344 ₂ or FIFO circuit 344 ₄ via the internal bus 347. In the processing elements 343 ₃ and 343 ₂ , among the image data input from the FIFO circuits 344 ₂ and 344 ₄ , the image data becomes the read object shown in FIG. 10 corresponding to the area 221 to be read in one frame shown in FIG. The image data 511 is selected for processing. As described above, in the present embodiment, the processing element 34
By selecting the image data 511 in 3 ₃ and 343 ₂ , the read control from the main memory 20 by the memory control circuit 341 can be simplified.

Hereinafter, an operation example of the multiprocessor system 100 shown in FIG. 1 will be described. Data from the image data processing circuit 21 ₁ is input to the processing element 343 ₁ in real time via the external terminals 246a _1, predetermined processing in the processing element 343 ₁ based on the data is performed in real time. Then, the data S364 ₁ is written in real time to the FIFO circuit 344 ₁ is a processing element 343 ₁ of the processing result. Further, in the processing element 343 ₃ , a predetermined process is performed based on the data S364 ₂ input from the FIFO circuit 344 ₂ , and the processing result data S364 ₃ is output to the FIFO circuit 3344.
It is written to 44 _3. Further, the processing element 343 _2, the process based on the data S364 ₄ from the FIFO circuit 344 ₄ is performed in real time,
Data of the processing result is output in real time via the external terminals 246a ₂ to the image data processing circuit 21 _2. The processing elements 343 _{1 to} 34 described above.
3 in the process of _3, to be accompanied by a memory access to the main memory 20, depending on the image format, as described above, the internal bus 347 and the main memory 20 by using all the 64-bit data width Data transfer is performed between them. At this time, as described above, all the effective image data are stored in each row of the storage area of the main memory 20.

As described above, according to the multiprocessor system 100, access to the main memory 20 can be realized with a simple and small configuration. Also,
According to the multiprocessor system 100, the size of the main memory 20 can be reduced as compared with the related art. Also, according to the multiprocessor system 100, the internal bus 34
7,348 can be increased, and the data width required for the internal buses 347,348 can be reduced.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case where image data is handled in the multiprocessor system 100 has been described as an example. However, the present invention is not limited to image data, but is data including a plurality of modules having a predetermined data length, and The present invention is also applicable to a case where data of a plurality of formats having different predetermined data lengths is handled. For example,
The present invention relates to FA (Factory Automation), NC (Numerical
Control), broadcasting and communication.

Further, in the above-described embodiment, the case where the frame data is handled has been exemplified, but the field data may be handled. Further, in the present invention, the number of processing elements and the connection form are not limited to those described above. Further, in the above-described embodiment, the case where the multiprocessor system is connected to the image data processing circuit that performs the real-time processing is illustrated. However, the multiprocessor system may be connected to another circuit that performs the real-time processing. Further, in the above-described embodiment, the case where the main memory 20 is realized using an SDRAM is illustrated, but the main memory 20 may be realized using another memory such as an SRAM.

[0066]

As described above, according to the data processing apparatus of the present invention, data of a plurality of formats having a plurality of modules having a predetermined data length and different in the predetermined data length depending on the format is obtained. Even in the case of handling, a high data transfer rate can be realized, and the storage area of the storage circuit can be used efficiently. Further, according to the data processing device of the present invention, even when various image formats are adopted, a high data transfer rate can be realized, and the storage area of the storage circuit can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a real-time processing system and a non-real-time processing system of the multiprocessor system shown in FIG. 1;

FIG. 3 is a diagram for explaining a FIFO circuit and a storage area of a main memory shown in FIG. 1;

FIG. 4 is a diagram illustrating the FIF shown in FIG. 1 when one pixel data adopts a 16-bit image format;
FIG. 3 is a diagram illustrating a storage image of pixel data in an O circuit and a main memory.

FIG. 5 is a diagram illustrating the FIF shown in FIG. 1 when one pixel data adopts a 24-bit image format;
FIG. 3 is a diagram illustrating a storage image of pixel data in an O circuit and a main memory.

FIG. 6 is a diagram illustrating the FIF shown in FIG. 1 when one pixel data adopts an image format of 16 bits.
FIG. 3 is a diagram illustrating a relationship between a storage image of pixel data in an O circuit and a main memory and a unit of burst transfer.

FIG. 7 is a diagram illustrating the FIF shown in FIG. 1 when one pixel data employs an image format of 16 bits.
FIG. 4 is a diagram illustrating a relationship between a storage image of each line of one frame in an O circuit and a main memory and a unit of burst transfer.

FIG. 8 is a diagram illustrating the FIF shown in FIG. 1 when one pixel data adopts a 24-bit image format;
FIG. 3 is a diagram illustrating a relationship between a storage image of pixel data in an O circuit and a main memory and a unit of burst transfer.

FIG. 9 is a diagram for explaining an operation of reading a part of image data in one frame from a main memory under the control of the memory control circuit shown in FIG. 1;

FIG. 10 is a diagram for explaining the read operation shown in FIG. 9 in units of pixel data;

FIG. 11 is a diagram for explaining a conventional storage image in a system memory (main memory) when one pixel data adopts a 24-bit image format.

[Explanation of symbols]

20: Main memory, 21 ₁ , 21 ₂ : Image data processing circuit, 341: Memory control circuit, 342 ... Internal bus control circuit, 343 _{1 to} 343 ₅ ... Processing elements, 344 _{1 to} 344 ₄ ... FIFO circuit, 345 ... Memory I / F circuit, 345a ... external terminals, 246 ... system I / F circuit, 145a, 246a ₁ ~246a ₄ ... external terminals, 347, 348 ... internal bus

Claims (16)

[Claims] 1. A data processing apparatus for handling data of a plurality of formats, each of which comprises a plurality of modules having a predetermined data length, and wherein the predetermined data length differs depending on a format, comprising: a storage circuit; a data transmission path; When accessing the storage circuit via a data transmission path, even when handling data of any of the plurality of formats, the plurality of data is transmitted using the entire data width of the data transmission path. A control circuit that determines a transmission pattern of the module, and divides at least one of the modules as necessary and transmits the divided modules at different timings via the data transmission path. 2. The data processing device according to claim 1, wherein the data width of the data transmission path is the same as the data width of the storage circuit. 3. The data processing apparatus according to claim 1, wherein said control circuit performs access to said storage circuit by burst-transferring said data via said data transmission path. 4. A data processing apparatus for handling a plurality of frame data or field data which is a plurality of frame data or a plurality of pixel data having a predetermined data length and which differs in the predetermined data length depending on a format. Or, a storage circuit for storing field data, a data transmission path, and when accessing the storage circuit via the data transmission path, when handling data in any of the plurality of formats, the data transmission path A transmission pattern of the plurality of pixel data is determined so that the pixel data is transmitted using the entire data width, and if necessary, at least one of the pixel data is divided through the data transmission path at different timings. Processing device having a control circuit for transmitting data . 5. The control circuit according to claim 1, wherein the pixel data at the head of each line of the image corresponding to the frame data or the field data is a data amount of an integral multiple of the data amount transferred by one burst transfer. 5. The data processing device according to claim 4, wherein the data is stored in the storage circuit at an address interval corresponding to the following. 6. When reading out the pixel data of a partial area of an image corresponding to frame data or field data from the storage circuit, the control circuit is configured to read the pixel data of a plurality of lines including all of the partial area. 5. The data processing device according to claim 4, wherein the pixel data is sequentially read from the storage circuit and transmitted via the data transmission path. 7. A processing circuit for selecting and processing pixel data corresponding to the partial area among the pixel data of the plurality of lines read from the storage circuit input through the data transmission path. Claim 6 further comprising:
A data processing device according to claim 1. 8. A data processing apparatus for handling data of a plurality of formats having a plurality of modules each having a predetermined data length and having the predetermined data length different depending on a format, wherein the plurality of modules have a common data width. A first storage circuit that stores the data as a plurality of line data, and reads out the stored line data in a writing order; and when the data of any of the plurality of formats is handled, the data width of the line data is completely used. A processing circuit for writing the line data containing the module into the first storage circuit, dividing at least one of the modules into different line data as needed, and writing the divided line data to the first storage circuit; A data transmission path having the same data width as the first storage circuit; A data processing device comprising: a path; and a storage control circuit that writes the line data read from the first storage circuit to the second storage circuit. 9. The second storage circuit has the same data width as the first storage circuit, and the storage control circuit transmits the line data read from the first storage circuit to the data transmission path. 9. The data processing device according to claim 8, wherein the data is directly written into the second storage circuit via the second storage circuit. 10. A data processing apparatus for handling frame data or field data of a plurality of formats, which is frame data or field data composed of a plurality of pixel data having a predetermined data length and has different predetermined data lengths depending on formats. A first storage circuit that stores a plurality of pixel data as a plurality of line data having a common data width, and reads out the stored line data in a writing order; and when handling frame data or field data of any of the plurality of formats However, the line data containing the pixel data is written into the first storage circuit so as to use up the entire data width of the line data, and if necessary, at least one of the pixel data is divided into different line data. Put in data A processing circuit for writing to the first storage circuit, a data transmission path having the same data width as the first storage circuit, a second storage circuit, and the line data read from the first storage circuit. A data processing device comprising: a storage control circuit that writes to the second storage circuit. 11. The second storage circuit has the same data width as the first storage circuit, and the storage control circuit transmits the line data read from the first storage circuit to the data transmission path. 11. The data processing device according to claim 10, wherein the data is written to the second storage circuit as it is via an external device. 12. The storage control circuit according to claim 1, wherein the pixel data at the head of each line of the image corresponding to the frame data or the field data is an integral multiple of a data amount transferred by one burst transfer. 11. The data processing device according to claim 10, wherein the data is written to the second storage circuit at an address interval corresponding to the amount. 13. When reading out the pixel data of a partial area of an image corresponding to frame data or field data from the second storage circuit, the control circuit may include a plurality of pixels including all of the partial area. 2. The pixel data of a line is sequentially read from the second storage circuit and transmitted via the data transmission path.
0. The data processing device according to 0. 14. A method of selecting and processing pixel data corresponding to the partial area from among the pixel data of the plurality of lines read from the second storage circuit input through the data transmission path. 14. The data processing device according to claim 13, further comprising a processing circuit that performs the processing. 15. A data processing device for handling frame data or field data comprising a plurality of pixel data each having a data length of 16 bits, wherein said stored data is stored as a plurality of line data having a data width of 64 bits. A first storage circuit for reading data in the order of writing, a processing circuit for writing the line data containing the four pixel data to the first storage circuit, a data transmission path having a data width of 64 bits, A data processing device comprising: a second storage circuit; and a storage control circuit that writes the line data read from the first storage circuit directly to the second storage circuit via the data transmission path. 16. A data processing apparatus for handling frame data or field data comprising a plurality of pixel data each having a data length of 24 bits, wherein said data is stored as a plurality of line data having a data width of 64 bits. A first storage circuit for reading data in the order of writing; a processing circuit for writing the line data containing 8/3 of the pixel data into the first storage circuit; a data transmission path having a data width of 64 bits; A data processing device, comprising: a second storage circuit; and a storage control circuit that writes the line data read from the first storage circuit directly to the second storage circuit via the data transmission path.