JPH0266654A - Cache memory controlling system - Google Patents
Cache memory controlling systemInfo
- Publication number
- JPH0266654A JPH0266654A JP63219327A JP21932788A JPH0266654A JP H0266654 A JPH0266654 A JP H0266654A JP 63219327 A JP63219327 A JP 63219327A JP 21932788 A JP21932788 A JP 21932788A JP H0266654 A JPH0266654 A JP H0266654A
- Authority
- JP
- Japan
- Prior art keywords
- cache
- access
- circuit
- memory
- rewriting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 7
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000008014 freezing Effects 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はキャッシュメモリ制御方式に関し、特に外付け
のメモリキャッシュ装置の制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method, and particularly to a control method for an external memory cache device.
従来、この種のキャッシュメモリ制御方式は、マツプ方
式で同じエントリにマツピングされるアドレスをアクセ
スするとキャッシュの内容が書き換えられてしまってい
た。Conventionally, this type of cache memory control method uses a map method, and when an address mapped to the same entry is accessed, the contents of the cache are rewritten.
上述した従来のキャッシュメモリ制御方式は、広い範囲
のメモリアクセスでは、アクセスする度にキャッシュの
内容が書き換えられてしまうので、キャッシュの効果が
得られないという欠点がある。The above-described conventional cache memory control method has the disadvantage that when a wide range of memory is accessed, the contents of the cache are rewritten each time it is accessed, so that the cache effect cannot be obtained.
本発明のキャッシュメモリ制御方式は、外部メモリと、
キャッシュ回路と、メモリアドレスのアクセス頻度を計
測するカウンタと、その計測情報に基づきアクセス頻度
の高いものはキャッシュ凍結し、アクセス頻度の低いも
のはキャッシュ書換え可とする制御を行うキャッシュ制
御部とを備えることを特徴とする。The cache memory control method of the present invention includes an external memory,
It includes a cache circuit, a counter that measures the access frequency of memory addresses, and a cache control unit that performs control based on the measurement information to freeze the cache of frequently accessed addresses and to enable cache rewriting of those that are accessed less frequently. It is characterized by
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図において、キャッシュ回路３はプロセッサ１がメ
モリ２をアクセスしたときのアクセスアドレスがキャッ
シュの中に存在するかどうかをチエツクし、もし存在す
ればプロセッサ１はキャッシュ回路３内の値を読み出し
、またキャッシュの中に存在しなければ外部メモリ２か
ら読み出して自動的にキャッシュに書き込む。カウンタ
５はキャッシュ回路３へのアクセス頻度をキャッシュ制
御装置４を介して計測し、キャッシュ制御装置４はアク
セス頻度の高い順にキャッシュ凍結（書換え不許可）し
、アクセス頻度の低いものに対してはキャッシュ書換え
可とする。In FIG. 1, the cache circuit 3 checks whether the access address used when the processor 1 accesses the memory 2 exists in the cache, and if it exists, the processor 1 reads the value in the cache circuit 3, If it does not exist in the cache, it is read from the external memory 2 and automatically written to the cache. The counter 5 measures the frequency of access to the cache circuit 3 via the cache control device 4, and the cache control device 4 freezes the cache (disallows rewriting) in order of access frequency, and caches the cache circuit 3 for the cache circuit 3 with low access frequency. It is rewritable.
本実施例では、キャッシュ制御装置４とカウンタ５とを
キャッシュ回路３に付加しているだけなので、メモリア
クセスの実効速度に何ら影響を与えることなく、アクセ
ス頻度の高いものをキャッシュに置くことができる。In this embodiment, since the cache control device 4 and the counter 5 are simply added to the cache circuit 3, frequently accessed items can be placed in the cache without any effect on the effective speed of memory access. .
以上説明したように本発明によれば、アクセス頻度を計
測してアクセス頻度の高いものをキャッシュ凍結するこ
とにより、広い範囲のメモリアクセスでも毎回書き換え
られることなしに最大のキャッシュ効果が得られる。As described above, according to the present invention, by measuring the access frequency and freezing the cache of frequently accessed items, the maximum cache effect can be obtained even in a wide range of memory accesses without being rewritten each time.
第１図は本発明の一実施例を示すブロック図である。
１・・・プロセッサ、２・・・外部メモリ、３・・・キ
ャッシュ回路、４・・・キャッシュ制御部、５・・・カ
ウンタ。FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Processor, 2... External memory, 3... Cache circuit, 4... Cache control part, 5... Counter.
Claims (1)
クセス頻度を計測するカウンタと、その計測情報に基づ
きアクセス頻度の高いものはキャッシュ凍結し、アクセ
ス頻度の低いものはキャッシュ書換え可とする制御を行
うキャッシュ制御部とを備えることを特徴とするキャッ
シュメモリ制御方式。A counter that measures the access frequency of external memory, cache circuits, and memory addresses, and a cache control that controls the cache of frequently accessed items based on the measurement information, and freezes the cache of frequently accessed items, and allows cache rewriting of infrequently accessed items. A cache memory control method comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63219327A JPH0266654A (en) | 1988-08-31 | 1988-08-31 | Cache memory controlling system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63219327A JPH0266654A (en) | 1988-08-31 | 1988-08-31 | Cache memory controlling system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0266654A true JPH0266654A (en) | 1990-03-06 |
Family
ID=16733726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63219327A Pending JPH0266654A (en) | 1988-08-31 | 1988-08-31 | Cache memory controlling system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0266654A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5380614A (en) * | 1992-04-02 | 1995-01-10 | Tomoegawa Paper Co., Ltd. | Positive chargeable color toner |
| US8261022B2 (en) | 2001-10-09 | 2012-09-04 | Agere Systems Inc. | Method and apparatus for adaptive cache frame locking and unlocking |
-
1988
- 1988-08-31 JP JP63219327A patent/JPH0266654A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5380614A (en) * | 1992-04-02 | 1995-01-10 | Tomoegawa Paper Co., Ltd. | Positive chargeable color toner |
| US8261022B2 (en) | 2001-10-09 | 2012-09-04 | Agere Systems Inc. | Method and apparatus for adaptive cache frame locking and unlocking |
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