JPH026224B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to direct tunneling, Fauler-Nordheim tunneling, conduction via trap levels, and isocarriers passing through at least a portion of the forbidden band (hereinafter, the term "tunnel" will be used generically). ) Carriers are injected from the conductive opposing region into the semiconductor, which has a narrower bandgap than the thin film, through a semiconductor thin film or insulating thin film that has a relatively thin film thickness and a wide bandgap, and is amplified. The present invention relates to semiconductor devices and their integrated circuits that perform functions such as , switching, oscillation, generation of voltage or current, and generation of negative resistance.

In a conventional pn junction, the conditions for efficient carrier injection into one region are that both the p and n regions forming the junction have good crystallinity, with few defects and trap levels, and The relationship between impurity concentrations is limited, and the impurity concentration in the region receiving implantation is more than an order of magnitude lower than in the other region. The optimal design was not carried out. Furthermore, it has been difficult to directly inject light into the semiconductor surface, to efficiently utilize light emitted externally, to achieve useful functions with a small number of regions, and to create devices that perform new operations. .

The present invention aims to eliminate these conventional drawbacks and provide a new device. To this end, the present invention uses carrier injection through a thin film as the operating principle of the device. If this thin film is thin enough to allow transport of more carriers than expected from the bulk material, such as through direct or indirect tunneling of carriers, and if the bandgap is larger than that of the semiconductor receiving the carrier injection, then the semiconductor receiving the injection Even if the impurity concentration of Can be set regardless of carrier density. In other words, by selecting a material relationship in which the barrier of the thin film seen from the semiconductor has a high barrier with respect to a carrier of opposite polarity to the main carrier, and the barrier of the thin film seen from the opposing region is lower with respect to the main carrier, it is possible to Injection into a semiconductor region can be performed efficiently. Moreover, even without using such material relations, it is possible to select a thin film in which the carrier transported through this thin film is mainly a single carrier, or to use a conductive region having the polarity of the carrier that is desired to be transported in the thin film. The object of the present invention can be achieved by forming the semiconductor region with a shaped semiconductor region. According to such a configuration, the thin film and the opposing region do not necessarily have to be a single crystal with good crystallinity, and may be polycrystalline or amorphous. Of course, the opposing region may be a metal electrode, and the thin film may be an insulating film such as SiO ₂ .

Hereinafter, the present invention will be explained in detail through specific examples.

FIG. 1 shows an embodiment of the present invention, in which 100 is a semiconductor region to be implanted, 1 is a thin film of a material with a large forbidden band width, and 10 is a semiconductor region 100 with thin film 1 in between.
This is the opposing area facing the . FIG. 1b shows an example of a band diagram of the device whose cross-sectional view is shown in a, and shows the case where electrons are mainly transported between the opposing region 10 and the semiconductor region. In the following examples, the explanation will be made assuming that the main carriers transported through the thin film are electrons, but if the main carriers are holes, the semiconductor receiving injection and the opposing region are semiconductors, the conductivity type of the opposing region will be explained. Just include it and reverse the pn relationship.

Now, when the potential of the opposing region 10 is increased in the negative direction, the electron potential of the opposing region 10 becomes the first
The electrons rise as shown in FIG. 2B, and electrons from the opposing region 10 are transferred through the thin film 1 to the semiconductor region 100 by a tunneling phenomenon or the like and are injected. Here, a specific example will be described in which the thin film 1 is made of a material in which the semiconductor region 100 is n-type and the main carriers to be transported are electrons.

When the potential of the opposing region 10 is increased to the negative side,
When the surface of the semiconductor region 100 facing the opposing region 10 becomes depleted and the potential of the opposing region is further increased to the negative side, holes are induced in the surface of the semiconductor region 100.

However, these holes are minority carriers in the semiconductor region 100 and the supply amount is small, so even if the main carriers in the thin film 1 are electrons, these holes are sufficiently transported through the thin film 1 to the opposing region 10 side. Otherwise, the holes are recombined at the interface between the thin film 1 and the semiconductor region 100, so that holes do not accumulate on the surface of the semiconductor region, and as shown in the imaginary band diagram D in FIG. As shown, a state can be created in which the depletion layer expands as the potential of the opposing region 10 increases.

Therefore, under such conditions, as shown in the embodiments of the present invention shown in FIGS. 2 and 11, which will be described later, a small number of When carrier holes are supplied, the holes are accumulated on the surface of the semiconductor region 100 and an inversion layer is formed, that is, as shown by the solid line band diaphragm L in FIG. 1b. As shown in FIG.

In this case, more electrons from the opposing region 10 are injected into the semiconductor region 100 through the thin film 1 due to a tunneling phenomenon or the like, and in this case, the electric field vs. current characteristic of the thin film 1 is usually exponential. As a result, in the above operating region, a small change in the electric field causes a large change in the current.
A current larger than the current used to supply holes can be passed.

That is, the semiconductor device of the present invention that can cause such an operation has the opposing region 10 as an emitter,
A bipolar transistor operation can be performed using a depletion layer or an inversion layer, which does not exist but occurs during operation, as a base and the semiconductor region 100 as a collector.

In this way, the device of the present invention whose principle structure and operation have been explained based on FIG. 1 can be constructed as a more specific embodiment as shown in FIG.

As described above, the base for the operation of the bipolar transistor in the device of the present invention does not exist in this embodiment either, but is a depletion layer or an inversion layer induced on the surface of the n-type semiconductor region 102. n
The shaped semiconductor region 102 is similar to the semiconductor region 10 in FIG.
Corresponds to 0.

The potential of the depletion layer or inversion layer can be controlled by connecting the depletion layer or inversion layer with a directly adjacent channel or the like in the semiconductor region 102, as shown in the embodiments described later. In order to be able to control from the n-type semiconductor region 102
It is sufficient to provide a p-type semiconductor region 101C as a second region on the surface of the substrate at a position where carriers can reach from the depletion layer or inversion layer.

This second region 101C can just be used as a base connection region (base contact region), and can also be used as 10E, 101E, 1 in FIG.
02E acts as an emitter terminal, a base terminal, and a collector terminal, which are ohmically connected to the opposing region 10, the base connection region 101C, and the n-type semiconductor region 102 through electrodes, respectively.

The feature of this device is that carriers injected from the opposing region 10, which is an emitter, pass through a metallurgically formed, so to speak, substantial base region, as seen in conventional bipolar transistors. Differently, since it passes through a depletion layer or an inversion layer that is electrically induced on the surface of the semiconductor region, it can reach the semiconductor region 102, which is the collector region, in an extremely short time.In other words, it is faster than the conventional bipolar transistor structure. It has a structure that is much more convenient for operation.

This is because the depletion layer or inversion layer used in this device can be extremely thin compared to the metallurgically formed base region found in ordinary bipolar transistors. This is because it is formed.

Furthermore, if the base region is composed of an induced depletion layer or an inversion layer, it is easy to obtain a structure in which a circuit is directly connected to a MOS transistor or a CCD, as shown in the 11th embodiment shown in FIG. Become.

FIG. 3 explains another operating principle that can be adopted in the present invention, and the cross-sectional structure shown in FIG.
It has substantially the same cross-sectional structure as that in FIG. 1a. However, in order to exhibit new functions as described below, there are different design standards for, for example, the thickness of the thin film 1.

For example, in FIG. 3a, the film thickness of the thin film 1 is such that the potential of the opposing region 10 is set to a value larger than the voltage conversion value of the forbidden band width E _G of the semiconductor region 100 with respect to the semiconductor region 100, although the tunnel current flows If the thickness is such that a reasonable current can flow without causing destruction even if the tunneling carrier is an electron (on the negative side), the opposing region 10 is When biased to a voltage equivalent to the forbidden band width or more than the conduction band of the semiconductor region 100, the tunnel-injected electrons are in a high energy state (e ^* ) and generate electron-hole pairs near the surface of the semiconductor region 100. be able to. The generated holes are collected on the surface of the semiconductor region 100, and if the semiconductor region 100 is n-type, the width of the surface depletion layer is not small, so the injection of electrons from the opposing region 10 is further promoted, resulting in an on state. .

As a result, a current controlled negative resistance as shown in FIG. 4 is obtained. In Figure 3b, band diagram a shows the state before the generation of electron-hole pairs, and band diagram b shows that the generated holes are accumulated on the surface and that less voltage is required to flow the same current. shows.

An example of experimental results for the specific example shown in FIG. 3 will be described next. The opposing region 10 is a metal thin film, for example aluminum, the thin film 1 is an insulating film, for example a clean SiO ₂ film of around 30 Å, and the semiconductor region is 10 ¹⁷ pieces/cm ³
When using a Si single crystal containing phosphorus atoms, the breakover voltage of the negative resistance characteristic shown in Figure 4
V _B is −4V to −5V, holding voltage V _H is −3.1 to −3.2V,
The holding current density (=holding current I _H /device area) was approximately 2 μA/cm ² . Further, when the opposing region of this experimental sample is biased between -3.2V and -4V with respect to the semiconductor region, and light from a light emitting diode or about 500 mW tungsten lamp is applied in a pulsed manner, the sample changes from the off state to the on state. This state persisted even after the light was removed unless the bias voltage was changed from the holding voltage _VH to 0 volts. This experimental example demonstrates that according to the present invention, electronic switch operation can be realized with a simple structure.

Furthermore, when the above-mentioned basic structure of the device structure of the present invention is used, even if a general non-luminescent material such as Si is used as the semiconductor region 100, electron-hole pairs are generated by high-energy carriers. By using this, various other device operations can also be made possible.

FIG. 5 shows one specific example of this, in which holes generated by high-energy carriers injected from the opposing region 10 are brought into contact with the n-type semiconductor region 100 and within the reachable distance due to hole diffusion or drift. When collected in the provided p-type semiconductor region 101B, even though a negative bias is applied to the opposing region 10, the region 1
A positive potential can be extracted from 01B.

In short, it can also be used as a power source with polarity inversion having the characteristics shown in FIG. Furthermore, as shown in the same figure, it can also generate current and can be used as a current source. This is convenient for obtaining biases with different polarities in integrated circuits and the like. FIG. 7 shows a concrete example of this application. As shown in the figure, on the high impurity concentration n-type region 100b.
It is possible to simultaneously fabricate a p-channel insulated gate transistor and a multi-collector npn bipolar transistor with a p-type base in the surface of a substrate on which an n-type region 100a of the order of 10 ¹⁴ to 10 ¹⁶ is formed, but these two elements are not identical. A negative power supply and a power supply are required to operate simultaneously within the board. However, if the specific example of the present invention shown in FIG. 5 is further applied, only one type of external power source is required. In cross-sectional view a, regions 110 and 111 respectively represent the source and drain regions of the insulated gate transistor, 112 represents the insulated gate,
113 indicates a gate insulating film. Region 10 is an opposing region, 1 is a thin film, and 101B is a region that collects minority carriers generated on the surface of the region 100a by high-energy carriers that have passed through the thin film 1 in a tunnel or the like. It is provided within the reach of the minority carrier from the joint surface. Region 101B is a region of the opposite conductivity type to region 100a,
In this specific example, it is p-type. Areas 104A and 104
B is a region formed in the region 101B and has a conductivity type opposite to that of the region 101B, and forms a multi-collector of the npn transistor. The base of the npn transistor is common to the carrier collection region 101B described above, and the emitter is formed of the substrates 100a and 100b. In the figure, the portion indicated by _CT1 is an amplification circuit or logic circuit of an npn transistor output that operates by applying a negative bias to the opposing region 10, as shown in the equivalent circuit _CT1 of figure b. On the other hand, the portion indicated as _Q1 is a p-channel insulated gate transistor as shown in the equivalent circuit of Figure b, and can be used as a circuit element that operates with negative bias. Therefore, by using the present invention, an integrated circuit that conventionally required two bipolar power supplies can be operated with a single power supply. In addition, in the equivalent circuit of figure b, the symbol shown on each terminal indicates that it is a terminal drawn out from the electrode or region of figure a. Further, in FIG. 7, the region for collecting holes generated by high-energy electrons and the base region of the bipolar transistor are common, and a high-density integrated circuit is realized.

If channel regions 105A and 105B are formed as shown by dotted lines in FIG.
It also functions as a gate of a field effect transistor whose drains are 4A and 104B, and can be formed in common with the hole collecting region. In this case, area 101
Even if B is not a p-type semiconductor, the rectifying junction is connected to region 1.
00a (metal or 100a
and a semiconductor that forms a heterojunction). In order to operate this integrated circuit as a direct-coupled logic circuit, a gate region 101B and a source region (100
The impurity concentration and dimensional relationship is selected such that the channel region is depleted even when a+100b) is 0 bias.

FIG. 8 shows still another embodiment of the present invention, in which a region corresponding to the semiconductor region 100 in the explanatory diagram of FIG. A second region 102 of the same conductivity type as the main carrier is provided in contact with the region 101. Thin film 1 is provided in contact with region 101 . An example of this cross-sectional structure is shown in FIG. 8a, and a band diagram when the main carriers passing through the thin film 1 are electrons is shown in FIG. 8b. A bias is applied between the region 102 and the opposing region 10, and the main carrier from the opposing region 10 passes through the thin film 1 to the semiconductor region 10.
1, the energy level of the opposing region 10 and the region 10
When the difference between the band edges of 1 becomes larger than the forbidden band width of region 101, electrons and
Hole pairs are generated, and due to the carriers having the opposite polarity to the main carriers, the region 101, which was in a reverse bias state with respect to the region 102, is charged as shown in band diagram a, and becomes zero bias. It gets closer. As a result, the electric field in the thin film 1 is strengthened, so that more and more high-energy carriers are injected. At this time, if the distance of the region 101 sandwiched between the thin film 1 and the second region 102 is within the reach distance due to diffusion or drift of the main carrier of the thin film 1, the main carrier injected into the region 101 (region 1
01) reaches the second region 102, and as a result, once electron-hole pairs are generated in the structure shown in FIG. 8, a large current flows between the opposing region 10 and the second region. It flows between 102 and 102. Therefore, unless the external terminal is taken out from region 101, an element exhibiting current-controlled negative resistance or switch characteristics can be obtained.

Next, a configuration example of an integrated circuit to which the eighth illustrated embodiment is applied will be described.

The embodiment shown in FIG. 9 is a specific example in which the element shown in FIG. 8 is used in a memory cell, and FIG. 9a shows its cross-sectional configuration, b shows its equivalent circuit, and c shows its operating waveform.

In the case of this embodiment, a region 102 corresponding to the second region 102 of the eighth illustrated embodiment is configured as a semiconductor substrate, and has a conductivity type opposite to that of this region 102 and constitutes a semiconductor region. area 10
1 is a region formed on the surface of the semiconductor substrate 102, and is a common region with the drain of the insulated gate field effect transistor. Opposing region 10 is connected to resistive element R via wiring 10E, and the other end of R is connected to power supply voltage V _DD . The insulated gate 112 of an insulated gate field effect transistor (IGFET) is connected to the X-ray, and the source region 110 of the IGFET is connected to the Y-line to be selected as the XY address of the memory array on the matrix. The operation of this cell will be explained below. First, the IGFET is assumed to be a p-channel for simplicity. In this case, the thin film 1 is made of tunnelable thin (about 30 Å to 50 Å) SiO ₂ doped with impurities such as tungsten if necessary, and the thin film 10 may be a metal thin film,
An n-type semiconductor with a wide band gap, such as SnO ₂ , is even more effective. First, when the potential of the region 101 is closer to the power supply voltage than the substrate 102, it is set to "1", and when it is closer to the substrate voltage, it is set to "0". To write "0", first apply a suitable negative voltage to the gate of the IGFET, and when a voltage closer to the substrate is applied to the source, the region 101 also becomes a voltage close to the source voltage. In the element of the present invention composed of the region 10, the thin film 1, the region 101, and the region 102,
Since a large voltage is applied between the opposing region 10 and the region 101, electron-hole pairs are generated by the high-energy main carriers injected from the opposing region 10, and from then on, the high-energy carriers are R Since it is supplied from VDD through _VDD , the state persists even if the gate voltage is returned to a voltage that turns it off. Region 101 is held at a potential near substrate 102 . When writing “1”, if a potential close to V _DD is applied to the gate and source, region 1
01 has a similar potential, and even if high-energy carriers were injected before writing, it will be in a cutoff state, and even if the IGFET gate potential is returned to the off state, the region 101 will remain at a potential close to V _DD . It will be kept as is. Since the leakage current due to the reverse bias in regions 101 and 102 is supplied from V _DD through the thin film 1 through R, there is no need for a refresh operation as in a conventional dynamic memory. On the other hand, since the wafer occupancy area is approximately one transistor, a high-density static memory can be obtained. In order to reduce the power consumption during standby, it is normal to use an equivalently high-resistance element (or a micro-current element if the element exhibits constant current characteristics) for R, so it is relatively low in high-speed readout. Since a large current is read out, a so-called destructive readout is performed, resulting in a long cycle time. In order to avoid this, it is conceivable to insert an IGFET _OR in series between the opposing region 10 and V _DD as shown in FIG. 10 instead of the resistive element R. The resistive element R can be integrated in a small area using a thin polycrystalline Si film or the like formed on an insulating film, but in this case, a unit cell requires the area occupied by two transistors. However, the newly connected IGFET
By biasing the gate of _QR in the direction of lower resistance during reading, non-destructive reading becomes possible and high-speed operation can be achieved. Note that by forming a bipolar transistor with the region 101 as the collector in FIG. 9, a memory cell using the bipolar transistor as a selection element can be realized. The region 101 is shared with the drain or source of a field effect transistor, or
A high density memory cell can be provided by sharing the collector of a bipolar transistor.

Furthermore, as mentioned earlier, as a circuit structure including the device structure shown in FIG. 8, as shown in FIG. Insulated gates 121, 122,...1 provided through an insulating film to
27) and a third region 101D that is provided so as to partially overlap under the insulated gate when viewed in plan and forms a rectifying junction with the semiconductor region 100 can be exemplified.

In the case of such a structure, three insulated gates are shown in Figure 11 as an example, but if there is only one insulated gate, the electric field effect will change depending on the value of the bias applied to this insulated gate. Due to transistor operation, through the channel under the insulated gate,
Carriers of opposite polarity to the main carriers passing through the thin film 1 are selectively supplied to the depletion layer or inversion layer induced under the opposing region 10 from the third region 101D, or conversely, the depletion layer or inversion layer is induced under the opposing region 10. From the inversion layer,
A carrier of opposite polarity to the main carrier is placed in the third area 10.
It becomes possible to selectively extract to 1D.

Further, as shown in FIG.
1, 122, ... 127, by shifting the phase of the bias applied to each gate,
Through the CCD operation, a carrier having a polarity opposite to that of the main carrier passing through the thin film 1 is supplied from the third region 101D to the depletion layer or the inversion layer, or conversely, a carrier having a polarity opposite to that of the main carrier passing through the thin film 1 is supplied from the depletion layer or the inversion layer to the depletion layer or the inversion layer. It becomes possible to draw out carriers of opposite polarity to the third region 101D.

In particular, if the injection of high-energy carriers from the opposing region to the semiconductor region described above and the associated generation of electron-hole pairs on the surface of the semiconductor region are utilized,
It can also perform the functions summarized below. First, when the insulated gates 121, 122...127 are one continuous gate, the region 101
It operates as a unit cell of a memory array with D as a write/read line and an insulated gate as an address selection line. Second, the insulated gates 121, 122...127 are driven by appropriately phase-shifted pulses, and the CCD
By operating the device, a transfer signal can be stored in the device portion of the present invention comprising the facing region 10, the thin film 1, and the semiconductor region 100 without a refresh operation. Thirdly, in the device portion of the present invention,
The device of the present invention is turned on when a signal charge is sent by CCD operation and a predetermined amount of charge is accumulated, so that the number of signal charges can be counted, the frequency of the drive pulse can be divided, etc. Various useful functions can be realized.

In the above description of the specific example, electrons were used as the main carriers, but if holes were used, p and n in each semiconductor region could be exchanged, and the polarity of the bias could be reversed. It is clear that it is effective. Furthermore, areas 101B, 101
C, 101D, 102, etc. may be made of different materials as long as they have a rectifying junction with the semiconductor region 101
B, 101C, 102, etc. need only be within the reachable distance of the carrier from the surface of the semiconductor region under the opposing region.

According to the configuration of the present invention, not only the opposing region but also the crystallinity of the semiconductor region, which is one of the constituent requirements,
In designing the impurity concentration relationship, good device characteristics can be achieved by using a wider range of characteristics than in the past. In particular, memory elements, current or voltage current sources with new characteristics, switch elements that have common areas with conventional devices and realize high-density ICs,
Various distinctive devices and integrated circuits such as amplification elements, negative resistance elements, and bipolar transistors with high speed and low base resistance can be realized.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram related to the basic configuration of the present invention, FIG. 2 is a schematic configuration diagram of the first embodiment of the present invention, and FIG. 3 is an explanation of another operating principle that can be adopted in the present invention. 4 to 11 each show an embodiment of the present invention. In the figure, 1 is a thin film, 10 is an opposing region, and 100 is a semiconductor region.

Claims (1)

[Scope of Claims] 1. A semiconductor region; A counter region facing the semiconductor region; A material having a larger forbidden band width than the semiconductor region, and a material that is capable of transporting at least one carrier between the counter region and the semiconductor region. a thin film having such a small thickness that the transport is carried out through transport through the forbidden zone; a depletion layer or an inversion layer induced on the surface of the semiconductor region opposite to the opposing region with the thin film in between; What is claimed is: 1. A semiconductor device characterized in that it operates as a bipolar transistor, with the opposing region serving as an emitter, the depletion layer or inversion layer serving as a base, and the semiconductor region serving as a collector. 2. In the semiconductor device according to claim 1; the thin film has a barrier height lower than the main carrier when viewed from the opposing region, and a barrier height when viewed from the semiconductor region. A semiconductor device consisting of a material whose height is higher than that of the main carrier and the carrier of opposite polarity. 3. The semiconductor device according to claim 1, wherein carriers transported within the thin film are primarily of unipolar nature. 4. The semiconductor device according to claim 1, wherein the opposing region is a semiconductor region having a conductivity type having the same polarity as the polarity of the main carrier of the thin film. 5. In the semiconductor device according to claim 1; the semiconductor region includes a second region having a rectifying junction with the semiconductor region within a range where carriers can reach from the depletion layer or the inversion layer. provided,
A semiconductor device characterized in that the second region is a base contact region. 6. A semiconductor region; A counter region facing the semiconductor region; A material having a wider forbidden band width than the semiconductor region, and at least a part of carrier transport between the counter region and the semiconductor region is within the forbidden band. injecting high-energy carriers greater than the energy gap of the semiconductor region from the opposing region into the semiconductor region, thereby increasing the surface of the semiconductor region; a bias means for generating electron-hole pairs; and a bias means for generating electron-hole pairs; A semiconductor device with functions. 7. In the semiconductor device according to claim 6; the thin film has a barrier height lower than the main carrier when viewed from the opposing region, and a barrier height when viewed from the semiconductor region. A semiconductor device consisting of a material whose height is higher than that of the main carrier and the carrier of opposite polarity. 8. The semiconductor device according to claim 6, wherein carriers transported within the thin film are primarily of unipolar nature. 9. The semiconductor device according to claim 6, wherein the opposing region is a semiconductor region having a conductivity type having the same polarity as the polarity of the main carrier of the thin film. 10. In the semiconductor device according to claim 6; the semiconductor region has a second region having a rectifying junction with the semiconductor region within a range that a carrier can reach from a surface portion facing the opposing region. A semiconductor device characterized in that a region is provided. 11. The semiconductor device according to claim 6, wherein the semiconductor region is used as a region for controlling switching characteristics between the opposing region and the second region. 12. The semiconductor device according to claim 6, wherein the second region is used as a region for controlling switching characteristics between the opposing region and the semiconductor region. 13. In the semiconductor device according to claim 6; the second region generates a voltage with an opposite sign to the voltage applied to the opposing region with respect to the semiconductor region, or generates a current. Semiconductor devices are an area where 14. In the semiconductor device according to claim 6; the second region is used as a common region with a gate of a junction field effect transistor, or the second region is a semiconductor of a conductivity type opposite to that of the semiconductor region. A semiconductor device characterized in that the region is used as a common region with a base of a bipolar transistor. 15. In the semiconductor device according to claim 6; the semiconductor region is used as a common region with a drain or a source of a field effect transistor, or
Or a semiconductor device characterized in that it is used as a common region with the collector of a bipolar transistor. 16 a semiconductor region; a counter region facing the semiconductor region; a material having a wider forbidden band width than the semiconductor region, and at least a portion of carrier transport between the counter region and the semiconductor region is within the forbidden band; a thin film of such a thin thickness as to be carried out by transport through the opposing region;
and an insulated gate provided on the surface of the semiconductor region with an insulating film interposed therebetween; and a third region provided partially overlapping with the insulated gate and forming a rectifying junction with the semiconductor region. A semiconductor device comprising: and; 17. The semiconductor device according to claim 16, wherein the insulated gate includes a plurality of insulated gates whose adjacent portions are insulated from each other.