JPH0262106A - Operational amplifier - Google Patents

Operational amplifier

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Publication number
JPH0262106A
JPH0262106A JP63213959A JP21395988A JPH0262106A JP H0262106 A JPH0262106 A JP H0262106A JP 63213959 A JP63213959 A JP 63213959A JP 21395988 A JP21395988 A JP 21395988A JP H0262106 A JPH0262106 A JP H0262106A
Authority
JP
Japan
Prior art keywords
output
terminal
current
transistor
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63213959A
Other languages
Japanese (ja)
Other versions
JP2900373B2 (en
Inventor
Toshihiko Ichise
俊彦 市瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63213959A priority Critical patent/JP2900373B2/en
Publication of JPH0262106A publication Critical patent/JPH0262106A/en
Application granted granted Critical
Publication of JP2900373B2 publication Critical patent/JP2900373B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain a sufficient output voltage for operation by outputting from a positive power source to an output terminal, when the output voltage is positive, by a first current mirror circuit and outputting from an output edge terminal to a negative power source by a second current mirror circuit when the output voltage is negative. CONSTITUTION:By the function of a polarity identifying circuit, and when the output electric power positive, by the function of a first current mirror circuit 9, the current flows from a supply voltage VDD to an output terminal. When the output voltage is negative, the current flows from output terminal to a negative input terminal VSS by the function of a second mirror circuit. When the potential of a positive input terminal 1 is higher than the potential of a negative input terminal 2, a transistor TR Q15 is conducted, TR Q17 is off and an output terminal 3 is lifted up to a positive supply voltage VDD side. At this time, TR Q7 is on, and through a resistance R16 to the circuit 9, the current flows. At the collector of TR Q22, the current of the product of the emitter area ratio of TR Q21 and Q22 and the collector current of TR Q21 flows, and the output terminal 3 is also lifted up to a VDD side. In the same way, when the potential of the negative input terminal 2 is higher than the potential of the terminal 1, the output is shifted to the VSS side.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は集積回路に使用される演算増幅器に関すするも
のであり、特に出力電圧が正の電源電圧から負の電源電
圧まで可変する事ができる演算増幅器に関する。
[Detailed Description of the Invention] Industrial Application Field The present invention relates to an operational amplifier used in an integrated circuit, and particularly to an operational amplifier whose output voltage can be varied from a positive power supply voltage to a negative power supply voltage. Regarding amplifiers.

従来の技術 従来の演算増幅器の回路の一例を第2図に示す。Conventional technology An example of a conventional operational amplifier circuit is shown in FIG.

第2図においてQ1〜Q、8.R,〜R++は演算増幅
器を講成するトランジスタと抵抗であり1は(→入力端
子、2は(ハ)入力端子、3は出力端子、4はプラス電
源端子(以下”vDD”と略す)、5はマイナス電源端
子(以下”vss”と略す)、6は接地端子(以下GN
Dと略す)である。
In FIG. 2, Q1 to Q, 8. R, ~R++ are transistors and resistors that form the operational amplifier; 1 is the (→input terminal), 2 is the (c) input terminal, 3 is the output terminal, 4 is the positive power supply terminal (hereinafter abbreviated as "vDD"), 5 is a negative power supply terminal (hereinafter abbreviated as "vss"), 6 is a ground terminal (hereinafter GN
(abbreviated as D).

発明が解決しようとする課題 この様な従来の演算増幅器では出力端子3のとることの
可能な電圧範囲は、 Vn  =vnn  (vcxSatQ7+VagQ+
s)   からvL  =vSS + vax”tQ1
6+VBzQ17  tテテhる。
Problems to be Solved by the Invention In such a conventional operational amplifier, the possible voltage range of the output terminal 3 is Vn = vnn (vcxSatQ7+VagQ+
s) from vL = vSS + vax”tQ1
6+VBzQ17

ただし、Vo、satとはトランジスタのコレクタエミ
ッタ間の飽和電圧、vBxとはベース、エミッタ間の順
方向電圧降下を意味する。
However, Vo and sat mean the saturation voltage between the collector and emitter of the transistor, and vBx means the forward voltage drop between the base and emitter.

仮りにVC,satを0.2V、Voを0.7 vとす
ると従来の演算増幅器の出力電圧はV、D−0,9”/
からvss + 0.9 Vまテトなルタメ特ニvDD
、vssカ低い電圧の場合、出力電圧が十分得られない
ことがあった。
If VC,sat is 0.2V and Vo is 0.7V, the output voltage of the conventional operational amplifier is V,D-0,9''/
From vss + 0.9 V
, vss. When the voltage is low, a sufficient output voltage may not be obtained.

本発明はこのような問題を解決するもので、電源電圧が
低くても十分な出力電圧が得られるようにすることを目
的とする。
The present invention is intended to solve such problems, and aims to enable a sufficient output voltage to be obtained even when the power supply voltage is low.

課題を解決するだめの手段 上記問題点を解決するだめの本発明の技術的手段は、極
性の異なる第1.第2のトランジスタのエミッタをそれ
ぞれ接地端子に接続すると共に両方のベースを抵抗を介
して出力端子に接続しかつ出力電圧が接地電位に対し正
の時第1のトランジスタが導通し負の時第2のトランジ
スタが導通する極性識別回路と、上記第1のトランジス
タのコレクタと抵抗を介して接続され第1のトランジス
タのコレクタ電流を正の電源電圧に対しミラーさせる第
1のカレントミラー回路と、上記第2のトランジスタの
コレクタと抵抗を介して接−統され第2のトランジスタ
のコレクタ電流を負の電源電圧に対しミラーさせる第2
のカレントミラー回路とを具備し、第1.第2のカレン
トミラー回路の出力側の端子を出力端子に接続するもの
である。
Means for Solving the Problems The technical means of the present invention for solving the above problems are as follows: The emitters of the second transistors are respectively connected to the ground terminal, and both bases are connected to the output terminal via a resistor, and when the output voltage is positive with respect to the ground potential, the first transistor conducts, and when the output voltage is negative, the second transistor conducts. a first current mirror circuit connected to the collector of the first transistor via a resistor and mirroring the collector current of the first transistor with respect to a positive power supply voltage; A second transistor is connected to the collector of the second transistor via a resistor and mirrors the collector current of the second transistor with respect to the negative power supply voltage.
a current mirror circuit; The output side terminal of the second current mirror circuit is connected to the output terminal.

作用 この構成によって通常の演算増幅器では先に従来例で説
明した通り出力電圧はvno  0.9Vからvs s
 + 0.9 Vまでしか出力できないが、極性識別回
路の働きによって出力電圧が正の時は第1のカレントミ
ラー回路の働きにより出力端子へVDDから電流が流れ
る。また出力電圧が負の時は第2のカレントミラー回路
の働きによって出力端子からvs8へ向かって電流が流
れる。出力端子に接続される負荷のインピーダンスが大
きく負荷電流が第1、第2のカレントミラー回路の出力
電流よりも少なければ、出力端子電圧はほぼvDI、か
らVSSまで出力することができる。
Operation With this configuration, in a normal operational amplifier, the output voltage varies from vno 0.9V to vss as explained in the conventional example earlier.
Although it can only output up to +0.9 V, when the output voltage is positive due to the function of the polarity identification circuit, current flows from VDD to the output terminal due to the function of the first current mirror circuit. Further, when the output voltage is negative, a current flows from the output terminal toward vs8 due to the action of the second current mirror circuit. If the impedance of the load connected to the output terminal is large and the load current is smaller than the output currents of the first and second current mirror circuits, the output terminal voltage can be output from approximately vDI to VSS.

実施例 以下本発明の一実施例を第1図を用いて説明する。Example An embodiment of the present invention will be described below with reference to FIG.

第1図において第2図と同一機能を有する素子には同一
符号を付して説明を省略する。了は極性識別回路を構成
する第1のトランジスタ、8は同じく第2のトランジス
タ、9は第1のカレントミラー回路、1Qは第2のカレ
ントミラー回路である。(イ)入力端子1の電位が(へ
)入力端子2の電位より高い時にはトランジスタQ+5
が導通(以下ONと記す)、トランジスタQI7が遮断
(以下OFFと記す)し出力端子3はvD、側にもち上
がる。この時第1のトランジスタ7がONし、第1のカ
レントミラー9に抵抗R,を通して電流が流れる。
In FIG. 1, elements having the same functions as those in FIG. 2 are denoted by the same reference numerals, and explanations thereof will be omitted. Reference numeral 8 indicates a first transistor constituting a polarity identification circuit, 8 a second transistor, 9 a first current mirror circuit, and 1Q a second current mirror circuit. (a) When the potential of input terminal 1 is higher than the potential of input terminal 2, transistor Q+5
is conductive (hereinafter referred to as ON), transistor QI7 is cut off (hereinafter referred to as OFF), and the output terminal 3 rises to the VD side. At this time, the first transistor 7 is turned on, and current flows through the first current mirror 9 through the resistor R.

トランジスタQ2□のコレクタにはトランジスタQ2+
のエミッタ面積とトランジスタQ22のエミッタ面積の
比とトランジスタQ)Hのコレクタ電流の積の電流が流
れようとするため、出力端子3をさらにVDD側にもち
上げ負荷インピーダンスが大きければ出力端子電圧はv
DD−vOIIQ2□#vDD となる。同様に(ハ)
入力端子2の電位が(イ)入力端子1の電位より高い時
にはトランジスタQj7がOWLトランジスタQ+5が
OFFすることにより出力端子電圧はvss側になりこ
れによって第2のトランジスタ8がONL、、第2のカ
レントミラー10に抵抗R47を介して電流が流れ、4
トランジスタQ25のコレクタ電流によって出力端子3
の電圧はほぼVSSまで下げることができる。
Transistor Q2+ is connected to the collector of transistor Q2□.
Since a current equal to the product of the ratio of the emitter area of , the emitter area of transistor Q22, and the collector current of transistor Q)H will flow, if the output terminal 3 is further raised to the VDD side and the load impedance is large, the output terminal voltage will be v.
DD-vOIIQ2□#vDD. Similarly (c)
When the potential of the input terminal 2 is higher than the potential of the input terminal 1 (a), the transistor Qj7 is OWL.The transistor Q+5 is turned off, and the output terminal voltage becomes the vss side. A current flows through the current mirror 10 through the resistor R47, and 4
Output terminal 3 due to the collector current of transistor Q25.
The voltage can be lowered to approximately VSS.

尚この演算増幅器に負帰還を付加しリニア増幅器とした
場合の動作は出力端子3の電圧がVDD側の時にはトラ
ンジスタQ2□のコレクタ電流をトランジスタQj7の
エミッタ電流が吸い込んで出力端子電圧がリニアに制御
される。また、出力端子3の電圧がvss側の時にはト
ランジスタQ25のコレクタ電流をトランジスタQi5
のエミッタ電流が制御し、出力端子電圧がリニアに制御
される。
Note that when negative feedback is added to this operational amplifier to make it a linear amplifier, the operation is such that when the voltage at the output terminal 3 is on the VDD side, the emitter current of the transistor Qj7 absorbs the collector current of the transistor Q2□, and the output terminal voltage is controlled linearly. be done. Furthermore, when the voltage of the output terminal 3 is on the vss side, the collector current of the transistor Q25 is changed to the transistor Qi5.
emitter current is controlled, and the output terminal voltage is linearly controlled.

発明の効果 以上のように本発明は、出力端子電圧がvDDがらvs
sまでのいかなる電圧をも出力することが可能な演算増
幅器とすることができる。
Effects of the Invention As described above, the present invention has the advantage that the output terminal voltage varies from vDD to vs
It can be an operational amplifier capable of outputting any voltage up to s.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の演算増幅器の回路図、第2
図は従来の演算増幅器の回路図である。 1・・・・・・(イ)入力端子、2・・・・・・(ハ)
入力端子、3・・・・・・出力端子、4・・・・・プラ
ス電源端子(vDD)、6・・・・・マイナス電源端子
(vss )、6・・・接地端子、了・・・・・・第1
のトランジスタ、8・・・・第2のトランジスタ、9・
・・°・第1のカレントミラー 10・・・・・・第2
のカレントミラー
FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram of a conventional operational amplifier. 1...(A) Input terminal, 2...(C)
Input terminal, 3... Output terminal, 4... Plus power terminal (vDD), 6... Negative power terminal (vss), 6... Ground terminal, End... ...First
transistor, 8... second transistor, 9.
...°・First current mirror 10...Second
current mirror of

Claims (1)

【特許請求の範囲】[Claims] 極性の異なる第1、第2のトランジスタのエミッタをそ
れぞれ接地端子に接続すると共に両方のベースを抵抗を
介して出力端子に接続しかつ出力電圧が接地電位に対し
正の時第1のトランジスタが導通し負の時第2のトラン
ジスタが導通する極性識別回路と、上記第1のトランジ
スタのコレクタと抵抗を介して接続され第1のトランジ
スタのコレクタ電流を正の電源電圧に対しミラーさせる
第1のカレントミラー回路と、上記第2のトランジスタ
のコレクタに抵抗を介して接続され第2のトランジスタ
のコレクタ電流を負の電源電圧に対しミラーさせる第2
のカレントミラー回路とを具備し、第1、第2のカレン
トミラー回路の出力側の端子を出力端子に接続した演算
増幅器。
The emitters of the first and second transistors having different polarities are connected to the ground terminal, and both bases are connected to the output terminal via a resistor, and when the output voltage is positive with respect to the ground potential, the first transistor is conductive. and a first current connected to the collector of the first transistor via a resistor to mirror the collector current of the first transistor with respect to the positive power supply voltage. a mirror circuit, and a second transistor connected to the collector of the second transistor via a resistor to mirror the collector current of the second transistor with respect to the negative power supply voltage.
an operational amplifier, comprising: a current mirror circuit; and the output terminals of the first and second current mirror circuits are connected to the output terminal.
JP63213959A 1988-08-29 1988-08-29 Operational amplifier Expired - Fee Related JP2900373B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63213959A JP2900373B2 (en) 1988-08-29 1988-08-29 Operational amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63213959A JP2900373B2 (en) 1988-08-29 1988-08-29 Operational amplifier

Publications (2)

Publication Number Publication Date
JPH0262106A true JPH0262106A (en) 1990-03-02
JP2900373B2 JP2900373B2 (en) 1999-06-02

Family

ID=16647895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63213959A Expired - Fee Related JP2900373B2 (en) 1988-08-29 1988-08-29 Operational amplifier

Country Status (1)

Country Link
JP (1) JP2900373B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117709A (en) * 1990-09-03 1992-04-17 Nec Ic Microcomput Syst Ltd Constant current circuit
US6064525A (en) * 1997-03-25 2000-05-16 Glaverbel Optical device including a dichromatic mirror
JP2014175983A (en) * 2013-03-12 2014-09-22 Toyota Central R&D Labs Inc Amplification circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04117709A (en) * 1990-09-03 1992-04-17 Nec Ic Microcomput Syst Ltd Constant current circuit
US6064525A (en) * 1997-03-25 2000-05-16 Glaverbel Optical device including a dichromatic mirror
JP2014175983A (en) * 2013-03-12 2014-09-22 Toyota Central R&D Labs Inc Amplification circuit

Also Published As

Publication number Publication date
JP2900373B2 (en) 1999-06-02

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