JPH0262022A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH0262022A
JPH0262022A JP21332488A JP21332488A JPH0262022A JP H0262022 A JPH0262022 A JP H0262022A JP 21332488 A JP21332488 A JP 21332488A JP 21332488 A JP21332488 A JP 21332488A JP H0262022 A JPH0262022 A JP H0262022A
Authority
JP
Japan
Prior art keywords
dielectric
layer
laminated
surface layer
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21332488A
Other languages
Japanese (ja)
Inventor
Toshiki Nishiyama
俊樹 西山
Yoshiaki Kono
芳明 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP21332488A priority Critical patent/JPH0262022A/en
Publication of JPH0262022A publication Critical patent/JPH0262022A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To make a surface layer dense, to harden the layer without changing the composition material and to prevent this layer from being broken or chipped off by an external force by a method wherein the particle diameter of the laminated surface layer of a dielectric ceramic is made smaller than the particle diameter inside the layer. CONSTITUTION:Internal electrodes 3 are buried to be layer-like between a plurality of laminated dielectric ceramics 2; these are sandwiched between dielectric ceramics 2 which do not have the electrodes 3; a laminated dielectric 1 is formed. A particle diameter of a surface layer of the ceramics 2 is made smaller than a particle diameter at the inside. It is preferable that the surface of the dielectric 1 having the electrodes 3 is coated with a paste containing a rare-earth oxide and is baked. Then, only the surface layer can be made dense and hardened without changing a composition material. Thereby, it is possible to prevent the layer from being broken or chipped off by an external force.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、誘電体セラミックの間に内部電極を埋設した
積層セラミックコンデンサに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multilayer ceramic capacitor in which internal electrodes are embedded between dielectric ceramics.

従来の技術 積層セラミックコンデンサは、誘電体セラミックの間に
内部電極を層状に埋設して積層誘電体を形成し、さらに
この積層誘電体の両端に外部電極を配設したものが一般
である。
Conventional multilayer ceramic capacitors generally have internal electrodes embedded in layers between dielectric ceramics to form a multilayer dielectric, and external electrodes are disposed at both ends of the multilayer dielectric.

また、この積層セラミックコンデンサは、近時実装効率
を高めるためにチップ型とされて非常に小型化されてお
り、さらに、最近の表面実装技術の進歩に伴い、配線用
基板に対して自動実装により直付けされている。
In addition, these multilayer ceramic capacitors have recently been made into chip-type and extremely miniaturized to increase mounting efficiency.Furthermore, with recent advances in surface mounting technology, they have been automatically mounted on wiring boards. Directly attached.

明が解決しようとする課題 しかし、この種の積層セラミックコンデンサを配線用基
板に実装すると、チッピングが生じて劣化が早まり、電
気的特性も変化するという不具合があった。即ち、自動
実装装置によりコンデンサを挾持して基板に半田付けす
る際、把持力が強すぎると耐チッピング性、つまり衝撃
等の外力に対する強度に劣るコンデンサの表面に欠けや
クラック等の損傷が生しる。また、配線用基板が、半田
付は時の熱や実装された際の熱ストレスを受けると、僅
かながらも変形してそりが生じる。このとき、基板に直
付けされた積層セラミックコンデンサに対して曲げ応力
が作用し、機械的強度に劣る従来の積層セラミックコン
デンサにおいては、その表面に割れや欠けが生じ、所謂
チッピングが発生する。また、このチッピングにより誘
電率が変化して、静電容量が低下する等の問題点もあっ
た。
Problems that Ming was trying to solve However, when this type of multilayer ceramic capacitor was mounted on a wiring board, there were problems such as chipping, accelerated deterioration, and changes in electrical characteristics. In other words, when an automatic mounting device grips a capacitor and solders it to a board, if the gripping force is too strong, damage such as chips or cracks may occur on the surface of the capacitor, which has poor chipping resistance, that is, strength against external forces such as shock. Ru. Furthermore, when the wiring board is subjected to heat during soldering or thermal stress during mounting, it deforms and warps, albeit slightly. At this time, bending stress acts on the multilayer ceramic capacitor directly attached to the substrate, and in conventional multilayer ceramic capacitors having poor mechanical strength, cracks and chips occur on the surface, causing so-called chipping. Furthermore, this chipping causes a change in dielectric constant, resulting in a decrease in capacitance.

そこで、前記積層誘電体を耐チッピング性に優れた材料
にて組成し、積層セラミックコンデンサ全体の機械的強
度を高めることが試みられている。
Therefore, attempts have been made to compose the laminated dielectric with a material having excellent chipping resistance to increase the mechanical strength of the entire laminated ceramic capacitor.

しかし、積層誘電体の組成が変更されると、誘電率等の
電気的特性も変化するため、その改質には限界がある。
However, when the composition of the laminated dielectric is changed, electrical properties such as dielectric constant also change, so there is a limit to its modification.

また、耐チッピング性を高める材料は、積層誘電体の組
成に適合きせる必要があり、多品種の積層セラミックコ
ンデンサに共通して適用し得るものではなく、その応用
範囲は極めて狭いものである。
Furthermore, the material that improves chipping resistance must be compatible with the composition of the laminated dielectric, and cannot be commonly applied to a wide variety of laminated ceramic capacitors, so its range of application is extremely narrow.

この点に鑑み、近時、積層セラミックコンデンサをバレ
ル研摩する方法が採用されている。これは、亀裂や割れ
の発生し易い積層セラミックコンデンサの稜線部分を面
取りすることによって、耐チッピング性や抗折強度等の
機械的強度を高めようとするものである。なお、製作に
際しては、焼成後の積層誘電体セラミックを被研摩材と
する一方、ZrO,等の粉末を研摩材として容器に投入
し、この容器を振動もしくは回転させ、誘電体セラミッ
クの表面を研摩している。
In view of this point, a method of barrel polishing multilayer ceramic capacitors has recently been adopted. This is intended to improve mechanical strength such as chipping resistance and bending strength by chamfering the ridgeline portions of multilayer ceramic capacitors where cracks and cracks are likely to occur. In addition, during manufacturing, while the laminated dielectric ceramic after firing is used as the material to be polished, powder such as ZrO is put into a container as an abrasive material, and the container is vibrated or rotated to polish the surface of the dielectric ceramic. are doing.

しかし、この様にして得られた積層セラミックコンデン
サは、抗折強度を若干向上させ得るものの電気的特性が
逆に低下する等、好ましい効果を得がたい。即ち、バレ
ル研摩は、表面の仕上げが容器の回転速度や回転時間に
大きく影響される。
However, although the multilayer ceramic capacitor obtained in this manner may have slightly improved bending strength, it is difficult to obtain desirable effects such as deterioration of electrical characteristics. That is, in barrel polishing, the surface finish is greatly affected by the rotation speed and rotation time of the container.

例えば、回転時間が短い場合、被研摩材である積層誘電
体セラミックの研摩量が少なくなって稜線部分の面取り
が充分に行なわれず、抗折強度が低下する。一方、回転
時間が長くなると必要以上に研摩がなされ、稜線部分の
みならず積層誘電体セラミックの表面が深く削り取られ
、抗折強度が逆に低下するうえ、静電容量も変化すると
いう問題を生じていた。この様に、バレル研摩による方
法は、電気的特性に影響を与えず最適な研摩を行なうこ
とが難しく、しかもコンデンサの品種、形状、数量等に
よって微調節が必要であることから、積層セラミックコ
ンデンサの製作効率も極めて低い。
For example, if the rotation time is short, the amount of polishing of the laminated dielectric ceramic material to be polished will be reduced, and the ridgeline portions will not be chamfered sufficiently, resulting in a decrease in bending strength. On the other hand, if the rotation time becomes longer, polishing will be performed more than necessary, and not only the ridgeline portion but also the surface of the laminated dielectric ceramic will be deeply scraped off, causing problems such as a decrease in bending strength and a change in capacitance. was. In this way, with the barrel polishing method, it is difficult to perform optimal polishing without affecting the electrical characteristics, and furthermore, it requires fine adjustment depending on the type, shape, quantity, etc. of the capacitor, so Production efficiency is also extremely low.

本発明は、前記問題点に鑑みてなされたもので、電気的
特性を低下させずに、抗折強度及び耐チッピング性を高
め、しかも多品種の積層誘電体にも適用可能し得る様に
改質された積層セラミックコンデンサを提供することを
課題としている。
The present invention has been made in view of the above-mentioned problems, and has been improved to improve bending strength and chipping resistance without deteriorating electrical characteristics, and to be applicable to a wide variety of laminated dielectrics. Our goal is to provide high-quality multilayer ceramic capacitors.

課題を解決するための手段 以上の課題を解決するため、本発明に係る積層セラミッ
クコンデンサは、積層誘電体セラミックの表面層の粒子
径が内部の粒子径よりも小径であることを特徴とする。
Means for Solving the Problems In order to solve the above problems, the multilayer ceramic capacitor according to the present invention is characterized in that the particle size of the surface layer of the multilayer dielectric ceramic is smaller than the particle size inside.

好ましくは、内部電極を有する積層誘電体の表面に希土
類酸化物を含むペーストを塗布して焼成する。
Preferably, a paste containing a rare earth oxide is applied to the surface of the laminated dielectric having internal electrodes and then fired.

作−一用 以上の構成により、積層された誘電体セラミックの表面
層は、粒子径がその内部よりも小径とされていることか
ら、組成材料に変更なく表面層のみ緻密化、硬化されて
いる。従って、コンデンサとしての電気的特性が低下す
ることなく、耐チッピング性や抗折強度が高められ、外
力による割れや欠は等の発生が防止され、長寿命を維持
する。
Due to the above configuration, the particle size of the surface layer of the laminated dielectric ceramic is smaller than that of the inside, so only the surface layer is densified and hardened without changing the composition material. . Therefore, the chipping resistance and bending strength are increased without deteriorating the electrical characteristics as a capacitor, and the occurrence of cracks, chips, etc. due to external forces is prevented, and a long life is maintained.

実施例 以下、本発明の実施例を図面に基づいて説明する。Example Embodiments of the present invention will be described below based on the drawings.

本発明に係る積層セラミックコンデンサは、第1図に示
す様に、積層きれた複数枚の誘電体セラミック2の間に
、内部電極3を層状に埋設し、これらを内部電極を有し
ない誘電体セラミック2a。
As shown in FIG. 1, the multilayer ceramic capacitor according to the present invention has internal electrodes 3 embedded in a layered manner between a plurality of laminated dielectric ceramics 2, and a dielectric ceramic having no internal electrodes. 2a.

2aにて挾んで積層誘電体1を形成している。さらに、
両端に外部電極4,4を配設した構成とされている。な
お、この積層セラミックコンデンサは、以下の工程順に
製作されるが、直方体で小形のチップ型とすることによ
り、配線用基板に対し半田を介して直付は接読が可能で
ある。
A laminated dielectric 1 is formed by sandwiching the two layers at 2a. moreover,
It has a configuration in which external electrodes 4, 4 are provided at both ends. This multilayer ceramic capacitor is manufactured in the following process order, and by making it a rectangular parallelepiped and small chip type, it can be directly attached to a wiring board via solder and can be read directly.

次に、製造工程を第2図ないし第4図に従って説明する
Next, the manufacturing process will be explained according to FIGS. 2 to 4.

まず、グリーンシートを作成する。ここでは、粉末状の
BaTi0m : 84.35mo1%にBaZr0m
 : 15.65mo1%を加えたもの100wt%に
対し、MnC0,を0.07wt%の割合で添加して混
合する。そして、これら原料粉末にバインダとしてPV
A(ポリビニルアルコール)を用いると共に、界面活性
剤、分散剤及び水等を加えて混練し、スラリーを得る。
First, create a green sheet. Here, BaZr0m was added to powdered BaTi0m: 84.35mol1%.
: MnC0 is added at a ratio of 0.07 wt% to 100 wt% of 15.65 mo1% and mixed. Then, PV is added to these raw powders as a binder.
Using A (polyvinyl alcohol), a surfactant, a dispersant, water, etc. are added and kneaded to obtain a slurry.

続いて、このスラリーをドクターブレード法によりシー
ト状に形成し、厚み35μmのグリーンシートとする。
Subsequently, this slurry is formed into a sheet by a doctor blade method to obtain a green sheet with a thickness of 35 μm.

この後、各グリーンシートを乾燥し、その−面には、内
部電極3が形成される。この内部電極は、パラジウムや
銀等の金属粉末に適当なバインダを混入したものを前記
各グリーンシート上に印刷した後乾燥する。そして、こ
のグリーンシートは、所要の静電容量に応じて複数枚が
積み重ねられ、内部電極を有しないグリーンシートにて
挾んだ状態でプレス圧着する。続いて、第2図に示す如
く、積層したグリーンシートを所定サイズにカットし、
積層誘電体1を得る。
Thereafter, each green sheet is dried, and internal electrodes 3 are formed on its negative side. The internal electrodes are made by printing a mixture of metal powder such as palladium, silver, or the like with a suitable binder on each of the green sheets, and then drying it. A plurality of green sheets are stacked according to the required capacitance, and the green sheets are pressed together while being sandwiched between green sheets having no internal electrodes. Next, as shown in Figure 2, the laminated green sheets are cut to a predetermined size.
A laminated dielectric 1 is obtained.

次に、第3図に示す如く、積層誘電体1の表面に酸化物
を塗布する。この酸化物としてはDy!Oa、CeOz
、Sm、O,、Gd、O,等の希土類酸化物から少なく
とも一種類が選択される。そして、この酸化物30吐%
にエチルセルロースとブチルセロソルブアセテートとを
加えてペースト状にし、このペーストを前記積層誘電体
1の上下面に塗布する。続いて、この積層誘電体1を乾
燥した後、1300°Cで2時間焼成する。この後、前
記積層誘電体1の両端面に導電性ペーストが塗布、焼付
けられ、外部電極4゜4が形成きれ、第1図に示す積層
セラミックコンデンサが構成される。
Next, as shown in FIG. 3, an oxide is applied to the surface of the laminated dielectric 1. As this oxide, Dy! Oa, CeOz
, Sm, O, , Gd, O, and the like. And this oxide 30%
Ethyl cellulose and butyl cellosolve acetate are added to make a paste, and this paste is applied to the upper and lower surfaces of the laminated dielectric 1. Subsequently, this laminated dielectric 1 is dried and then fired at 1300°C for 2 hours. Thereafter, a conductive paste is applied and baked on both end faces of the laminated dielectric 1 to complete the formation of external electrodes 4.4, thereby constructing the laminated ceramic capacitor shown in FIG. 1.

この様にして得られた積層セラミックコンデンサは、下
記の通りである。
The multilayer ceramic capacitor thus obtained is as follows.

外形寸法 幅:       1.6mm長さ:   
     3.2mm 厚さ:        1.2mm セラミック単位厚き:20μm −層当りの対向型極面積:   1.3mm2誘電体内
部層の平均粒径:4.5μm 誘電体表面層の平均粒径:2.5μm なお、前記平均粒径は、走査型電子顕微鏡による目視観
察により測定したもので、表面層の粒子径が内部層より
も小径であることが明らかとなった。これは、前記酸化
物がセラミック表面層の結晶の成長を抑制するためであ
ると考えられる。
External dimensions Width: 1.6mm Length:
3.2 mm Thickness: 1.2 mm Ceramic unit thickness: 20 μm - Opposed pole area per layer: 1.3 mm2 Average grain size of dielectric inner layer: 4.5 μm Average grain size of dielectric surface layer: 2. 5 μm The above average particle size was measured by visual observation using a scanning electron microscope, and it became clear that the particle size of the surface layer was smaller than that of the inner layer. This is thought to be because the oxide suppresses the growth of crystals in the ceramic surface layer.

次に、この積層セラミックコンデンサの耐チッピング性
、抗折強度及び電気的特性を知るために、従来品を比較
例として同一条件の下に試験を行なった。この試験に際
しては、重量や形状の等しい積層セラミックコンデンサ
を試料とし、それぞれ同−個数用いている。
Next, in order to find out the chipping resistance, bending strength, and electrical characteristics of this multilayer ceramic capacitor, a conventional product was used as a comparative example and tested under the same conditions. In this test, monolithic ceramic capacitors having the same weight and shape were used as samples, and the same number of capacitors were used.

まず、耐チッピング性の試験に際しては、積層セラミッ
クコンデンサに衝撃力を加えた際に生じる割れや欠は等
の欠損を知るために、各100個の積層セラ、ミックコ
ンデンサを250m1の塩化ビニル製のポットに投入し
、約16時間回転した後、重量を測定して各試料の重量
減(%)を求めた。この重量減を求める式は下記のとお
りである。
First, in the chipping resistance test, in order to detect defects such as cracks and chips that occur when impact force is applied to multilayer ceramic capacitors, 100 multilayer ceramic capacitors and 100 microcapacitors were each placed in a 250 m1 vinyl chloride capacitor. After the samples were placed in a pot and rotated for about 16 hours, the weight was measured to determine the weight loss (%) of each sample. The formula for determining this weight loss is as follows.

試験(二点支持中央集中荷重)を行なった。A test (two-point support central concentrated load) was conducted.

さらに、電気的特性の測定に際しては、積層セラミック
コンデンサの静電容量(C)及び誘電損失(tanδ)
を知るために、まず、自動ブリッジ式測定器を用い、各
試料に1 kHz、I Vrmsの電圧を印加した。次
に、絶縁抵抗(R)を測定するために、絶縁抵抗計を用
いて50Vの電圧を60秒間印加し、そのCR積(Ω・
F)を測定した。
Furthermore, when measuring the electrical characteristics, the capacitance (C) and dielectric loss (tan δ) of the multilayer ceramic capacitor are
To find out, first, a voltage of 1 kHz, I Vrms was applied to each sample using an automatic bridge measuring device. Next, to measure the insulation resistance (R), a voltage of 50V was applied for 60 seconds using an insulation resistance meter, and the CR product (Ω・
F) was measured.

以上の試験による測定結果は表の通りである。The measurement results from the above tests are shown in the table.

[以下余 白コ 次に、抗折強度の試験に際しては、内部電極を埋設して
いない焼結済みの誘電体に荷重を加えた場合に亀裂が生
じた時を降伏点として、その際の荷重を測定した。なお
、ここでは試験片として外形寸法が厚さ3mm、幅4m
m、長さ40mmの長方形の焼結済みの誘電体を各5個
用意し、バレル研摩にて表面仕上げした後、抗折試験機
により三点曲げ前記表から理解される様に、本発明例の
積層セラミックコンデンサは、電気的特性に殆ど影響な
く、機械的強度のみ高められることが明らかとなった。
[Leave below]Next, when testing the flexural strength, the yield point is defined as the point at which a crack occurs when a load is applied to a sintered dielectric material without embedded internal electrodes, and the load at that time is determined as the yield point. was measured. In addition, the outer dimensions of the test piece used here are 3 mm thick and 4 m wide.
Five rectangular sintered dielectrics each having a length of 40 mm were prepared, and after the surface was finished by barrel polishing, three-point bending was performed using a bending tester. As can be understood from the above table, the present invention example It has become clear that the multilayer ceramic capacitor of 2008 has only improved mechanical strength, with almost no effect on electrical characteristics.

即ち、電気的特性として静電容1t(C)は、比較例及
び本発明例共に0.14μFであり、誘電損失(tan
s)は僅かに本発明例が0,2%上回るのみである。ま
た、絶縁抵抗(R)は比較例及び本発明例共に5000
ΩFであり、全く変化がなかった。
That is, as an electrical characteristic, the electrostatic capacitance 1t (C) is 0.14 μF for both the comparative example and the present invention example, and the dielectric loss (tan
s) is only 0.2% higher in the example of the present invention. In addition, the insulation resistance (R) is 5000 for both the comparative example and the present invention example.
ΩF, and there was no change at all.

一方、機械的強度として耐チッピング性を知るための重
量減は、比較例が2.3%であるのに対し、本発明例は
1.1%であり、約半分に抑えられた。
On the other hand, the weight loss, which is used to determine chipping resistance as mechanical strength, was 2.3% for the comparative example, while it was 1.1% for the inventive example, which was suppressed to about half.

また、抗折強度は、比較例が1560kg/cm2であ
るのに対し、本発明例では2170kg/cm2であり
、1.4倍の強度が認められ、曲げ応力にも優れている
ことが判った。
In addition, the bending strength was 1560 kg/cm2 for the comparative example, while it was 2170 kg/cm2 for the inventive example, which was 1.4 times the strength and was found to be excellent in bending stress. .

以上の様に、本実施例の積層セラミックコンデンサは、
積層誘電体1に希土類酸化物を主成分としたペーストを
塗布して焼成すると、積層誘電体1の表面層の粒子径が
誘電体内部の粒子径よりもノJ\径となり、緻密化され
た。これにより、表面層が硬化されて、電気的特性に影
響を与えず耐チ、2ピング性及び抗折強度を高めること
ができた。従って、この積層セラミックコシデンサは機
械的強度に優れ、配線用基板に自動実装する際、従来の
様な欠けや損傷が表面層に生じることはない。また、積
層セラミックコンデンサを実装した基板が熱ストレスに
より変形してそり返り、積層セラミックコンデンサに曲
げ応力が作用しても、稜線部分に亀裂が生じることなく
、割れ等の発生も防止される。
As described above, the multilayer ceramic capacitor of this example is
When the laminated dielectric 1 is coated with a paste mainly composed of rare earth oxides and fired, the particle size in the surface layer of the laminated dielectric 1 becomes larger than the particle size inside the dielectric, resulting in densification. . As a result, the surface layer was hardened, and the chip resistance, 2-pin resistance, and bending strength could be improved without affecting the electrical properties. Therefore, this multilayer ceramic cocidenser has excellent mechanical strength, and when it is automatically mounted on a wiring board, the surface layer is not chipped or damaged as in the conventional case. Further, even if the substrate on which the multilayer ceramic capacitor is mounted is deformed and warped due to thermal stress and bending stress is applied to the multilayer ceramic capacitor, no cracks will occur in the ridgeline portion, and the occurrence of cracks or the like is prevented.

なお、本発明に係る積層セラミックコンデンサは前記実
施例に限定きれるものではなく、その要旨の範囲内で種
々に変形することができ、特に、セラミックの組成材料
、製作工程等は幅広く適用可能であり、さらに、表面層
の粒子径を小きく押さえるために塗布する酸化物の種類
は希土類のほかに、表面層の小粒径化に効果のあるその
他の物質でも適用可能である。
It should be noted that the multilayer ceramic capacitor according to the present invention is not limited to the above embodiments, and can be modified in various ways within the scope of the gist, and in particular, the ceramic composition material, manufacturing process, etc. can be widely applied. Furthermore, the type of oxide applied to reduce the particle size of the surface layer may be, in addition to rare earths, other substances that are effective in reducing the particle size of the surface layer.

発明の効果 以上詳述した様に、本発明によれば、積層誘電体セラミ
ックの表面層の粒子径が内部の粒子径よりも小径であり
、緻密化きれているため、積層セラミックコンデンサの
表面層が硬化される。これにより、電気的特性に影響を
与えることなく、積層セラミックコンデンサの耐チッピ
ング性や抗折強度等の機械的強度が高められる。従って
、コンデンサ自体に外力が加えられた際、割れや欠は等
の発生が防止きれ、コンデンサとしての特性が低下する
ことなく、劣化も防止されて長寿命を維持する。しかも
、各種積層コンデンサに適用が可能であり、適用範囲は
格段に広がる。
Effects of the Invention As detailed above, according to the present invention, the particle size of the surface layer of the multilayer dielectric ceramic is smaller than the internal particle size and is fully densified. is hardened. As a result, the mechanical strength such as chipping resistance and bending strength of the multilayer ceramic capacitor can be improved without affecting the electrical characteristics. Therefore, when an external force is applied to the capacitor itself, cracks, chips, etc. can be prevented from occurring, the characteristics of the capacitor will not deteriorate, and deterioration will be prevented, thereby maintaining a long life. Moreover, it can be applied to various multilayer capacitors, and the range of application is greatly expanded.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の実施例を示し、第1図は積層セラミック
コンデンサの断面図、第2図ないし第4図は製作工程を
示す断面図である。 1・・・積層誘電体、2,2a・・・誘電体セラミック
、3・・・内部電極、4・・・外部電極。 特許出願人   株式会社村田製作所
The drawings show embodiments of the present invention; FIG. 1 is a sectional view of a multilayer ceramic capacitor, and FIGS. 2 to 4 are sectional views showing manufacturing steps. DESCRIPTION OF SYMBOLS 1... Laminated dielectric material, 2, 2a... Dielectric ceramic, 3... Internal electrode, 4... External electrode. Patent applicant Murata Manufacturing Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 1.複数枚の誘電体セラミックの間に内部電極を埋設し
た積層セラミックコンデンサにおいて、積層された誘電
体セラミックの表面層の粒子径が内部の粒子径よりも小
径であることを特徴とする積層セラミックコンデンサ。
1. A multilayer ceramic capacitor in which internal electrodes are embedded between a plurality of dielectric ceramic sheets, characterized in that the particle size of the surface layer of the laminated dielectric ceramic is smaller than the particle size of the internal particles.
JP21332488A 1988-08-26 1988-08-26 Laminated ceramic capacitor Pending JPH0262022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21332488A JPH0262022A (en) 1988-08-26 1988-08-26 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21332488A JPH0262022A (en) 1988-08-26 1988-08-26 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH0262022A true JPH0262022A (en) 1990-03-01

Family

ID=16637266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21332488A Pending JPH0262022A (en) 1988-08-26 1988-08-26 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH0262022A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081228A (en) * 2005-09-15 2007-03-29 Tdk Corp Surface mounted electronic component array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081228A (en) * 2005-09-15 2007-03-29 Tdk Corp Surface mounted electronic component array

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