JPH10106881A - Multilayered ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered ceramic capacitor capable of maintaining reliability as a capacitor, by preventing deterioration of dielectric characteristics which is to be caused by thinning layers and increasing the number of layers, and restraining generation of cracks in a surface mounting process. SOLUTION: A multilayered ceramic capacitor is provided with the following; a part 3 which is composed of a plurality of dielectric ceramic layers 1 clamped by a pair of internal electrode layers 2 and generates capacitance, a part 8 formed on the outer peripheral surface of the part 3 which is composed of ceramic and does not generate capacitance, and an external electrode 9 connected with the internal electrode layers 2. The thermal expansion coefficient of the part 8 is smaller than that of the dielectric ceramic layer 1 of the part 3, by 4-10-10×10<-7> / deg.C. The volume of the part 8 is 5-50% of the total volume except the external electrode 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor.

[0002]

2. Description of the Related Art Recently, chip-type multilayer ceramic capacitors have been widely used as electronic components. The multilayer ceramic capacitor includes a dielectric ceramic layer having a thickness of 5 to 30 μm made of barium titanate or neodymium titanate, an internal electrode layer having a thickness of 0.5 to 2 μm made of silver palladium or nickel, and the like. Thickness 100 to 5 made of dielectric ceramic of the same quality as the ceramic layer
After a protective layer of 00 μm is bonded and integrally fired, an external electrode connected to an internal electrode layer is formed on both end surfaces of the laminated sintered body by firing.

In recent years, such chip type multilayer capacitors have been required to have a large capacity as well as a small size.
To meet this demand, the dielectric ceramic layers are made thinner to achieve higher lamination. In addition, it is necessary to increase the internal electrode area of each layer by reducing a margin portion that does not contribute to the obtained capacitance in order to obtain a capacitance as large as possible.

As a method for manufacturing a multilayer ceramic capacitor for reducing a margin portion, a method has been proposed in which a side margin portion is formed by printing or coating a ceramic slurry, as disclosed in Japanese Patent Application Laid-Open No. Hei 6-13259. According to this method for manufacturing a multilayer ceramic capacitor, it is possible to prevent a decrease in the facing area due to the displacement of the internal electrodes inside the multilayer capacitor, to obtain a large capacitance, and to obtain a multilayer ceramic capacitor with little variation.

[0005]

However, in the manufacturing method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 6-13259, the shrinkage ratio, the coefficient of thermal expansion and the like during firing of the metal contained in the internal electrode and the dielectric ceramic layer are reduced. Due to the difference, the internal stress generated in the capacitor increases, and the distortion increases. Due to this distortion, even if the dielectric thickness is the same, the dielectric characteristics are degraded due to the increase in the number of stacked layers, and the thermal stress and mechanical stress generated in the surface mounting process, as well as cracks in the capacitor due to thermal shock, etc. There is a problem that causes a decrease in

When a multilayer capacitor is actually manufactured, if the number of layers increases, the thickness of the internal electrodes causes the stacking thickness of the portion where the internal electrodes overlap via the ceramic layer inside the multilayer body and the other margin portion to be increased. And the problem described above was likely to occur.

The present invention provides a multilayer ceramic capacitor capable of preventing deterioration of dielectric properties due to thin layers and high lamination, suppressing cracks in a surface mounting process, and maintaining reliability as a capacitor. The purpose is to:

[0008]

That is, a multilayer ceramic capacitor according to the present invention has a capacitance generating portion composed of a plurality of dielectric ceramic layers sandwiched between a pair of internal electrode layers, and is formed around the outer periphery of the capacitance generating portion. In a multilayer ceramic capacitor including a non-capacitance generating portion made of ceramic and an external electrode connected to the internal electrode layer, a thermal expansion coefficient of the non-capacitance generating portion is smaller than that of the dielectric ceramic layer of the capacitance generating portion. The thermal expansion coefficient is smaller by 4 to 10 × 10 ⁻⁷ / ° C., and the volume of the non-capacity generating portion is 5 to 50% of the total volume (excluding external electrodes).

[0009]

According to the multilayer ceramic capacitor of the present invention, during the cooling process after sintering, tensile stress is accumulated in the capacity generating portion and compressive stress is accumulated in the non-capacity generating portion, and the residual stress is retained. Can show the original characteristics.

That is, for example, as shown in FIG. 3, a pair of external electrodes 9 of the multilayer ceramic capacitor of the present invention are mounted on a substrate 11 made of glass epoxy or the like, which is wired with copper.
When mounting is carried out, since both sides are fixed by the external electrodes 9, the thermal stress and mechanical stress generated in the mounting process and the thermal shock (bending applied to the substrate 11) are applied to the capacitance generating portion 3 between the external electrodes 9. Stress or thermal load during soldering), the tensile stress is absorbed by the compressive stress of the non-capacitance generating section 8, and as a result, the non-capacitance generating section 8 and the capacity generating section 3 Stress is not generated between them and cracks are prevented from occurring. In FIG. 3, the internal electrode layer of the capacitance generating section 3 is omitted.

When the width and thickness of the multilayer ceramic capacitor are the same, it is difficult to distinguish the mounting direction. However, since the corner where the stress is concentrated is the non-capacitance generating portion having a specified thermal expansion coefficient, Even when mounted, most of the tensile stress can be absorbed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a multilayer ceramic capacitor according to the present invention, as shown in FIGS. 1 and 2, a plurality of dielectric ceramic layers 1 and a plurality of internal electrode layers 2 are alternately laminated.
A capacitance generating section 3 composed of a plurality of dielectric ceramic layers 1 sandwiched between a pair of internal electrode layers 2 is formed. Side surface margin portions 4 and 5 made of a pair of ceramics are formed on the side surface of the capacitance generation portion 3, and upper and lower surface margin portions 6 and 7 are formed on upper and lower surfaces of the capacitance generation portion 3. The capacitance generating section 3 includes these side margin sections 4, 5 and upper and lower margin sections 6,
Reference numeral 7 denotes a non-capacity generating unit 8.

External electrodes 9 connected to the internal electrode layer 2 are formed at both ends of the capacitor body 15 including the capacitance generating section 3 and the non-capacitance generating section 8.

The coefficient of thermal expansion of the non-capacitance generating section 8 is 4 times larger than the coefficient of thermal expansion of the dielectric ceramic layer 1 of the capacity generating section 3.
10 to 10 × 10 ⁻⁷ / ° C., and a non-capacity generating portion 8
Is 5 to 50% of the total volume of the capacitor excluding the external electrodes 9, that is, the total volume of the capacitance generating section 3 and the non-capacitance generating section 8.

The thermal expansion coefficient of the non-capacitance generating section 8 is 4 to 10 × the thermal expansion coefficient of the dielectric ceramic layer 1 of the capacitance generating section 3.
10 ^-7 / ° C. only small, of the ratio of the volume of the non-capacitance generation portion 8 and 5 to 50 percent, the difference of thermal expansion coefficient of 4 × 10 ^-7 /
° C or the volume ratio of the non-capacity generating portion 8 is 5% of the whole.
%, A tensile stress for preventing deterioration of the dielectric properties cannot be applied to the capacitance generating portion 3 and a compressive stress sufficient to absorb thermal stress, mechanical stress and thermal shock generated in the surface mounting process. Cannot be applied to the non-capacity generating portion 8, and cracks are likely to be generated from the surface.

On the other hand, if the difference in thermal expansion coefficient exceeds 10 × 10 ⁻⁷ / ° C. or the proportion of the non-capacity generating portion 8 exceeds 50%, the tensile stress of the capacity generating portion 3 becomes too large, and This is because a crack is easily generated from the generation part 3.

The difference in the coefficient of thermal expansion between the non-capacitance generating portion 8 and the dielectric ceramic layer 1 of the capacitance generating portion 3 is used to prevent the deterioration of the dielectric properties and to reduce the compressive stress generated in the surface mounting step and the like. Because the optimal tensile stress is applied to the capacity generating section 3, the capacity generating section 3 is 6 to 10 × 10 ⁻⁷ /
It is desirable that the temperature is higher by ° C.

The ratio of the volume of the non-capacitance generating portion 8 to the entire volume of the capacitor excluding the external electrodes 9 is to prevent the deterioration of the dielectric characteristics and to reduce the compressive stress generated in the surface mounting step and the like. It is desirable to be 12 to 40% from the viewpoint that the optimal tensile stress is applied to the capacity generating portion 3.

The volume of the capacitance generating section 3 includes the lowermost internal electrode layer 2 and the uppermost internal electrode layer 2, and is formed on the inner side of the lowermost internal electrode layer 2 and formed on the inner side. Of the dielectric ceramic layer 1 in contact with the internal electrode layer 2 and the portion formed between the dielectric ceramic layer 1 formed on the inner side of the uppermost internal electrode layer 2 and in contact with the uppermost internal electrode 2 It is the volume and the volume excluding the side margin portions 4 and 5.

From the viewpoint of improving the dielectric properties, the dielectric ceramic layer is mainly made of a dielectric material mainly composed of a titanate such as barium titanate, lanthanum titanate, calcium titanate, neodymium titanate and magnesium titanate. It is desirable to be composed of ceramic. in this case,
Non-capacitance generation part made of ceramics contains 5 to 15 mol of zirconate from dielectric ceramic layer of capacitance generation part
By adjusting so as to include more by%, the difference in the coefficient of thermal expansion between the non-capacitance generating portion and the dielectric ceramic layer of the capacitance generating portion can be set as described above. When the excess content of the zirconate in the non-capacity generating portion is less than 5 mol%, the difference in thermal expansion coefficient tends to be smaller than 4 × 10 ^-7 / ° C. The difference in thermal expansion coefficient tends to be larger than 10 × 10 ⁻⁷ / ° C.

Although zirconate is not used as a raw material of the dielectric ceramic layer, it may be inevitably contained in the raw material, and zirconate is post-added as one composition material of the dielectric ceramic. In some cases, the non-capacity generating portion of zirconate is 5 to 5.
It was described as containing 15 mol% more. As described above, it is more preferable to add zirconate as a raw material of the dielectric ceramic layer because the ceramic strength as a capacitor increases.

The multilayer ceramic capacitor of the present invention can be made of, for example, barium titanate, yttrium oxide (Y
_A dispersant or the like is added to a dielectric material powder mainly composed of ₂ O ₃ ) and magnesium oxide, and these are pulverized and mixed to prepare a slurry. A green sheet having a predetermined thickness is prepared from the obtained slurry by a known molding method, for example, a doctor blade method, and is used as a green sheet for a capacity generating portion.

The raw material powder of the dielectric ceramic layer of the capacity generating section may be made of a zirconate, for example, calcium zirconate (CaZrO ₃ ), barium zirconate (BaZr
O ₃ ) powder is added and treated in the same manner as above to produce a slurry for the side margin. Further, a green sheet having a predetermined thickness is prepared from the slurry by a known molding method, for example, a doctor blade method, and is used as a green sheet for the upper and lower surface margins.

First, an internal electrode paste was printed on one side of the green sheet for the capacity generating section, and a plurality of green sheets on which the internal electrode paste was printed were laminated to form a laminated molded body of the capacity generating section. Green sheets for an upper surface margin portion and a lower surface margin portion are respectively laminated on the upper and lower surfaces of the laminated molded body, and after thermocompression bonding, cut into predetermined dimensions so that the internal electrode layers are exposed on the side surfaces.

Next, the slurry for the side margin portion is applied by printing to a predetermined thickness by a known method, for example, an offset printing method, on a portion where the internal electrode layer is exposed on the side surface of the laminated molded body of the capacity generating portion, and dried. , To make a raw chip.

The raw chips are placed in an oxidizing atmosphere such as the air or a reducing atmosphere such as a nitrogen atmosphere, and
After firing at 00 ° C. for 0.5 to 4 hours, external electrodes connected to the internal electrodes are formed to obtain the multilayer ceramic capacitor of the present invention.

When firing in a reducing atmosphere, the porcelain may be oxidized in an oxidizing atmosphere such as the air.
Further, the multilayer ceramic capacitor of the present invention is particularly effective in a case where 40 or more dielectric ceramic layers are stacked. Furthermore, as a means for reducing the coefficient of thermal expansion of the non-capacitance generating portion, a method of adding zirconate to the dielectric ceramic of the non-capacitance generating portion is employed, but the use of other methods is not excluded.

Further, zirconate is added to the slurry for the side margin portion and the green sheet for the upper and lower margin portions, and the thermal expansion coefficient of the non-capacity generating portion is calculated from the thermal expansion coefficient of the dielectric ceramic layer of the capacitance generating portion. 4-10 × 10 ^-7 /
Although the temperature is decreased by only ° C, the slurry for the side margin may be made to have the same composition as the dielectric ceramic layer of the capacity generating part, and zirconate may be added only to the green sheets for the upper and lower margins. That is, an internal electrode paste is applied to a green sheet so as to expose only a connection portion with an external electrode, and a plurality of the green sheets are laminated to produce a laminated molded body of a capacity generating portion. On the bottom,
It may be manufactured by a conventional manufacturing method in which green sheets for the upper and lower margins to which zirconate is added in a larger amount than the dielectric ceramic layer of the capacitance generating portion are respectively laminated.

[0029]

【Example】

(A) Barium titanate (BaTiO ₃ ) and BaTi
O ₃ yttrium oxide relative to 100 parts by weight of (Y
₂ O ₃ ) and 0.4 parts by weight of magnesium oxide (MgO) were added to a dielectric material powder to which a dispersant and ethyl cellosolve were added, and these were added to a ball mill using ZrO ₂ balls. The mixture was ground and mixed for an hour to obtain a slurry.

(B) Polyvinyl butyral and a plasticizer were added to the obtained slurry and mixed, and then a green sheet for a dielectric ceramic having a capacity generating portion having a thickness of about 8 μm was obtained by a doctor blade method.

(C) An internal electrode paste composed of 50% by weight of nickel, ethylcellulose and butyl carbitol acetate was printed on one side of the green sheet, and the green sheets were stacked in the number of layers shown in Table 1 to form a capacity generating section. A molded body was produced.

(D) Calcium zirconate (CaZrO ₃ ) and / or barium zirconate (BaZrO ₃ ) powders are added to the above-mentioned dielectric material powder in the amounts shown in Table 1, and the same as the above-mentioned slurry for dielectric ceramics. This was processed to obtain a slurry for a side margin portion. Using this slurry, green sheets for the upper and lower margins having a thickness of 10 to 50 μm were prepared in the same manner as in (b).

(E) Two green sheets for the upper and lower margin portions are laminated on the upper and lower surfaces of the laminated molded product obtained in the step (c), respectively, and then thermocompression-bonded to produce a laminated molded product. Thereafter, the internal electrodes were cut to predetermined dimensions such that the internal electrodes were exposed on the side surfaces.

(F) Next, the slurry for the side surface margin portion is applied by printing on the side surface of the laminated molded body of (e) where the internal electrodes are exposed by offset printing, and dried to form a layer for insulating the internal electrodes. To obtain raw chips. The thickness of the green sheet for the upper and lower margin portions and the slurry application thickness for the side margin portions were adjusted so that the volume ratio of the non-capacity generating portion after sintering was as shown in Table 1.

(G) Place the raw chips on a zirconia plate and place them in nitrogen gas containing 3% hydrogen for 1150 to 13
Baking at 00 ° C, oxidizing at 600 ° C in air for 30 minutes, length 2mm x width 1.1mm, thickness 0.62-0.80
mm, effective lamination number 100 layers, effective electrode area 1.6 mm x
0.66-1.09mm, dielectric ceramic layer thickness 5μ
m of a sintered body for a chip capacitor was obtained. The thickness of the left and right side margins and the thickness of the upper and lower margins were as shown in Table 1.

(H) After barrel polishing of the sintered body, a copper paste is applied to both sides of the capacity generating portion where the side margins are not formed, and baked at 900 ° C.
i-plating and Sn-plating to form external electrodes,
The multilayer ceramic capacitor shown in FIGS. 1 and 2 was obtained.

(I) The thickness of the side margin and the thickness of the upper and lower margins, CaZrO ₃ and BaZr
For the sample in which the added amount of O ₃ was changed, the volume occupied by the entire non-capacitance generating portion was calculated, and the value obtained by subtracting the thermal expansion coefficient of the non-capacitance generating portion from the thermal expansion coefficient of the dielectric ceramic layer of the capacitance generating portion. Δα is measured and calculated, and the residual stress (compressive stress at the non-capacity generating portion, tensile stress at the capacity generating portion) is further analyzed by FEM.
It was determined by an analytical method.

The capacitance generating portion includes a lowermost internal electrode layer and an uppermost internal electrode layer, and is a portion on the inner side of these internal electrode layers and excluding a side margin portion. The other part was defined as a non-capacity generating part.

Further, the sample was measured with an LCR meter 4284A.
Using a frequency of 1.0 MHz and an input signal level of 1.0 V
The capacitance at −55 to 125 ° C. was measured at rms, and the change rate TCC of the capacitance at each temperature with respect to the capacitance at + 25 ° C. was calculated.

(J) Then, as shown in FIG. 3, a sample capacitor is bonded on a copper epoxy glass epoxy substrate 11 by solder 13 and the substrate 11 is separated by 90 mm.
Of the substrate 11 was pressed from the back surface of the substrate 11 to determine the amount of flexural deformation of the substrate 11 until the sample capacitor cracked (based on the Japan Electronic Machinery Manufacturers Association standard RC-3402).

(K) The polished cross section of the sintered body of (g) was observed with a stereoscopic microscope (× 40), and the presence or absence of cracks in the capacity generating portion was examined.

The amount of CaZrO ₃ and BaZrO ₃ added,
Ratio of the volume of the non-capacitance generating portion to the whole except the external electrodes (%), the coefficient of thermal expansion of the non-capacitance generating portion, the difference in the coefficient of thermal expansion between the non-capacitance generating portion and the dielectric ceramic layer of the capacitance generating portion, residual Stress (kg / mm ² ), flexural deformation of substrate before cracking (mm), presence or absence of crack in capacity generating part after firing, result of dielectric property TCC (%), thickness and top surface of side margin part And the thickness of the bottom margin,
Tables 1 and 2 show the effective electrode area of one layer.

[0043]

[Table 1]

[0044]

[Table 2]

From Tables 1 and 2, Sample No. 3 to 9, 11,
12, 14, 15, 18, and 19 all have a large compressive stress in the non-capacitance generating portion, and therefore have a deformation amount of 3.2 mm before cracking according to the test method of the above-mentioned standard RC-3402.
It is understood that the above is large enough to withstand the tensile stress at the time of surface mounting. Further, since the tensile stress of the capacity generating portion is small, there is no internal crack.

On the other hand, the sample No. In Nos. 1 and 17, there is no difference in the thermal expansion coefficient between the non-capacity generating portion and the capacity generating portion, so that the compressive stress is not accumulated in the non-capacity generating portion, and thus the deformation amount before cracking is 2.5 mm or less. Cracks may occur due to tensile stress during surface mounting. Sample No. When the number of laminations is increased by 1 and 17, the amount of flexural deformation increases, and it becomes possible to withstand large deformation, but it can be seen that the temperature change rate TCC of the capacitance deteriorates. It can be seen that the TCC of the sample of the present invention is good even when the number of layers increases. In addition, the sample No. 13
In the case of (2), since the volume ratio of the non-capacity generating portion was large, the tensile stress of the capacity generating portion was large, and cracks occurred inside the sintered body.

Conversely, for sample no. In No. 10, since the ratio of the volume of the non-capacitance generating portion is small, the tensile stress of the capacitance generating portion is small and the TCC cannot be improved. Sample No. In No. 2, since the difference in the coefficient of thermal expansion is small, the tensile stress in the capacity generating portion becomes small, and the TCC cannot be improved. Further, the sample No. 16
In the sample No., the tensile stress at the capacity generating portion became large due to a large difference in the coefficient of thermal expansion. As in the case of No. 13, internal cracks occurred.

In Samples Nos. 18 and 19, an internal electrode paste was applied to a green sheet so as to expose only a connection portion with an external electrode, and a plurality of the green sheets were laminated to form a capacitance generating portion and side margins. Parts were formed, and green sheets for the upper and lower margins to which zirconate was added more than the dielectric ceramic layer of the capacity generating part were respectively laminated on the upper and lower surfaces of the laminated molded body. This is a case where it is manufactured by a conventional general manufacturing method. Also in this case, the compressive stress of the non-capacity generating portion is large, the deformation amount before cracking is as large as 4 mm or more, and there is no internal crack. .

[0049]

According to the multilayer ceramic capacitor of the present invention, after sintering, tensile stress accumulates and remains in the capacitance generating portion, and the dielectric characteristics, particularly the temperature change rate TCC of the capacitance, do not change even at the time of high lamination. In addition, compressive stress accumulates and remains in the non-capacity generating portion, and the compressive stress can absorb the tensile stress at the time of surface mounting, thereby suppressing cracking at the time of surface mounting,
The reliability of the capacitor can be maintained.

[Brief description of the drawings]

FIG. 1 is a perspective view illustrating a non-capacitance generating portion and a capacitance generating portion of a multilayer ceramic capacitor according to the present invention.

2A is a longitudinal sectional view of FIG. 1, and FIG.
FIG.

FIG. 3 is a longitudinal sectional view showing surface mounting of the multilayer ceramic capacitor on a substrate.

[Description of Signs] 1 ... Dielectric ceramic layer 2 ... Internal electrode layer 3 ... Capacitance generating part 4, 5 ... Side margin part 6, 7 ... Upper and lower surface margin part 8 ... Non-capacitance generator 9 ・ ・ ・ External electrode 11 ・ ・ ・ Substrate 13 ・ ・ ・ Solder 15 ・ ・ ・ Capacitor body

Claims (1)

[Claims] A capacitor generating portion formed of a plurality of dielectric ceramic layers sandwiched between a pair of internal electrode layers; a non-capacitance generating portion made of ceramic formed around the capacitor generating portion; In the multilayer ceramic capacitor including the external electrodes connected to the layers, the coefficient of thermal expansion of the non-capacitance generating portion is 4 to 10 × 10 ⁻⁷ / ° C. higher than the coefficient of thermal expansion of the dielectric ceramic layer of the capacitance generating portion. Small and the volume of the non-capacitance generating part is the whole volume (excluding external electrodes)
5% to 50% of the multilayer ceramic capacitor.