JPH0261746A - Dma control system - Google Patents

Abstract

PURPOSE:To efficiently perform DMA data transfer regardless of a small capacity by easily performing DMA data transfer between memories existing in different spaces through a data buffer while monitoring the status cycle. CONSTITUTION:A data buffer 18 is provided between a first memory (local memory) 10 and a second memory (main storage) 14, and the data buffer 18 is directly accessed by a control part 20 having a first space (adapter space), and a cycle status 22 of a second DMA control part (common bus DMA control part) 16 is monitored. The first DMA control part (local bus DMA control part) 12 is not used but only the second DMA control part 16 is used to directly transfer data between the first memory 10 and the second memory 14 through the data buffer 18 by the control part 20.

Description

[Detailed description of the invention] [N required] Regarding a DMA control method that transfers data between memories that physically exist in different spaces, the purpose is to efficiently transfer data even if the data length is short. A data buffer located between the memory existing in the first space and the memory existing in the second space is provided, and the data buffer can be directly accessed by the control unit that owns the first space, and data can be transferred between the memory and the second space memory. It is possible to monitor the status cycle of the DMA control unit that transfers data in the first space, without using the DMA control unit that transfers data in the first space, and by using only the DMA control unit for the second space, data is transferred to the first The configuration is configured to directly transfer data between the spatial memory and the second spatial memory.

[Industrial Application Field] The present invention provides D
DMA transfer t, IJ control (especially Memory to
Memory) is also trending towards faster speeds and larger capacities.

For this reason, in order to achieve faster speeds and larger-capacity transfers for DMA control methods, the address width and data width have been expanded, block transfers have been adopted, and in terms of hardware, LSI
In order to reduce costs, the circuit configuration and control method are becoming more complex.

While increasing the speed and capacity of the MA transfer control method is effective for large-capacity (large-length) data transfers, it often has the opposite effect on small-sized data transfers. Efficient transfer control is also desired for capacity data transfer.

[Conventional technology] FIG. 4 is a block diagram showing a conventional DMA control method.

FIG. 4 shows the DM between the main memory (MM) 14 on the host side and the local memory (LM) 10 on the adapter 100 side.
A transfer control is shown, and the adapter 100 includes a local bus DMA control unit (L-B
A common bus DMA control unit (C-BUS-D
MA control unit) 16, a data buffer 18 existing between the local memory 10 and the main memory 14, and a main control unit (MPtJ) 20 that controls the adapter space.

Data transfer control based on such a conventional DMA control method will be described first with respect to DMA read control for transferring data from the main memory 14 to the local memory 10.

(1”) DMA read (MMl 4 to LMl
0) [Step 1] The main control unit 20 reserves a data buffer in the local memory 10. However, if the DMA transfer mode has restrictions such as 16-byte boundary (block transfer), 16-byte boundary (block transfer), etc.
Secure an area that is a multiple of .

[Step 2] The local bus DMA control unit 12 is initialized.

・Set the start address of the data buffer secured in the local memory 10 in all registers indicating the address space; ・Set the transfer length (this register uses the common bus DMA
May exist on the control unit 16 side>: ・Write, read,
Setting of transfer mode such as data width and cycle type; [Step 3] Set the common bus DMA control unit 16.

・Main memory 1 for all registers indicating address space
Setting the start address of the data buffer secured in step 4; - Setting the transfer mode such as read, write, data width, cycle type: [Step 4] Start DMA transfer control.

・Transfer a specified length of data according to the mode and direction determined by the hardware: ・The activation bit may be present in both or either of the common bus DMA control unit 16 and the local bus DMA control unit 12: [ Issue a step 5 completion notification (interruption).

・Know the completion of transfer by interrupt occurrence: [Step 6] Check completion status.

- Check the validity of the DMA abnormal status register, address register, and length register (both H and L): [Step 7] Analyze the buffer contents.

- If the DMA transfer mode has restrictions such as a 16-byte boundary, there is a possibility that unnecessary data may be added, and in this case, only necessary data is used.

Next, a DMA write for transferring data from the local memory 10 to the main memory 14 in the conventional method will be explained.

(2) DMA light (LMlo to MM14)
[Step 1] The main control unit 20 formats the transfer data onto the local memory 1O. However, if the DMA transfer mode is 16
If there are restrictions such as byte boundaries, it may be necessary to correct or pad the start address.

[Step 2] The local bus DMA control unit 12 is initialized.

・Same as step 2 of DMA read; [Step 3] The common bus DMA control section 16 is set.

・Same as step 3 of DMA read; [Step 4] Activate DMA data transfer control.

・Same as step 4 of DMA read; [Step 5] Notify completion by interrupt.

[Step 6] Check completion status.

・Same as step 6 of DMA read; FIG. 5 shows the contents of the address register, length register, mode register, start register, and status register provided in the local bus DMA control unit 12 and common bus DMA control unit 16 in FIG. 4. shows.

[Problems to be Solved by the Invention] However, although such conventional DMA control methods are effective for data transfers of large length and maximum capacity, they are not effective for data transfers of small capacity.
There is a problem in that data transfer takes time due to overhead associated with the complexity and multi-step control program.

That is, in the case of small-capacity data transfer, there is a problem in that the running time of the control program for starting the DMA transfer control is longer than the DMA transfer time.

The overhead caused by such small-capacity data transfer becomes a problem in the following cases.

First, command-level information other than general data, that is, command and status information that is passed between the system memory and the adapter internal port and local memory, is generally about a few bytes, and has a fast response time. required.

Second, even in general data, not all data lengths are long. That is, the data length is not fixed on the line, and short data is often transferred.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a DMA control method that allows efficient DMA data transfer even with a small capacity.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, the present invention first describes a plurality of first memories (local memory>1
A first DMA control unit (which performs DMA data transfer between
local bus DMA control unit) 12 and a second memory (main memory) 1 that exists in a physically different second space (host side)
4 and the first DMA control unit (local bus DMA control unit) 12;
Aυ [D with surface section (common bus DMA control section) 16
Targets MA control method.

Regarding this MA control method, in the present invention,
A data buffer 18 is provided between the first memory (local memory>10) and the second memory (main memory), and the data buffer 18 can be directly accessed by the control unit 20 that owns the first space (adapter space). with second
The cycle status 22 of the DMA control unit (common bus control unit) 16 can be monitored without using the first DMA control unit (local bus DMA control unit) 12. The control unit 20 is configured to directly transfer data between the first memory (local memory) 10 and the second memory (main memory) 14 via the data buffer 18 by using only the second memory (main memory).

[Operation] In the DMA control method of the present invention having such a configuration, DMA control between memories existing in physically different spaces is possible.
Regarding data transfer, for small data transfer,
A DM that transfers DMA data in different spaces without using a DMA control unit that transfers DMA data within the same space.
By using only the A control unit and monitoring the status cycle, it is possible to easily transfer DMA data between memories located in different spaces via the data buffer, and even if the transfer data is small, it can be transferred. Response time and buffer usage efficiency can be improved by performing DMA control commensurate with the data length.

Specifically, the DMA control method of the present invention provides the following advantages.

(1) No need to set the local bus DMA control unit; - Address setting, length setting, transfer mode setting, startup setting (2) No need to check the completion status of the local bus DMA control unit: - Abnormal status check, address register check, Range register check (3) Buffer processing becomes simple and can be used efficiently; - Boundary restrictions such as starting address boundary, insertion or deletion of dummy data, etc. are not required. - Direct control unit processes data, so buffer Improved usage efficiency (4) No need for interrupts or bus arbitration time; ・Since the control unit directly monitors the common bus DMA cycle status every time, no interrupts are required.As a result, efficiency is improved even with short data lengths. DMA data transfer can be performed with good efficiency and high buffer utilization efficiency.

[Embodiment] FIG. 2 is a configuration diagram of an embodiment of the present invention, showing a local bus DMA control section, a common bus DMA control section, and a data buffer provided in an adapter.

In FIG. 2, 12 is a local bus DMA control section, which includes a data bus 24, an address bus 26, and a control line 28.
It is connected to a main control unit (MPU) 20 (not shown) and a local memory (LM) 10 (not shown) that control the adapter space through the adapter. Note that the address bus 26 is provided with an address bus driver 30, and the control line 28 is provided with a driver/receiver 32.

The local bus DMA control unit 12 includes an address register 34-1, a length register 36-1, a mode register 38-1, and a start register in order to transfer DMA data between multiple local memories existing in the same space within the adapter. 40-1 and a status register 42-1 are provided.

16 is a common bus DMA control unit, and the common bus DMA control unit 16 is connected to a main control unit (MPU) 20 (not shown) and a local memory (LM) via a data bus 24 in the adapter.
10, and on the other hand, it controls an address line 46 via an address driver 44 and a driver/receiver 4B to transfer data between it and a main memory (MM) 14 (not shown) existing in a different space. The line 50 is further connected to a common bus (not shown) by a data bus 54, and an adapter-specific data bus 214 is connected via a data transmitting/receiving section 52.

This common bus DMA control unit 16 also has a local bus DMA.
Similar to the control unit 12, an address register 34-2, a length register 36-2, a mode register 38-2, a start register 40-2, and a status register 42-2 are provided.

Furthermore, within the adapter, a read data buffer 18-1 is provided as a buffer existing between the local memory (LM) 10 existing within the adapter and a main memory (MM) 14 (not shown) existing in a different external space. A data buffer 18-2 is provided for RIE 1 to RIE 1.

The data buffer '18 1 for reading is a main memory (MM
) 14 to the local memory (LM) 10 in the adapter. In addition, the data buffer 118-2 for the drive 1 is a DM that transfers data from the local memory (LM) 10 in the adapter to the main memory (MM) 14 (not shown) existing in an external space.
Used for A-light.

Furthermore, FF56 and FF58 are provided corresponding to the read data buffers 18-1 and 18-2.

[[56 is the common bus DMA control unit 1 at the time of DMA read.
6, and the outputs from Sera 1 through the setting of this FF56 are sent to the common bus DMA! ill u11 part 1
6 is read as a read request (RQR), and the next DMA cycle is prohibited while the FF 56 is set, as will be explained later.

Also, once set FF56 is data buffer 118-
When data reading is determined by the main control unit (MPU) 20 in the adapter via the control line 60, the main control unit (MPU) 20 in the adapter
It is reset via the OR gate 62 by a read signal from the PU) 20.

On the other hand, the FF 58 provided on the data buffer 18-2 side for writing is connected to the limiting V line 64 and the OR gate 6 from the main control unit (MPU) 20 in the adapter during DM and A writing.
The set output of the FF 58 sends a write request to the common bus DMA control unit 16 (
RQW), and while the FF 58 is in the set state, it is in the DMA cycle request state for c-sus. Once set, the FF 58 is reset by a reset signal from the common bus DMA control unit 16 when data transfer for DMA write via the data buffer 18-2 is completed.

In the case of short data length DMA transfer which is controlled by the present invention, the local bus DMA control unit 12 side is not used, as shown by the broken line in FIG. 2, and is shown by the solid path line or control line. Only the common bus DMA control section 16 side is used to perform data transfer for DMA read or DMA write.

Next, the control processing of DMA data transfer in the embodiment shown in FIG. 2 will be explained.

First, a DMA read control process for transferring data from the master memory (MM) 14 existing in the external space to the local memory (LM) within the adapter will be described.

(1) DMA read (MM14 °C OLMI○) [Step 1] The main control unit (MPU) 20 in the adapter secures a data buffer in the local memory (LM) 10. however,
It is not always necessary to secure a data buffer area within the local memory 1 (LM) 10.

(Step 2) The common bus DMA control section 16 is set.

- Set the start address of the data buffer in the main memory (MM) 14 to the address register 34-2: - Set the transfer mode to the mode register 38-2: - Start register 40-
Set DMA star l~ to 2; [Step 31 Start DMA transfer control.

- The common bus DMA control unit 16 reads 1 byte or 1 word of data from the main memory (MM") 14 via the common bus, sets it in the data buffer 18-1 for reading, and simultaneously sets the FF 56; - This The 5usy bit of the status register 42-2 is set to “1” only during the cycle.
”; While the FF 56 is set, the next DMA cycle is prohibited: [Step 4] Read data from the read data buffer 18-1.

・The main control unit (MPU) 20 in the adapter is a common bus DM
BUSY of status register 42-2 of A control unit 16
The completion of the DMA cycle is known when the bit becomes rOJ; - Next, the main control unit (MPU) 20 refers to the status registers 42 to 2 and confirms that no DMA abnormality has occurred: - Next The main control unit (MPU) 20 is a data buffer 18
-1 reads data and performs analysis processing.

・The common bus DMA control unit 16 is a main control unit (MPU>20
By reading the data base from the data buffer 18-1, FF5 is sent via the control line 60 and the OR gate 62.
6 and returns to the process of step 3 again; [Step 5] The main control unit (MPU) confirms that the DMA read is completed.

- When the main control unit (MPU) 20 determines that the data is the final data, it sends the DM of the start register 40-2 of the common bus DMA control unit 16.
A: Turn off the 5TART bit and read the data; ・The DMA 5TART bit of the startup register 40-2 turns off, and the subsequent DMA cycle is stopped; teeth,
If the length register 36-2 exists in the common bus DMA control unit 16 as shown by the broken line in FIG. 2, the length register 36-2 may be used. That is, by using the length register 36-2, when the length of the transfer data matches the set value of the length register 36-2, the DMA 5TART bit of the activation register 40-2 is automatically turned off, and at the same time, the status register 42 is turned off. -2 DMA END bit will be turned on.

Furthermore, the BUSY bit of the status register 42-2 is checked if the common bus DMA cycle is
It is not necessary if the processing speed is sufficiently faster than U>20.

FIG. 3 shows the address register 34-- provided in the common bus DMA control unit 16 used in steps 1 to 5 described above.
2. Length register 36-2, mode register 38-
2. Starting registers 40 to 2, and status register 4
2-2 is a register explanatory diagram showing the contents of step 2-2. By referring to the register explanatory diagram of FIG. 3, the processing of steps 1 to 5 described above will become more clear.

Next, in Figure 2, the local memory (L
A DMA write control process for transferring data from M) 10 to MM 14 provided in an external space will be explained.

(2) DMA write (LMlo tQ MM14)
Step 1] The main control unit (MPU) 20 in the adapter prepares transfer data on the local memory (LM) 10.

Note that this data L may be prepared at the time when transfer data of 1 byte or 1 word is generated, and does not need to be specially prepared on the local memory (LM>10).

[Step 2] Settings for the common bus DMA control section 16 are performed.

- Set the start address of the data buffer in the main memory (MM) 14 in the address register 34-2; - Set the transfer mode in the mode register 38-2; - Start register 40-
Set DMA 5TART to 2; [Step 3] The main control unit (MPtJ) 20 performs write access to the data buffer 18-2 via the control line 64 and the OR gate 66, so that the data is transferred from the local memory (LM) 10. At the same time, FF58 is also set, and a write request (RQW) is issued by the set output of FF58.
), the common bus DMA control unit 16 starts operating. Note that while the FF 58 is in the set state, the BUSY bit of the status register 42-2 becomes 11.
The next DMA cycle is inhibited by the MPU.

When the DMA cycle of the common bus DMA control unit 16 completes data transfer of 1 byte or 1 word, the FF 58 is reset. During this DMA cycle, the BUSY bit of the status register 42-2 is "1".

[Step 4] The main control unit (MPU) 20 in the adapter checks the status. That is, the main control unit (MPU) 20 uses the common bus DM.
Read the status register 42-2 in the A control unit 16 and confirm that the BUSY bit is -0 and that no DMA abnormality has occurred.

[Step 5] Confirm the completion of the DMA write request.

・If the next data exists, return to step 3. ・If the next data does not exist, start register 4.
Turn off the DMA 5TART bits of 0-2. Of course, until the transfer mode is changed, the activation register 40-2
may be left as is; D shown in steps 1 to 5
Even in MA write, if the length register 36-2 exists in the common bus DMA control unit 16 as shown by the broken line in FIG. The DMA 5TART bit is automatically turned off, and the status register 4
The DMA END bits 0-2 can also be turned on automatically.

Further, checking the BUSY bit of the status register 42-2 is not necessary if the DMA cycle of the common bus DMA control section 16 is sufficiently faster than the processing speed of the main control section (MPU>20).

The DMA read or DMA write in the DMA control method of the present invention has the following advantages over the conventional method.

First, address setting, length setting, transfer mode setting, and startup setting for the local bus DMA control unit 12 are not necessary.

Second, there is no need to check the completion status in the local bus DMA control unit 12, ie, abnormality status check, address register check, and length register check.

Third, buffer processing becomes simpler and buffers can be used more efficiently. That is, there is no need for boundary restrictions such as making the start address into a boundary or inserting or deleting dummy data, and furthermore, since the main control unit (MPU) 20 directly processes data, buffer usage efficiency is improved.

Fourthly, since the main control unit (MPtJ) 20 in the direct adapter monitors the common bus DMA cycle status every time, there is no interruption to the main control unit (MPU>20) that makes requests and permission responses to the local bus arbiter. No longer required, bus arbitration time (request/grant time)
can be made unnecessary.

[Effects of the Invention] As explained above, according to the present invention, it is possible to perform DMA control that matches the transfer data size even for short data periods, thereby obtaining an optimal response time and improving buffer usage efficiency. can do.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention; Fig. 2 is a block diagram of an embodiment of the present invention; Fig. 3 is a diagram explaining the registers of the common bus DMA control unit according to the present invention; Fig. 4 is a block diagram of the conventional system; FIG. 5 is an explanatory diagram of a conventional DMA control unit register. In the figure, 10: first memory (local memory LM) 12: first DMA control section (local bus DMA control section) 14: second memory (main memory MM) 16: second DMA control section (common bus DMA control section) Control unit) 18: Data buffer? 18-1: Data buffer for reading 18-2 Data buffer for writing 20: Control unit (main control unit MPU) 22: Status cycle 24.54: Data bus 26.46: Address bus 28.50: Control line 30 .44 Near address driver 32.48: Driver/receiver 34-1.34-2 Near address register 36-1.36
-2: Length register 38-1.38-2: Mode register 56゜62゜1.40-2: Start register 1.42-2: Status register 58: FF 66: OR gate

Claims (2)

[Claims] (1) A first DMA control unit (12) that performs DMA data transfer between a plurality of first memories (10) existing in the first space.
) and a second memory (
14) and the first DMA control unit (12).
In a DMA control method including a second DMA control unit (16) that performs A data transfer, the first memory (10
) and a second memory (14), and a control unit (2) that owns the first space.
0), the data buffer (18) can be directly accessed and the cycle status (22) of the second DMA control unit (16) can be monitored, and the first DMA control unit (12) is used. without the second D
Direct data transfer is performed by the control unit (20) between the first memory (10) and the second memory (14) via the data buffer (18) by using only the MA control unit (16). Features DMA control method. (2) The first memory (10) is a local memory provided in the adapter space, and the first DMA control unit (10) is a local memory provided in the adapter space.
12) is a local bus DMA control unit in the adapter; the second memory (14) is a main memory connected to the adapter via a common bus;
2. The DMA control system according to claim 1, wherein the DMA control section (16) is a common bus DMA control section provided within the adapter.