JPH0260056B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming deep grooves in a semiconductor substrate, particularly a silicon substrate, by RIE (Reactive Ion Etching).

[Prior Art] Conventionally, the RIE technique has been used to form deep trenches in a structure consisting of a heavily doped semiconductor layer sandwiched in a sandwich pattern by upper and lower lightly doped semiconductor layers.

[Problems to be Solved by the Invention] When a deep trench is formed by etching a substrate with varying doping levels as described above necessary for forming a transistor device using the RIE technique, the doping levels vary. An undercut portion occurs in a portion of the substrate exhibiting This phenomenon occurs when the width of the groove is 1.25μ on the board configured as above.
This is noticeable when forming the following deep grooves.

IBM for lateral etching of heavily doped semiconductor regions (referred to as bloomig).
It is shown in TDB, Vol. 21, No. 7, December 1978, p. 2814.

In conventional methods, etching was performed in a mixture of CCl ₂ F ₂ +O ₂ or SF ₆ +CCl ₂ to provide the desired groove in the sander trench structure in a single step. When using these gases, if the groove width becomes smaller than 1.25μ,
When the above-described lateral etching is performed, a recess is created into which the insulating material cannot be filled when filling the recess or groove portion with the insulating material, which is an obstacle to the formation of high-density devices.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an RIE method for forming trenches with uniform sidewalls in a semiconductor substrate.

[Means for Solving the Problems] In the present invention, CCl ₂ F ₂ + argon and CCl ₂ F ₂ + oxygen are used for RIE. First, the former gas is used to etch at least a portion of the thickness of the exposed portion of the upper layer of the lightly doped semiconductor substrate. The latter gas, after exhausting the former gas, etches the remaining thickness of the upper layer, etches the heavily doped region, and etches the lightly doped region below it. Used for etching at least a portion. Although the present invention is not limited to any particular trench width, it is particularly suited for etching trenches with widths of approximately 1.25 microns or less.

[Example] First, FIG. 3 shows a partial cross-sectional view of a reactive ion etching (RIE) apparatus used in carrying out the method of the present invention. 1 is a vacuum housing, 2 is a base plate, and 3 is a glass or metal bell jar (sealed to the base plate 2). 4 is a cathode plate electrically and mechanically connected to the cathode 5;
It is located inside Bell Jar 3.

The cathode 5 is preferably a high frequency electrode supported by an electrode support element 6 provided through the base plate 2 via an insulator 7. The electrode support element 6 and the insulator 7 are connected to the base plate 2
Hold the cathode 5 almost parallel to the A shield 8 extending from the base plate 2 is provided at a distance from the cathode plate 4, cathode 5 and electrode support element 6, following the shape of these elements. The surface of the cathode plate 4 has a plurality of recesses 9 in which the substrate to be etched is accommodated.

10 is a perforated anode plate (capture plate).

The anode plate 10 confines the plasma generated during operation in the space between the anode plate 10 and the cathode plate 4. However, a diffused glow fills the remainder of the bell jar 3.

The cathode plate 5, usually made of copper, is provided with fluid conduits 12 for cooling the cathode plate 4 if necessary. A high frequency power source 13 that supplies power to the RIE apparatus is connected between the electrode support element 6 and the ground potential.

The anode plate 10 is connected to the same potential as the shield 8 (ground potential). Anode plate 10 is approximately 2.54 cm from cathode plate 4
(1 inch) apart. As the material of the cathode plate 4 is somewhat sputtered, the anode plate 10 is used to intercept the sputtered material and prevent it from diffusing back towards the surface of the substrate being etched. . When aluminum, stainless steel or copper is used as the material for the cathode plate 4, sputtering as described above may occur.

In FIG. 3, 14 is an exhaust pipe connected to a vacuum pump (not shown) for evacuating the inside of the bell jar 3. Exhaust is performed before RIE processing the substrate. Conduits 16 and 1 branched from conduit 15
7 has variable leak valves 18, 19 and a flow meter 20,
21 are provided. The valves and meters can be replaced by devices that function as flow controllers. Mass flow meters and control devices can be used, for example, with standard ^cubic
Measures the molecular flow rate in units of centimeters per minute (sccm). 22 and 23 are storage containers for a first gas and a second gas, respectively, used for RIE.

A substrate is placed in the recess 9 of the cathode plate 4. The substrate is arranged so that its surface is flush with the surface of the cathode plate 4.

Please refer to FIG. 2 which shows the prior art. 30 is a semiconductor substrate made of silicon, for example. Reference numeral 31 denotes a heavily doped n ⁺ conductivity type layer, with lightly doped n type layers 32 and 33 above and below it. 34 is a mask layer, which is the mask layer of the substrate 30.
It may be a single layer of silicon dioxide deposited on the surface of the substrate, or it may be a composite layer of silicon dioxide on top of a silicon nitride layer. The material of the mask layer may be any material that can serve as a mask for forming grooves in the substrate to a desired depth.

In FIG. 2, 35 is a groove. This is layer 3
1 and 32 and extends to layer 33. In the RIE apparatus of FIG. 3, when using an etching gas such as CCl ₂ F ₂ +Oxygen or SF ₆ +CCl ₂ , lateral etching occurs in region 36 in heavily doped n ⁺ layer 31. That is, the trench 35 exhibits non-uniform sidewalls, and when the trench is filled with insulating material, the recess of the region 36 significantly reduces the density of devices formed on the wafer. When using the above-mentioned prior art gas, the sidewalls are relatively uniform until the width W of the opening in the mask layer 34 is approximately 1.25 microns. However, beyond this point significant lateral etching occurs in the n ⁺ layer 31, resulting in the undesirable density and recess problems described above.

Please refer to FIG. Much the same structure as in FIG. 2 is shown, but the sidewalls of trench 35 are uniform and there is no lateral etching of n ⁺ layer 31.

The substrate 30 of FIG. 1 is first prepared by implanting or diffusing an n-type silicon wafer with an n-conductivity type dopant, such as phosphorous or arsenic, to form layer 31. The doping level of layer 31 (1×10 ¹⁹ cm ⁻³ ) is heavily doped to exhibit n ⁺ conductivity type. Subsequently, a lightly doped layer 32 of n-conductivity type is formed on layer 31 using known techniques.
(1×10 ¹⁵ cm ^-3 ) is grown epitaxially.
Next, layer 3 is removed by CVD or other known reformation methods.
A mask layer 34 of silicon dioxide is formed on the surface of 2. A portion of the mask layer 34 is removed by photolithography, and a surface portion of the layer 32 in which the groove 35 is to be formed is exposed by RIE.

Next, the substrate 30 is placed in the recess 9 of the cathode plate 4 of the RIE apparatus shown in FIG. Seal the RIE device and connect the bell jar 3 via the exhaust pipe 14.
The inside is evacuated using a pump (not shown). respectively CCl ₂ F ₂
Vacuum housing 1 while controlling gas storage vessels 22 and 23 filled with +argon and CCl ₂ F ₂ +oxygen with valves 18, 19 and flow meters 20, 21.
Connect inside.

The groove depth etched by RIE is 5μ, layer 32 is 3μ thick, and layer 31 is 1μ thick.
, W is approximately 1.25μ, and the mask layer 34
Assuming that the thickness of the film is 5μ, the following process is carried out.

In a first step, CCl ₂ F ₂ + argon is introduced into the vacuum housing 1. RIE will be conducted under the following conditions.

(a) Gas flow rate 20sccm (b) Gas pressure 20μ (c) RIE power 100W (d) Gas ratio (volume ratio) 1 CCl ₂ F ₂ :Argon = 50:50 Under these conditions, the layer 32 is approximately 0.5μ Etch to a depth of .

Gas flow rates in the range of 20-25 sccm may be used in the above steps. Gas pressure is 18−23μ,
RIE power may be 100W±10%. Similar results are obtained within these conditions.

In the second step, the RIE is stopped and the CCl ₂ F ₂ + argon is evacuated via the exhaust pipe 14.

In the third step, CCl ₂ F ₂ + oxygen is introduced and RIE is performed under the following conditions.

(a) Gas flow rate 20sccm (b) Gas pressure 20μ (c) RIE power 100W (d) Gas ratio (volume ratio) 1 CCl ₂ F ₂ + O ₂ = 50:50 Under the above conditions, the remaining thickness of layer 32 and n ⁺
Layer 31 was etched, and a portion of n-layer 33 was etched. The side walls of the groove 35 are uniform. Similar results were obtained using a gas flow rate of 20-25 sccm, a gas pressure of 18-23 microns, and an RIE power of 100 W±10% in the last step.

Etching the epitaxial layer 32 with CCl ₂ F ₂
Even if complete etching is performed from the surface to the bottom the first time in an argon atmosphere, the subsequent
Etching in an atmosphere of CCl ₂ F ₂ and oxygen may avoid lateral etching. However, do not do this unless there is a special technical reason to etch all the way to the bottom during the first etching. layer 3
Preferably, at least a portion of 2 is etched. For example, for layer 31 of 1 .mu.m, the initial etched thickness of layer 32 is 0.4 .mu.m-0.6 .mu.m.
It goes without saying that the thicker the epitaxial layer 31, the larger the portion of layer 32 that will be etched, but since layer 31 is typically slightly less than half the thickness of layer 32, layer 32 is the first layer to be etched. It will not be penetrated by etching.

[Effects of the Invention] By using the above steps, grooves having uniform sidewalls can be formed in a semiconductor wafer. In typical applications, layer 31 is the subcollector layer and layer 32 is the emitter of the bipolar device.
Epitaxial layers forming the base and collector. The invention can be used not only in the specific case described above, but also in any stacked structure in which the doping levels of layers or regions vary.

Although Figure 1 shows an example of n-conductivity type,
It can also be applied to the case of p conductivity type. Furthermore, layer 33 in FIG. 3 may be p-type and the other regions may be n-type. Conversely, the layer 33 may be n-type and the other layers may be p-type.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a substrate provided with grooves having uniform sidewalls formed according to the present invention, and FIG. 2 is a cross-sectional view of a substrate provided with grooves having uneven sidewalls formed according to the prior art. , FIG. 3 is a diagram showing an outline of the RIE apparatus. 30...Substrate, 31...n ⁺ layer, 32...n layer,
33...N layer, 34...Mask layer, 35...Groove portion.

Claims (1)

[Claims] 1. A method for forming a deep trench in a silicon structure comprising a heavily doped layer sandwiched between first and second lightly doped layers, comprising: CCl ₂ F ₂ reactive ion etching of the exposed surface of the first layer at least partially through its thickness in an atmosphere of CCl ₂ F ₂ and oxygen; forming a deep trench in the silicon structure, including reactive ion etching the remaining thickness of the heavily doped layer and at least a portion of the second lightly doped layer; how to.