JPH0259960A - Digital signal processor - Google Patents

Abstract

PURPOSE:To execute digital signal processing at high speed with high efficiency by composing the second storing means of a ROM and a RAM and designating the address of one memory by the other memory. CONSTITUTION:A memory part 70 is equipped with pointers 71-73, which are, for example, composed of up/down counters, a selector 74, a RAM 75 as the first storing means, and a RAM 76 and a ROM 77 as the second storing means. Consequently, if the address is previously written to one memory out of the ROM 77 and the RAM 76, the memory having the previously written address outputs address data according to a microinstruction to be outputted from a control part 60 and directly designates the address for the other memory without passing through a data bus 100, and data in the other memory can be outputted. Thus, the number of instructions for random address designation can be reduced, and parallel instructions can be simultaneously executed using the data bus.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a digital signal processor, hereinafter referred to as DS.
In particular, it relates to a DSP that efficiently performs random access to memory.

(Prior Art) A DSP is a microprocessor dedicated to digital signal processing that was developed to quickly execute multiply-accumulate operations, which are common in digital signal processing.

Conventionally, this type of DSP was presented at the 1986 IEICE Comprehensive National Conference, Tsukagoshi, Yonekura, No1, Ando, Kanmoto,
Written by Mizutani [227032kbit/sADPCM C0
DECLSI Realization JP.

There was one described in 10-3. The configuration will be explained below using figures.

FIG. 2 is a schematic block diagram showing an example of the configuration of a conventional DSP.

This DSP includes a control section 10, a storage section 20, a calculation section 30,
It is comprised of an input/output (hereinafter referred to as Ilo) section 40, a data bus 50, and the like. The control unit 10 includes a program counter 11 and a read-only memory for storing programs (
(hereinafter referred to as ROM) 12, pipeline register 13
, and a decoder 14. The storage unit 20 includes a memory (hereinafter referred to as RAM) 21 that can be read and written at any time;
RA Jl, 'l pointer 22, ROM23, and R
It has 24 for OIVI river points. The calculation unit 30 is
Multiplier 31, arithmetic logic unit (hereinafter referred to as A L LJ) 32, accumulator (hereinafter referred to as ACC)
33, and selectors 34, 35, 36, etc. Further, the I10 section 40 includes an I10 register 41, an I10 buffer (not shown), and the like.

In the following configuration, for example, A.=B.×LogC...(1) However, B., C.; The calculation operation of variables (j=1 to 10) will be explained.

In addition, the variable B (i=1 to 10) is stored in the RAM 21 in order, the variable C1 (i=1 to 10) is output from the I10 register 41, and the logarithm (Log> conversion table is stored in the ROM 2B). , the operation result A. shall be transferred to the I10 register 41.

The calculation of equation (1) is executed in order according to the following Stellar functions 1> to (9>) by various microinstructions output from the decoder 14.

(1) Set the variable 01 in the I10 register 41 to the pointer 24 via the data bus 50.

(2) Set the first address value for the variable B· stored in the RAM 21 to the pointer 21 from the pipeline register 13 via the data bus 50.

(3) In accordance with the address data output from pointers 22 and 24, calculate the logarithmic value of variable B1 from RAM 21 and ROM 23, respectively. Output gCl, selector 34.35
The multiplier 31 executes B1×LogC1 and increments the pointer 22.

(4) Store the multiplication result in the ACC 32 via the ALU 32.

(5) Transfer the multiplication result stored in the ACC 33 to the 1/'0 register 41 via the data bus 50.

(6) Set variable 02 in I10 register 41 to pointer 24 via data bus 50.

(7) Variable B from RAM21 and ROM23 respectively
Logarithmically equal to 2. gC2 is output, and the multiplier 31 executes B2×LogC2 through the selectors 34 and 35, and the pointer 22 is incremented.

(8) Store the multiplication result in the ACC 33 via the ALU 32.

(9) Transfer the multiplication result stored in ACC3B to the D/○ register 41 via the data bus 50.

After that, if you repeat steps 6) to (9) above eight times,
A calculation result A1.0 is obtained.

(Problems to be Solved by the Invention) However, the DSP with the above configuration has the following problems.

By the address data output from the pointer 24, R
If an attempt is made to randomly read the multiplicand data stored in the OM 23 to the multiplier 31, several instructions are required. For example, when calculating equation (1), 41 steps are required. This allows the data in the I10 register 41 to be transferred to the pointer 24 via the data bus 50 for Loa conversion.
This is because operations cannot be executed during this time because the data is being transferred to. Therefore, in conventional DSPs, it has been difficult to improve calculation efficiency due to processing bottlenecks caused by data transfer.

The present invention provides a DSP that solves the problem of the prior art, which is low computational efficiency due to processing bottlenecks caused by data transfer.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a program memory for storing program data, successive reading means such as a program counter for sequentially reading out the program data,
and a control unit having means such as a decoder that outputs a plurality of microinstructions based on the program data read from the program memory, and a first . a storage section having a second storage means; a multiplier that multiplies data output from the first and second storage means; an ALU connected to the output side of the multiplier; In the DSP, the first storage means includes a calculation unit having an ACC that temporarily holds the output and inputs the output to the ALU, and a data bus that transfers data between the control unit, the storage unit, and the calculation unit. RAM'''C
The second storage means has a ROM and a RAM, and the addressing of one memory is performed by the other memory.

(Function) According to the present invention, since the DSP is +1N as described above, among the ROM and RAM in the second storage means,
If an address is written in the other memory in advance, this other memory will output address data in accordance with the microinstructions output from the control unit and can directly specify the address for the other memory without going through the C data bus. and output the data in one memory. This makes it possible to reduce the number of instructions for random addressing and to simultaneously execute parallel instructions using a data bus. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a DSP showing a first embodiment of the present invention.

This DSP is composed of an MO3 integrated circuit or CMO3 (complementary MO8>integrated circuit), and includes a control section 60 that controls the entire DSP, a storage section 70 for storing data, an arithmetic section 80 that performs calculations, and a data input/output 110 section 90, and a data bus 100 for data transfer between them.

The control unit 60 has a program counter 61 that outputs address data, and a program ROM 62, a pipeline register 63, and a decoder 64 are connected in this order to output example 1 of the program counter 61. The program ROM 62 is a memory that stores program data and outputs predetermined control data based on the address data of the program counter 61. The pipeline register 63 temporarily stores the control data output from the program VI 62, outputs address data 563a for randomly accessing data in the storage section 70 to the data bus 100, and also outputs the control data 563a to the data bus 100. Ta563
It has a function of outputting the data b to the encoder 64. The decoder 64 decodes the control data 563b and stores it in the storage unit 70.
, arithmetic unit 80, and 110 unit 90.

The storage unit 70 includes pointers 71, 72, and 73 composed of, for example, up/down counters, a selector 74, a RAM 75 as a first storage means, and a RAM 76 and a ROM 77 as second storage means. data bus 10
0 is connected to a RAM 75 via a pointer 71, and the RAM 75 is bidirectionally connected to a data bus 100.

Data bus 100 is connected to RAM 76 via pointer 72 , and RAM 76 is bidirectionally connected to data bus 100 as well as to pointer 73 via selector 74 .

Is pointer 73 a ROM? 7 and its ROM77
is connected to data bus 100.

The pointer 71 indicates the pipeline register 63 and the arithmetic unit 8.
Address data 5 output from I10 section 90
71a is temporarily stored, and the incremented or decremented address data 571b is stored in the RAM 7.
This is a circuit that outputs to 5. The RAM 75 has a function of storing, for example, calculation result data S75 on the data bus 100 and outputting the stored calculation result data S75 to the data bus 100 according to the address data 571b. The pointer 72 receives address data 572 that is incremented or decremented according to the address data 572a output from the pipeline register 63, the arithmetic unit 80, or the I10 unit 90 to the data bus 100.
There is a circuit for outputting the data b to the RAM 76. The RAM 76 stores data S76 on the data bus 100 for randomly accessing the ROM 77, and stores address data 5.
It has a function of outputting the stored data S76 to the data bus 100 and the selector 74 in accordance with 72b. Selector 74 selects data bus 10 according to microinstruction S64.
This circuit selectively outputs address data 0Jx or address data 376 output from the RAM 76 to the pointer 73. The pointer 73 transfers address data 873 that is incremented or decremented according to the address data output from the selector 74 to the ROM.
This is a circuit that outputs to 77. The ROM 77 has a function of storing operand data S77 to be multiplied and outputting the stored data S77 to the multiplier via the data bus 100 and a selector described later in accordance with address data S73.

The operation q8 unit 80 includes selectors 81, 82, 83, and a multiplier 8.
4, equipped with ALU85 and ACC86, RAiV17
A selector 81 connected to the output side of the ROM 77 and the data bus 100, and a selector 82 connected to the output side of the ROM 77 and the data bus 100 are connected to the multiplier 84. The output side of the multiplier 8/1 and the data bus 100 are connected to one input side of the ALU 85 via the selector 83, and the A1. ．． The output of 185 (the other input side of ALU 85 via ACC 86 and the data bus 10
Connected to 0.

The selector 81 selects the RAM according to the microinstruction S64.
This circuit selectively outputs the output data of 75 and the data on the data bus 100 to the multiplier 84. The selector 82 selectively converts the output data of the ROM 77 and the data on the data bus 100 into a multiplier 84 according to the microinstruction S64.
This is a circuit that outputs to. Multiplier 84 selector 81 .
Multiply the output data of 82, and the multiplication result 8
4 to the selector 83. The selector 83 selects the multiplier 84 according to the microinstruction S64.
There is a circuit for selectively outputting the multiplication result S84 or the data on the data bus 100 to the ALU 85. ALU8
5 is a circuit that performs arithmetic and logical operations according to the output data of the selector 83 and the output data S86 of the ACC 86. The ACC 86 temporarily stores the calculation result S85 of the ALU 85, and transfers the stored data S86 to the data bus 100 and the ALU 85.
There is a register that outputs to L U85.

The input/output unit 90 includes an I10 register 9 for storing data.
1, and an I10 buffer (not shown), etc.
Input data S9 from outside through I10 port 101
0 to the data bus 100,
It has a function of outputting the above data S90 to the I10 port 101.

FIG. 3 is a circuit diagram showing an example of the configuration of the selector in FIG. 1.

Selectors 74, 81-83 in FIG. 1 are constructed of the same circuit. Among them, for example, the selector 74 has a plurality of unit circuits 74-1 to 74-N, and each of these unit circuits 74-1 to 74-N is composed of a plurality of NAND gates (hereinafter referred to as NAND gates). ing.

FIG. 4 is a time chart of FIG. 1, and the calculation operation of FIG. 1 will be explained with reference to this diagram.

For example, a case will be described in which the above formula (1) is calculated. In addition, variable B・
(i=1 to 10) are sequentially stored in the RAM 75, variables Cj (i-1 to 10) are input in advance from the I10 register 91 to the RAM 76 in order, and a log conversion table is stored in the ROM 77. Operation result A・
is transferred to the I10 register 91.

The calculation of equation (1) above is executed in order according to the following steps (1) to (2) by various microinstructions 364 output from the decoder 64.

■ The pipeline register 63 transfers the first address value of the variable C stored in the RAM 76 to the data bus 1.
-00 and set in pointer 72.

- From the pipeline register 63, set the first address value of the variable B stored in R, AM75 to the pointer 71 through the data bus 100, and according to the address data 572b output from the pointer 72, data S76 is transferred from the RAM 76. and inputs the data S76 to the pointer 73 via the selector 74.

■ RAM75 and RO according to address data 571b and 873 output from pointers 71 and 73] VI77
From the variable B1 and the logarithm, respectively. , C1, and executes B 1 xLogC1 in the multiplier 84 through the selector 81.82, and increments the pointer 71.72.

(2) The multiplication result S84 is stored in the ACC 86 via the selector 83 and ALU 85.

■ Transfer the multiplication result S86 stored in the ACC 86 to the I10 register 91 via the data bus 100, and also transfer the address data 57 output from the pointer 72.
2b, data 876 is output from the RAM 76, and the data S76 is input to the pointer 73 via the selector 74.

■ Pointer 71. ``According to address data 571b and 373 output from RAM 75 and ROM 77, variable B2 and logarithm are output from RAM 75 and ROM 77, respectively. Output gc2, execute B2xLogC2 in multiplier 84 through selector 81.82, and increment pointer 71.72. do.

■ Multiplication result S84 is sent to selector 83 and AL, tJ
85 and stored in the ACC 86.

■ Stored in ACC86. The multiplication result S86 is transferred to the I10 register 91 via the data bus 100, and the address data 5 output from the pointer 72 is
72b, outputs data S76 from RAM76,
The data S76 is passed to the pointer 73 via the selector 74.
Enter.

Thereafter, by repeating steps ① to ② eight times, the calculation result AIO can be obtained.

This embodiment has the following advantages.

(a> Since the data to be multiplied is accessed using the RAM 76, by writing the address in the RAM 76 in advance, random addressing to the ROM 77 can be done with an extremely small number of steps (number of instructions). For example, when performing 10 multiplications (Alb) in equation (1) above, 41 instructions were required in a conventional DSP, but in this embodiment, it can be executed with 32 instructions, reducing the number of instructions by approximately 25%. This means that it has been reduced. 2.
By giving the output data S76 of the RAM 76 to the pointer 73 through the selector 74, n0M77 is accessed, and since the data bus 100 is not occupied during this time, parallel instructions that use the data bus 100, such as output data of ACC86, are accessed. (S86) to data bus 10
The instruction to transfer the data to the ■10 register 91 via 0 can be executed at the same time. Therefore, high speed and high efficiency of digital signal processing can be achieved.

(b) Selector 7 selects the data on data bus 100-hi.
4 to the pointer 73, the ROTVI 77 can be accessed by the value of ("EX" on the data bus 100.

FIG. 5 is a schematic structural block diagram of a DSP showing a second embodiment of the present invention, and elements common to those in FIG. 1 are given the same reference numerals.

In this DSP, instead of the storage section 70 in FIG.
is connected to. The selector 78 has a ROM on its input side.
77 and the output side of RAM 76, and the output side thereof is connected to multiplier 84 via selector 82. This selector 78 is set to ROM by microinstruction S64.
This circuit selects the output data S77 of the RAM 77 or the output data S76 of the RAM 76 and supplies it to the multiplier 84 via the selector 82, and is constructed of, for example, a circuit as shown in FIG. When such a selector 78 is provided,
The output data S76 of the RAM 76 can be input directly to the multiplier 84, thereby improving the calculation efficiency.

FIG. 6 is a schematic structural block diagram of a DSP showing a third embodiment of the present invention, and elements common to those in FIG. 5 are given the same reference numerals.

In this DSP, instead of the storage section 70A in FIG.
A storage section 70B in which M76 and ROM 77 are replaced is connected to the data bus 100.

In this storage section 70B, the output value of the ROM 77 is used as the address value of R,0M76, so that it is stored in the ROM 77. Fixed data allows RAM 76 to be accessed, thereby providing substantially the same advantages as the first and second embodiments.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a) In FIG. 5, if the ROM 77 is replaced with a RAM, data can be rewritten.

However, since RAM has a larger formation area than ROM,
The area occupied by the storage unit 70A increases.

(b) Other circuits such as registers and multipliers may be added to the arithmetic unit 80.

(Effects of the Invention) As described above in detail, according to the present invention, the second storage means is composed of a ROM and a RAM, and the addressing of the negative memory is performed by the other memory. By writing an address in the other memory, random addressing to one memory can be performed with an extremely small number of instructions (for example, one instruction), and in addition, the data bus is not occupied during the addressing period. Parallel instructions such as those that operate on a data bus can be executed simultaneously, and as a result, digital signal processing can be expected to be faster and more efficient.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a DSP showing a first embodiment of the present invention, FIG. 2 is a configuration block diagram of a conventional DSP,
3 is a circuit diagram of the selector in FIG. 1, FIG. 4 is a time chart of FIG. 1, and FIGS. 5 and 6 are a circuit diagram of the selector of the present invention.
FIG. 7 is a configuration block diagram of a DSP showing a third embodiment. 60... Control unit, 61... Program counter, 62... Program ROM, 63...
... Pipeline register, 64 ... Decoder, 70.70A. 70B...Storage section, 71, 72.73...
...Pointer, 74.78...Selector, 75
．． 76...Tune RAM, 77...ROM, 8o...
... Arithmetic section, 84 ... Multiplier, 85 ...
...ALU, 86...ACC190...
...Part I10.

Claims (1)

[Scope of Claims] A control system comprising a program memory for storing program data, reading means for sequentially reading the program data, and means for outputting a plurality of microinstructions based on the program data read from the program memory. a storage unit having first and second storage means for storing operand data, respectively; a multiplier that multiplies data output from the first and second storage means; an output of the multiplier; an arithmetic logic unit connected to the side, and an arithmetic unit having an accumulator that temporarily holds the output of the arithmetic logic unit and inputs the output to the arithmetic logic unit; and data transfer between the control unit, the storage unit, and the arithmetic unit. In the digital signal processor, the first storage means includes a memory that can be read and written at any time, and the second storage means includes a read-only memory and a memory that can be read and written at any time. A digital signal processor characterized in that the addressing of one memory is specified by the other memory.