JPH0259945A - Memory control circuit - Google Patents

Abstract

PURPOSE:To reduce the load of program structure by storing a jump instruction following a bank switching instruction in plural program ROMs. CONSTITUTION:The jump instruction following the bank switching instruction is stored in each of plural program ROMs 2a, 2b,.... At the time of recognizing the access of a next instruction, a next instruction detecting circuit 102 outputs its detecting signal, and when a ROM chip select signal(ROMCS) is outputted, a ROM address count circuit 103 applies an authorized signal to a bank switching instructing circuit 104 and bank instructing data for determining a specified ROM is outputted from a bank specifying port 6. Since a jumped address of a newly specified ROM is already outputted to an address bus 4 at the time of executing bank switching, the load of software construction for providing a bunk switching function can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory control circuit applied to microprocessors used in various electronic devices.

(Prior Art) In recent years, microcomputers have been used in products in various fields, and their program capacities have tended to increase.

Although the processing power of microcomputers has improved from 4 bits, 8 bits, 16 bits, and even 32 bits, it is especially important for consumer devices to use microcomputers that are as inexpensive as possible to efficiently run relatively large programs. It is hoped that

Although a microcomputer has a defined memory area that it can directly handle, as the number of programs increases, the ROM or RAM capacity becomes insufficient as a system, and multiple program ROMs are required. There is.

In such cases, bank switching means is employed to expand the program address space of the microcomputer.

Figure 5 shows a conventional microcomputer program R.
OM control means is shown. Central processing unit (C
(referred to as PU) 1 includes a plurality of program ROMs 2a, 2
b, 2cm, etc. via a data bus 3 and an address bus 4. The address bus 4 is further connected to an address decoder 5 constituting bank switching means.

The address decoder 5 receives the address from the address bus 4.

It decodes the memory request signal (MREQ) from the CPUI and the input/output request signal (IOREQ) to generate a chip select signal (ROMC8) that is the timing to activate the ROM. On the other hand, the data bus 3 is also connected to the bank designation port 6. The bank designation port 6 stores bank designation data output from the CPUI, and this bank designation data allows the program ROMs 2a, 2b,
2 One of these is specified in c...

For example, when the chip select signal (ROMC8) is output under a situation where the program ROM 2a is specified, the program ROM 2a becomes active at this timing. The read state is determined by a read or write signal (RD) from the CPUI.

Note that the system clock is supplied from the clock generation circuit 7 and the interrupt signal is supplied from the interrupt source circuit 8 to C0UI.

When an interrupt signal is input, the CPUI accesses the interrupt sequence area of the ROM that is currently being accessed and executes the interrupt program.

An example of the operation of the above memory control circuit will be described with reference to FIG.

Now, as shown in FIG. 6, the program ROMs 2a, 2b
, 2c, each sequence instruction in the memory space is as shown in the figure.

In the figure, (X-2), (X), ... (Y+2).

(Y), (W), and (Z) are addresses of each ROM. Also, rLDA, OIJ is an instruction to load "1" into the A register.

rOUT (n), ALJ is an instruction to output the contents n of the A register.

rJP ZJ is an instruction to jump to address Z at this step.

IMP WJ is an instruction to jump to address W at this step.

It is.

Now, ROM2a is specified and address (X-2)
If the instruction at the address is executed, “1” is written in the A register.
, that is, the specification data specifying ROM2b is stored,
It is sent to bank designated port 6. Next, when the CPUI address counter is incremented, rOUT (
n), ALJ is executed and an input/output request signal (IOREQ) is output at the same time. As a result, a timing signal is supplied from the address decoder 5 to the bank designation port 6, and the ROM 2b becomes active.

At this time, since the CPU program counter is automatically incremented, the address (X+2) is designated as the address of the ROM 2b. What should be noted here is that there is no problem if the next instruction following the program instruction that has been executed so far is stored at address (X+2) in ROM2b, but this limits the program storage to ROM2b. will occur. Therefore, normally, at address (X+2) of ROM2b (the next specified ROM address following the previous specified ROM address when switching banks),
A jump instruction for jumping to the address where the next instruction to be executed is stored is stored. FIG. 6 shows two examples of the route indicated by the arrows ■ and the route indicated by the arrow ■.

In this way, in the conventional memory control circuit, for example, R
If there is a bank switching command at address (X) of OM2a, the selected ROM (for example, RO
The next instruction or a jump instruction indicating a jump destination where the next instruction is stored must be stored at address (x+2) of M2b).

With such program storage constraints, multiple ROs
When storing a large-capacity program using M, it places a heavy burden on the software, and mistakes are likely to occur when building the software.

Next, in the case of a conventional memory control circuit, no matter which ROM program the CPU is operating on, if it is configured to accept interrupt signals, the CPU will execute the command. For this reason, it is necessary to reserve exactly the same interrupt area in the same corresponding area in each ROM. This means that the programs in the interrupt areas of each ROM are duplicated, resulting in waste.

Furthermore, in the case of conventional memory control circuits, jump instructions can only be effectively used on the same bank.

The address area of each bank (ROM) is the same, jumps can only be made on the same bank, and R
If you want to move from address (Y) of OM2c to address (W) of ROM2a, move to (Y+2) of ROM2a on -d.
There is no other way than to move to address (by executing bank switching) and then jump to address (W) of ROM2a using a jump command.

(Problem to be Solved by the Invention) According to the conventional memory control circuit described above, first, in order to execute the next instruction in conjunction with bank switching, the next instruction that follows one step after the previously specified ROM address is It is necessary to store the jump instruction in the ROM address specified by the jump instruction and move on to the next instruction, which puts a heavy burden on software construction. Also, the area for interrupt processing is
It is necessary to ensure that each ROM has exactly the same content.
area is wasted. Furthermore, different R
When jumping to an arbitrary address in OM, in order to increment the address of the CPU, it is necessary to switch the bank and jump using the newly specified ROM jump instruction, which requires building software. It's a big burden.

Therefore, this invention reduces the burden on the programmer when constructing software to provide a bank switching function, and also provides a function for interrupt processing.
An object of the present invention is to provide a memory control circuit that can improve the area usage efficiency of a ROM.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes an addressing means for giving a common address to a plurality of program ROMs, and a method for reading data from any of the program ROMs by the addressing means. a sequence processing means that reads a sequence command and operates based on this command; and a sequence processing means that operates based on this command; and a bank switching means for switching a designated ROM among the plurality of ROMs to an active state, wherein the plurality of program ROMs store a jump instruction following the bank switching instruction, and The sequence processing means outputs the bank switching command to the bank switching means, waits until the next jump command is determined, and based on this jump command (the address is derived from the addressing means to the bus). The present invention further includes bank switching timing control means for causing the bank switching means to execute a bank switching command at a certain stage.

The present invention also provides an interrupt processing unit that detects that an interrupt processing command is input to the sequence processing means and outputs a specific bank switching command that automatically activates a specific ROM among the plurality of program ROMs. introduction means and when a particular ROM is selected by this interrupt introduction means.

A bank switching instruction that specifies the ROM that was selected before this selection is stored, and when the sequence processing means detects the end of interrupt processing from the sequence instruction that is processing the interrupt, the bank switching instruction that specifies the ROM that was selected before this selection is stored. A bank switching command is given to the bank switching means to control the RO before the interrupt.
and interrupt return means for returning M to an access state.

(Function) By the above means, it is possible to establish a principle in which jump instructions to be stored in a plurality of program ROMs are automatically stored next to a bank switching instruction, so that the burden of program construction is reduced.

Further, the program for division processing can be stored in one ROM, and other ROMs can be used efficiently.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which differs from the conventional circuit in that a bank switching timing control section 100, an interrupt introduction section 2001, and an interrupt recovery section 300 are newly provided. The other parts are the same as the conventional circuit, and are therefore given the same reference numerals as in FIG.

Bank switching timing control will be explained.

Bank designation data for determining which of the multiple program ROMs 2a, 2b, 2c, and river to designate is as follows:
It is applied to the bank designated port via the data bus 3 and the bank switching port 101.

The bank designation port 6 does not output the bank designation data immediately, but only outputs the bank designation data when a timing pulse is supplied to its output timing terminal 0ut-T.

The timing pulse to the output timing terminal 0ut-T is sent to the bank switching instruction circuit 104 of the bank switching timing control section 1oo, the next instruction detection bank switching instruction circuit 202 of the interrupt introduction section 20, or the bank specification return of the interrupt return section 300. It is given from the instruction circuit 303.

The bank switching control section 100 includes a next instruction detection circuit 102, a ROM access count circuit 10B, and a bank switching instruction circuit 104.

The next instruction detection circuit 102 receives a memory request signal (MRE Q) and an input/output request signal (I
A standby state is entered in which it is detected whether there is a next instruction based on OREQ). To detect the next command, it is sufficient to monitor the M1 signal output from the CPUI. A lot of CPU
1 outputs a fetch machine cycle small signal (M1 signal) each time sequence processing progresses, so when the state of this signal changes, it is recognized that the next instruction has been loaded. In this embodiment, as will be described in detail in FIG. 2, a jump instruction is always stored after a bank switching instruction.

This jump instruction does not jump to the ROM currently being accessed, but to the next ROM selected by bank switching.
This is M's jump destination. When the next instruction detection circuit 102 recognizes that the next instruction has been accessed, it provides the detection signal to the ROM access capacitor circuit 103. This R.O.
The M access count circuit 103 issues a bank switching instruction time when the next instruction is detected at the time when the ROM chip select signal (ROM CS ) is output, that is, in synchronization with the ROM being activated. 1810
Give a permission signal to 4. Only after this operation is obtained, bank designation data for determining the designated ROM is output from the bank designation port 6.

When bank switching is performed in this manner, the newly specified jump destination address of the ROM has already been output to the address bus 4. Therefore, unlike in the past, there is no need to store the jump destination instruction for the next instruction in the newly specified ROM, and the programmer only needs to pay attention to the address of the ROM that stores the software programmer. You just need to know where to jump.

The bank switching operation will be explained with reference to FIG.

In FIG. 2, from the access state of ROM2a,
It is assumed that bank switching is performed in the access state of the ROM 2b. The instruction of ROM2a is r at address (X-2).
LD A, rOUT (n) at address 0IJ (X),
rJP ZJ is stored at address ALJ(X+2). Here, (Z) indicates the jump destination of ROM2b. When programmed in this way, in this embodiment, when address (X) is accessed, bank switching designation data is not immediately output from bank designation port 6, and address (X+2) is accessed by the address increment of CPU1. It will be latched until the Then, the bank switching timing control circuit 100 executes bank switching only when the jump destination address (Z) is output to the address bus 4. Therefore, bank switching is performed and the instruction at address (Z) (jump destination) of the ROM 2b is accessed. Figure 2 shows the sequence route ■
Examples of two routes are shown. ■The route is RO
This is an example in which a bank switching command is issued while M 2 c is being accessed, instructing switching to ROM 2 a. The meaning of each command is as explained in FIG.

The above operation is shown in a sequence flow as shown in FIG.

In this embodiment, bank switching is performed as described above. Furthermore, this circuit is designed to allow efficient use of the ROM even when interrupt processing is performed. That is, the interrupt introducing section 200 will be explained. The interrupt signal is supplied from the interrupt source circuit 8 to the CPUI, and is also supplied to the interrupt detection circuit 201 that constitutes the interrupt introducing section 200. Then, the interrupt detection circuit 201 provides the detection signal to the next instruction detection and bank switching instruction circuit 202. As a result, when the next instruction detection and bank switching instruction circuit 202 detects the next instruction using the M1 signal, it forcibly switches to the specified state of a specific ROM via the bank specification port 6. Therefore, at the time of an interrupt operation, a specific ROM is always specified, so the interrupt area may be reserved only in this specific ROM.

Further, when a specific ROM is designated, the bank designation data of the ROM that has been designated so far is simultaneously stored in the pre-interrupt bank designation storage circuit 304.

Next, the interrupt recovery unit 300 will be explained.

The interrupt return unit 300 includes an interrupt end recognition port 301,
Next instruction detection circuit 302, bank specified return instruction circuit 303
Consisted of. When the interrupt processing is finished, a flag can be obtained from the final address of the interrupt area, for example.
This is obtained via the address decoder 5. When the interrupt completion recognition port 301 detects this flag, the next instruction detection circuit 302 enters a standby state to detect the output of the next instruction. Next instruction detection circuit 302 detects M1
When detecting the output of the next instruction by the signal, the bank designation return instruction circuit 303 provides a timing signal to the bank designation port 6. At this time, the bank designation circuit 6
The bank designation data stored in the pre-interrupt bank designation storage circuit 304 is output. As a result, when the interrupt processing ends, the ROM specified before the interrupt is replaced by 9.

As described above, the interrupt introduction section 200 and the interrupt return section 300
By operating, if there is an interrupt instruction,
When the interrupt area access state of a specific ROM is forcibly switched, and the interrupt processing is completed, the state returns to the specified state of the ROM that was in the access state before the automatic interrupt. Therefore, it is not necessary to reserve the interrupt area in all ROMs, but it is sufficient to reserve the interrupt area only in a specific ROM, and the efficiency of ROM usage can be greatly improved. FIG. 4 shows a flowchart when the above interrupt processing is performed.

[Effects of the Invention] As explained above, according to the present invention, it is possible to reduce the burden on the programmer when constructing software for providing a bank switching function, and to provide a function for performing interrupt processing. The area usage efficiency can be improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams for explaining the bank switching operation of the circuit in FIG. 4 is an explanatory diagram shown to explain the operation of the circuit in FIG. 1 during interrupt processing, FIG. 5 is a block diagram showing a conventional memory control circuit, and FIG. 6 is a block diagram showing the conventional memory control circuit.
FIG. 3 is an explanatory diagram shown for explaining bank switching operation of the circuit shown in the figure. 1... Central processing unit (CPU), 2a, 2b. 2C1...Program ROM, 3...Data bus,
4...Address bus, 5...Address decoder, 6
...Bank designated port, 7...Clock generation circuit,
8... Interrupt source circuit, 100... Bank switching timing control section, 200... Interrupt introducing section, 300
...Interrupt return unit, 101...Bank switching port, 102.302...Next instruction detection circuit, 103...
ROM access counter, 104... Bank switching instruction circuit, 201... Interrupt signal detection circuit, 202...
・Next instruction detection and bank switching instruction circuit, 301...
Interrupt end recognition board, 303...bank return instruction circuit, 304...pre-interrupt bank designation storage circuit. Applicant's representative Patent attorney Takehiko Suzue! I! ! 1.

Claims (2)

[Claims] (1) Addressing means for giving a common address to a plurality of program ROMs, and a sequence process that reads a sequence instruction read out from one of the program ROMs by this addressing means and operates based on this instruction. and in response to processing of a bank switching command specifying one of the program RAMs in the command determined by the sequence processing means;
In a memory control device comprising bank switching means for switching a designated ROM among the plurality of ROMs to an active state, a jump instruction is stored in the plurality of program ROMs following a bank switching instruction, and the sequence processing The means outputs the bank switching command to the bank switching means, and then waits until the next jump command is output, and when the address based on this jump command is led out to the bus by the addressing means,
A memory control circuit comprising bank switching timing control means for executing a bank switching command from the bank switching means. (2) Addressing means for giving a common address to a plurality of program ROMs, and a sequence process that reads a sequence instruction read out from one of the program ROMs by this addressing means and operates based on this instruction. and in response to processing of a bank switching command specifying one of the program RAMs in the command determined by the sequence processing means;
In a memory control device comprising bank switching means for switching a designated ROM among the plurality of ROMs to an active state, it is detected that an interrupt processing command is input to the sequence processing means, and automatically switches the plurality of ROMs to an active state. an interrupt introducing means for outputting a specific bank switching instruction to activate a specific ROM among the program ROMs, and when a specific ROM is selected by the interrupt introducing means, a ROM that was selected before the selection is specified; A bank switching instruction to be executed is stored, and when the sequence processing means detects the end of interrupt processing from a sequence instruction that is processing an interrupt, the previously stored bank switching instruction is given to the bank switching means. 1. A memory control circuit comprising: interrupt recovery means for returning a ROM to an access state before the interrupt.