JPH025694A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To satisfactorily decode a teletext signal regardless of jitter by temporarily writing the signal in a storage circuit and reading out it based on the same signal as a reference signal used for frequency conversion of a color signal and inputting it to a character broadcast signal decoder. CONSTITUTION:The teletext signal is extracted from the luminance signal, which is demodulated by a luminance signal reproducing circuit 30, at the timing following up jitter and is temporarily stored in memories 41 and 42. The teletext signal is read out from memories 41 and 42 based on the phase of a reference oscillator 27, and the teletext signal of the Y signal is substituted with this teletext signal. The read signal from memories 41 and 42 is inputted to a signal mixer 50 through switches 61 and 62 and is mixed with the video signal removed by a character signal removing circuit 49, and the result is outputted as the luminance signal. Consequently, character data can be surely decoded even by a conventional teletext signal decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal reproducing device for reproducing video signals including teletext signals.

[Conventional technology]

Teletext broadcasting is a horizontal scanning period in which there is no video signal during the vertical blanking period of the video signal, for example, 14 to 16H, 21H in an odd field, and 277 to 2 in an even field.
The teletext signal is superimposed on the 79H1284H, and the teletext signal over one horizontal scanning period consists of a synchronization section consisting of a colorverse (usually colorverse) CB, a clock run-in CR and a framing code FC, a blifix, It consists of a 22-byte data block and a data bucket part DP consisting of a check code.

FIG. 4 is a block diagram showing the configuration of a teletext signal decoder for extracting teletext signal data from a conventional video signal reproducing device.

The frequency of the sampling clock for extracting teletext signal data is set to, for example, 5.72727 MHz, and this clock frequency is determined by two PLL (phase locked loop) circuits based on the color burst CB in the video signal. Created in 14.15. That is, the color burst in the input video signal is 3.58
The color burst signal CB is taken out through the MHz band pass filter 1 and the burst gate 2, and the color burst signal is extracted in the first PLL circuit 14 by the VXO 14b using the 3.58 MHz crystal oscillator 14a and the phase detector 14c. A phase-synchronized 3.58 MHz signal is created and sent to the second PLL circuit 15.

The clock frequency of 5.727 MHz is 815 times the color subcarrier frequency of 3.579 MHz, and the horizontal scanning frequency f
Using the relationship that it is 364 times H, the second PL
The L circuit 15 is 5. A VXO 15b using a 727 MHz crystal oscillator 15a, a 1/8 power counter 15C, a phase detector 15d, and a frequency dividing circuit 11 that divides the output of the PLL circuit.
A sampling clock having a frequency of 5.727 MHz is created by the 5 counter 15e.

This sampling clock signal is input to the frame pulse flywheel circuit 9 of the framing code detection circuit via a delay line 13 controlled by the sub CPU 12.

Further, a synchronizing signal is separated from the video signal by a synchronizing signal separation circuit 3, and this synchronizing signal is delayed by a pulse delay circuit (not shown) and inputted to the burst gate 2 described above.
Further, only the vertical synchronizing signal is extracted by the vertical synchronizing signal separation circuit 4 and is input to the pulse generator 5 including a monostable multivibrator. This pulse generator 5 generates a pulse for a period including the line on which the teletext signal is superimposed from the fall of the synchronization signal or the rise of the vertical synchronization signal, and only during the generation period of this pulse generates the framing code from the horizontal synchronization signal. The output is input to a fuse blowing type ROM 8, which will be described later.

Furthermore, the video signal is connected to the AGC and data slice circuit 6.
The teletext signal is extracted and stored in the shift register 7 according to the sampling clock. Then, the fuse blowing type ROM 8 reads out the data stored in the shift register 7 according to the address specified by the output of the shift register 7.

In other words, "1" is stored in the ROM 8 only at address values that match the framing code pattern, and a pulse is output only when the address specified by the output of the shift register 7 matches the framing code, and the pulse causes the framing. The code is detected, and a framing code detection pulse is output to the frame pulse flywheel circuit 9, which outputs a correct framing pulse depending on the presence or absence of frame synchronization. Further, an error correction circuit 10 is provided to correct errors in the extracted teletext signal. A sampling clock is also input to this error correction circuit 10, and the sub-CPU changes the delay amount of the delay line 13 so as to minimize the error amount, thereby realizing the minimum error amount.

However, it is difficult for such a decoder to decode teletext signals recorded on a VTR.

In other words, in the low-pass conversion color method, considering the relationship between the color burst and the luminance signal, the color burst is frequency-converted to 3,579 MHz with jitter compensation, but the signal that has passed through the luminance signal system still has jitter because no compensation for jitter is performed. Therefore, character information fluctuates following jitter, whereas the sampling clock is made from color bursts, so the optimal locking phase is completely different for each field. As mentioned above, the optimum phase of the sampling clock can be determined by adjusting the delay amount of the delay line 13, but this adjustment function is achieved by a fast response characteristic that matches the phase within the clock run-in range of each data packet. Not only do they not have a different phase, but they may not be treated as character information if they have different phases.

[Problem that the invention attempts to solve]

In this way, conventional teletext signal decoders generate sampling clocks based on color bursts, so if there is jitter in the reproduced signal, the color burst signals will also be out of phase, making it difficult to match the phase of the teletext signals. There was a problem.

The present invention has been made to solve such problems, and an object of the present invention is to provide a video signal reproducing device that can satisfactorily decode using a conventional teletext signal decoder even if there is jitter in the reproduced signal. .

[Means for solving problems]

The video signal reproducing device of the present invention is a video signal reproducing device for reproducing a video signal including a teletext signal of a low frequency conversion color system, and includes a reference oscillator that outputs a reference signal, and a drum of a head that is synchronized with the reference signal. a drum rotation control circuit that controls rotation; a frequency conversion circuit that frequency-converts a low-frequency color signal of a reproduced video signal in synchronization with the reference signal; and a storage circuit that stores a teletext signal in the reproduced video signal; a writing circuit for writing a teletext signal into the storage circuit in synchronization with a luminance signal of the reproduced video signal; and a reading circuit for reading out the teletext signal written in the storage circuit at a timing based on the reference signal. , a superimposition circuit that removes the teletext signal from the reproduced video signal and superimposes the teletext signal read out by the readout circuit to produce a reproduced video signal;
iii. The color burst signal of the reproduced video signal and the teletext signal are matched in phase.

[For production]

According to the video signal reproducing device according to the present invention, drum rotation control and frequency conversion of the low-frequency color signal are performed in synchronization with the same reference signal, and teletext signals are generated in synchronization with the luminance signal of the reproduced video signal. The written teletext signal is written into the storage circuit and read out at a timing based on the reference signal, and the read teletext signal is replaced with the teletext signal of the reproduced video signal, and the color burst signal and characters in the reproduced video signal are It becomes possible to match the phases of broadcast signals.

Therefore, first, the teletext signal is once written into the storage circuit, and the signal read out based on the same signal as the reference signal used for frequency conversion of the color signal is input to the teletext signal decoder. The broadcast signal has jitter removed and is in phase with the color burst signal.

Furthermore, writing of the teletext signal to the storage circuit is performed at a timing synchronized with the luminance signal of the reproduced video signal, that is, it is performed in a manner that follows the jitter, so it is possible to write the teletext signal without missing it. can.

Furthermore, since the time axis correction and drum rotation control in the frequency conversion of the low-frequency color conversion signal are performed based on the same reference signal, the phase error between the luminance signal and the color signal, including playback jitter, can be corrected for a predetermined period of time. Since the signal is kept within a certain range around the axis, it is possible to prevent the teletext signal to be superimposed from being superimposed on the synchronization signal system of the luminance signal.

〔Example〕

A video signal reproducing apparatus according to a first embodiment of the present invention is shown in FIG.

A video head 20 for recording and reproducing video signals is provided on a rotating drum 21, and this rotating drum 21 is connected to a motor 2.
Rotationally driven by 2. The phase detector 23, frequency-voltage converter 24, mixer 25, and motor drive amplifier 26 constitute a servo system for the motor 22. The phase detector 23 detects a phase error between the 3011z reference signal outputted from the reference oscillator 27 via the counter 28 and the motor signal.

Further, a speed error of the motor 22 is detected by the frequency-voltage converter 24. The phase error and speed error are mixed by a mixer 25, and this mixed signal is used to drive the motor drive amplifier 26.
drives and controls the motor 22 to servo control the motor 22.

The reproduced signal from the video head 20 is amplified by two amplifiers. This amplified reproduction signal is input to a luminance signal reproduction circuit 30, where processing such as demodulation is performed on the FM-modulated luminance signal.

On the other hand, the amplified reproduction signal is input to a low-pass filter 31, and a low-pass color signal is extracted by the low-pass filter 31. The saturation of this low-frequency color signal is controlled by an ACC circuit (automatic saturation control circuit) 32.

The saturation-controlled low-frequency color signal is sent to the main converter 33.
The frequency is converted into a color signal at the original frequency.

The output signal of this main converter 33 is input to a signal mixer 35 via a comb filter 34.

The sub-converter 36 outputs a signal having a frequency equal to the sum of the output signal of the V6O13 and the phase shift circuit 63, and inputs the signal to the main converter 32 as a reference signal. The input of the phase shift circuit 63 is a signal with a frequency of 4Ofl+ that follows the jitter from the PLL circuit 37, where 1
The phase is shifted by 90° every horizontal scanning period, and the direction of phase shift is reversed every vertical period (so-called VH
5 PS processing). As a result, at a given frequency,
A signal whose phase changes by 90'' for each IH in each vertical period is supplied as a reference signal to the main converter 33. From this main converter 33, the original carrier color signal of the color signal subcarrier frequency fc is extracted. , to a comb filter 34. This comb filter 34 removes crosstalk signals from adjacent tracks.
The regenerated carrier color signal of the color subcarrier frequency fe whose phase has been restored is extracted and guided to the mixer 35.

The reproduced carrier color signal output from the comb filter 34 is supplied to the phase comparator via the burst gate 38, where the phase is compared with the frequency fc from the reference oscillator 27 to determine the time axis variation component of the reproduced color burst signal. After this is detected, it is supplied to V6O13 as a control signal, and its output oscillation frequency is variably controlled so that the reproduced color burst signal is stabilized at a constant phase. As a result, the time axis fluctuation component of the reproduced conveyed color signal supplied to the mixer 35 is removed.

Next, processing of the luminance signal demodulated by the luminance signal reproducing circuit 30 will be explained. In this embodiment, the teletext signal is extracted from the luminance signal at a timing that follows jitter and is temporarily stored in the memories 41 and 42, and then the reference oscillator 2
A teletext signal is read out from the memories 41 and 42 based on the phase of 7, and the teletext signal of the Y signal is replaced with this teletext signal. The details of this process will be explained using the time chart of FIG. Note that FIG. 2 (1) shows the waveform of the video signal, and FIG. 2 (2) shows the waveform of each signal (a) to (1) in FIG.
) waveform is shown.

A synchronization signal is separated from the Y signal processed by the Y regeneration circuit 30 by a synchronization signal separation circuit 43.

Among the separated synchronization signals, the horizontal synchronization signal (a) is 1/
The signal is inputted to the timing generation circuit 46 via the 2-killer-1 circuit 44. On the other hand, the vertical synchronization signal (b) is detected by the vertical synchronization signal detector 45 and is also detected by the timing generation circuit 4.
6 is input.

Further, the PLL circuit 47 generates a 364Xf11 clock signal (C) for memory writing from the horizontal synchronization signal from the 1/2 killer circuit 44.

The teletext signal extraction circuit 48 slices the teletext signal from the reproduced signal from the Y reproduction circuit 30, latches it with a clock signal, extracts character data (d), and inputs it to the timing circuit 46.

The timing circuit 46 converts the vertical synchronization signal (b) and the horizontal synchronization signal (a) into lines (14 to
16H, 21H, 277-279H.

284H) and removes the teletext signal.
e). The character signal removal circuit 49 outputs a pulse (e)
The teletext signal is removed from the Y signal at the timing of . The Y signal from which the teletext signal has been removed is input to a mixer 50.

The timing circuit 46 generates a pulse (f') indicating a period for writing the character data into the memory 41 and 42 by counting the number of clocks from the beginning of the character data (d), and inputs it to the memory write control circuit 59. . A vertical synchronization signal (b) and a clock signal (C) are further input to the five memory write control circuits.

The memory write control circuit 59 receives a clock signal (C
), a read/write control signal and a write address for the memories 41 and 42 are generated and output from the pulse (r).

The write address is reset by the vertical synchronization signal (b),
Repeated for each field. The output signal of memory write control circuit 59 is input to memory 41.42 via switch 51.52.

The switches 51 and 52 are controlled to open and close alternately by a signal obtained by dividing the frequency of the vertical synchronizing signal (b) by 1/2 by the 1/2 frequency dividing circuit 53. In this way, the character data extracted by the character data extraction circuit 48 is transferred to the memory 41.42.
are written alternately.

Pulse fsc from reference oscillator 27 (~3.58M H
z) is converted to 815 by the 815 circuit 54, and a clock pulse (i) (~5.727M1(z)) is output to the timing generation circuit 55 and the flywheel circuit 56.

The flywheel circuit 56 is a circuit that outputs a pulse that serves as a reference timing for reading data from the memories 41 and 42. Since the water synchronization signal of the reproduced video signal has jitter, the PLL circuit 57 generates an HD pulse that is approximately averaged in time, and the flywheel circuit 56
to use human power. The flywheel circuit 56 is reset by this HD pulse. When it is determined that the HD pulse is sufficiently stable, the flywheel circuit 56 cancels the reset by the HD pulse and changes the clock pulse (i) to 364.
A pulse (I) is output to the timing generation circuit 55 every time the number is counted.

Based on this pulse (h), the timing generation circuit 55 generates a pulse (1) indicating the period for reading data from the memory 41, 42 using the tarokk (1) and the vertical synchronization signal (b).
j) and outputs this pulse (j) to the memory read control circuit 60.

The memory read control circuit 60 generates and outputs a read/write control signal and a read address for the memory 4L42 from the clock pulse (1) and pulse (j). The read address is reset by the vertical synchronization signal (b) and repeated for each field. The output signal of the memory read control circuit 60 is sent to the memory 41.4 via the switch 51.52.
2 is input. Character data at the read address of memory read control circuit 60 is read from either memory 41 or 42.

That is, when character data is written in the control memory 41, the character data written one field before is read out from the memory 42, and when character data is written in the memory 42, the character data written one field before is read out. The switches 51 and 52 are controlled to open and close so that the stored data is read from the memory 41.

The read signal from the memories 4] and 42 is sent to the switches 61 and 62.
The signal is input to the signal mixer 50 via the signal mixer 50.

The switches 61 and 62 are respectively connected to the timing generation circuit 5.
Since the opening/closing is controlled by the signals (k) and (1) from 5, the read signal from the memory 41 and the read signal from the memory 42 are outputted to the signal mixer 50 for each field.

The signal mixer 50 mixes the teletext signal from the memory 41 or 42 with the video signal removed by the character signal removal circuit 49, and outputs the mixture as a luminance signal.

The signal mixer 35 mixes this luminance signal with the color signal from the main converter 33 and outputs the mixed signal as a reproduced color video signal.

As described above, according to the video signal reproducing apparatus of this embodiment, the teletext signal in the reproducing signal becomes a signal from which jitter has been removed, and moreover, the signal from the same reference oscillator 27 can be used to convert the frequency of the color signal and the character signal. Since reading is being performed, the phases of the teletext signal and color burst signal are synchronized in a certain relationship. Therefore, even a conventional teletext signal decoder as shown in FIG. 4 can reliably decode character data.

A video signal reproducing apparatus according to a second embodiment of the present invention is shown in FIG. Identical components are given the same reference numerals and explanations will be omitted.

In this embodiment, the reference pulse of the clock pulse (i) (~5.727 MHz) to the flywheel circuit 56 is not the pulse output from the reference oscillator 27, but is derived from the reproduced color burst signal output from the burst gate 38. The signal is generated by the circuit 70. As a result, the phase of the readout timing signal of the teletext signal and the phase of the color burst signal become exactly the same, and character data can be more reliably decoded.

The present invention is not limited to the above embodiments, and various limitations are possible.

For example, in the above embodiment, the extracted teletext signal is temporarily stored in the memory, but instead of the memory, a delay line such as a CCD is used and the timing of data extraction from the delay line is synchronized with the color burst signal. Good too.

〔Effect of the invention〕

As explained above, according to the present invention, the teletext signal is
Once written in the memory circuit, the signal read out based on the same reference signal used for frequency conversion of the color signal is input to the teletext signal decoder, so the teletext signal has jitter removed and is converted into a color burst. This is synchronized with the signal, and even if there is jitter in the reproduced video signal, the teletext signal can be decoded satisfactorily.

Furthermore, writing of the teletext signal to the storage circuit is performed at a timing synchronized with the luminance signal of the reproduced video signal, that is, it is performed in a manner that follows the jitter, so it is possible to write the teletext signal without missing it. can.

Furthermore, since the time axis correction and drum rotation control in the frequency conversion of the low-frequency color conversion signal are performed based on the same reference tarok, the phase error between the luminance signal and the color signal, including playback jitter, can be corrected for a predetermined period of time. Since the teletext signal can be kept within a certain range around the axis, it is possible to prevent the teletext signal from being superimposed on the synchronization signal system of the luminance signal, and it is possible to prevent adverse effects on data slicing, etc. in the teletext signal decoder. It is advantageous in this respect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal reproducing device according to a first embodiment of the present invention, FIG. 2 is a time chart of each signal in the same video signal reproducing device, and FIG. 3 is a block diagram of a video signal reproducing device according to a second embodiment of the present invention. FIG. 4 is a block diagram of a video signal reproducing apparatus. FIG. 4 is a block diagram of a teletext signal decoder which has been commonly used in the past. 20... Video head, 21... Rotating drum, 22
... Motor, 23.39 ... Phase detector, 24.3
5.50... mixer, 26... motor drive amplifier,
27...Kitei oscillator, 28...Counter, 29...
- Amplifier, 30... Luminance signal regeneration circuit, 31... Low pass filter, 32... ACC circuit (automatic saturation control circuit), 33... Main converter, 34... Comb filter, 36... ...Sub converter, 37.47,
57.70... PLL circuit, 38... Burst gate, 40... VXO. 41.42... Memory, 43... Synchronization signal separation circuit, 44... 1/2 killer circuit, 45... Vertical synchronization signal detector, 46.55... Timing generation circuit, 48
...Character data extraction circuit, 49...Character signal removal circuit, 51.52.61.62...Switch, 53...
・1/2 frequency divider circuit, 54...815 circuit, 56...
Flywheel circuit, 5...Memory write control times 160...Memory read control circuit.

Claims (1)

[Claims] A video signal reproducing device that reproduces a video signal including a teletext signal of a low frequency conversion color system, comprising: a reference oscillator that outputs a reference signal; and a drum rotation control circuit that controls drum rotation of a head in synchronization with the reference signal. , a frequency conversion circuit for converting the frequency of a low-frequency color signal of the reproduced video signal in synchronization with the reference signal; a storage circuit for storing a teletext signal in the reproduced video signal; and a frequency conversion circuit synchronized with the luminance signal of the reproduced video signal. a writing circuit for writing a teletext signal into the storage circuit; a reading circuit for reading out the teletext signal written in the storage circuit at a timing based on the reference signal; and a superimposition circuit that removes the teletext signal read by the reading circuit and superimposes the teletext signal to produce a reproduced video signal.