JPH0255810B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory access control system in a processing device system in which a plurality of devices including a processing device that prefetches instructions use a common memory bus.

[Prior art]

Conventionally, when prefetching an instruction in an information processing device, the instruction at the address next to the address of the currently executing instruction is prefetched. However, prefetching this instruction is not only meaningless if a jump occurs in a jump type instruction, but also has the drawback that the instruction to which the jump is to be jumped cannot be accessed immediately because the memory cycle is occupied, resulting in memory waiting. are doing. That is, for an instruction with a high probability of a jump being established, the instruction execution time may actually increase compared to the case where instruction prefetching is not performed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access control method that eliminates the above-mentioned drawbacks and improves the substantial execution time of a jump instruction.

[Summary of the invention]

Generally, a memory bus contention circuit is required in a system in which a plurality of processing units share one memory bus. The memory access mechanism of such a system consists of (1) determining the next instruction address, (2) sending an access request signal to the conflict determination circuit, (3) determining memory bus conflict, and (4) in case of access permission. It can be divided into four steps: sending a memory access signal, waiting until access is granted if access is not permitted, and sending an access signal when access is permitted.

As system configurations become larger, the memory bus conflict determination logic becomes more complex, and the logic delay time from inputting an access request to outputting an access permission becomes increasingly large. A machine cycle is used, and the actual memory access may occur in the next memory access cycle.

The present invention makes use of the logic delay time in the memory bus conflict determination circuit, and executes memory access cycles according to the type of instruction under the condition that the memory request of the relevant device is permitted by the memory bus conflict determination circuit. By stopping the transmission of access signals,
This allows command preemption to be prohibited.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, an instruction execution control unit 1 is connected to a memory bus conflict determination circuit 3 via a memory request signal line 2-1.
It is connected to the. Similarly, although not shown in FIG. 1, other instruction execution control units 0 and 2 are also connected to the memory bus conflict determination circuit 3 via memory request signal lines 2-0 and 2-2, respectively. 30-0, 30-
1 and 30-2 are flip-flops that accept memory requests from each instruction execution control unit. For example, when the instruction execution control unit 1 sets the memory request signal line 2-1 to “1” (that is, issues a memory request), the flip-flop 30-1 is set. The same applies to the other flip-flops 30-0 and 30-2. Numerals 31, 32, and 33 are logic gate groups that perform memory request conflict determination. Here, the memory request signal line 2-0 (flip-flop 30-0) has the highest priority, followed by the memory request signal line 2-1 ( The flip-flop 30-1) connects the memory request signal line 2
-2 (Flip-flop 30-2 is given the lowest priority. 34 is a flip-flop indicating permission of memory request;
It is set when any one of -0 to 30-2 is set and the output of the OR gate 33 becomes "1". Memory request reception flip-flops 30-0 to 30-2 and conflict judgment logic gate group 3 in this memory bus conflict judgment circuit 3
1, 32, 33, memory request permission flip-flop 34, etc., are completely the same as in the prior art.

In the embodiment shown in FIG. 1, the output line (conflict determination output signal line) 4 of the memory bus conflict determination circuit 3 is used as one input of the memory access prohibition gate circuit 8,
The other input of the memory access inhibit gate circuit 8 is an inverted signal of a memory access halt signal line 7-1, which will be described later. Of course, this memory access prohibition gate circuit 8 may be part of the memory bus conflict determination circuit 3. On the other hand, 1 of the instruction execution control unit 1
1 is an instruction register, 12 decodes the type of instruction, and when a specific instruction is issued, an AND gate 14 is
This is a decoder that sets the memory access stop signal line 7-1 to "1" through the decoder. Reference numeral 13 denotes a memory access permission signal delay flip-flop which takes a set state when a memory request from the instruction execution control section 1 is accepted and the memory access permission signal line 5-1 becomes "1". When the decoder 12 decodes a specific instruction under the set condition, the memory access stop signal line 7-1 becomes "1" via the AND gate 14.
It becomes. The specific instructions here include unconditional jump instructions and some conditional jump instructions with a high probability of a jump (for example, a count of jump instruction, which sets a certain number in a counter and The targets are instructions that can be predicted to have a high probability of jumping to a certain extent, such as instructions that jump to a specific address until the address reaches zero, and then proceed to the next address when the address reaches zero.

FIG. 2 is a time chart of instruction execution for explaining the operation of the embodiment shown in FIG. In the figure, I is an instruction fetch, X is an address modification, P is an operand fetch, and A is an operation time area, indicating that each instruction is activated one after another with a time difference equal to the instruction fetch. T _I indicates a memory bus conflict determination cycle.

Now, a memory request for fetching the next instruction (instruction at the address next to the address of the own instruction) is sent from the instruction execution control unit 1 in FIG. 1 to the memory bus conflict determination circuit 3 via the signal line 2-1. Suppose it is released.
This memory request is issued at the beginning of the memory bus determination cycle T _I. The flip-flop 30-1 is set in response to a memory request from the instruction execution control unit 1, and if the flip-flop 30-0 is not set at this time, the flip-flop 30-1 is set.
The output of -1 is selected by the gate group 31, 32, 33, and the memory request grant flip-flop 34 is set at the end of the memory bus determination cycle _TI .
By setting the flip-flop 34, the contention determination output signal line 4 becomes "1". This conflict determination output signal line 4 is connected to a memory request reception flip-flop 30-
In this case, when the signal line 4 becomes "1", the flip-flop 30-1 is restored to the reset state. Further, the fact that the memory request has been granted is sent back to the instruction execution control unit 1 via the output line (memory access permission signal line) 5-1 of the AND gate 31, and thereby the instruction execution control unit 1 accesses the memory. Set the request signal line 2-1 to "0". The above operation of the memory bus conflict determination circuit 3 is exactly the same as the conventional one.
At the same time, since the memory request of the instruction execution control section 1 is granted, the flip-flop 13 for delaying the memory access permission signal takes a set state.

The memory conflict determination cycle T _I of the above-mentioned next instruction and the instruction fetch time domain I of the previous instruction (self-instruction) overlap, and in the instruction execution control unit 1,
In parallel with the operation of the memory bus conflict determination circuit 3, the own instruction is set in the instruction register 11 and decoded. Then, the self-instruction is an unconditional jump instruction or some conditional jump instruction (a conditional jump instruction with a high probability of a jump being established).
In this case, the decoder 1 executes the instruction execution control unit 1 under the condition that the memory request of the instruction execution control unit 1 is permitted.
2, the memory access stop signal line 7-1 becomes "1" via the AND gate 14. A little later than the confirmation of this decoding, a memory bus judgment cycle is executed.
Design the circuit so that T _I ends. Therefore,
When an unconditional jump instruction or some conditional jump instructions are decoded by the decoder 12, the memory bus conflict determination circuit 3 is used to fetch the next instruction.
Even if the conflict determination output signal line 4 is set to "1", the memory access prohibition gate circuit 8 is already set to "1" since the memory access stop signal line 7-1 is
The output of is turned off, and memory access for fetching the next instruction to the instruction execution control unit 1 is prohibited. Also, memory access stop signal line 7-1
is connected to the reset terminals of flip-flop 30-1 and flip-flop 34, and when memory access stop signal line 7-1 becomes "1", the internal state of memory bus conflict determination circuit 3 set by the previous memory request is changed. It will be reset. At this time, the memory access permission signal delay flip-flop 13 in the instruction execution control section 1 is also reset.

On the other hand, when the type of the own instruction corresponds to a normal instruction, the memory access stop signal line 7-1 is “0”.
Therefore, when the conflict determination output line 4 becomes "1" to indicate access permission, the output line 6 of the memory access prohibition gate circuit 8, that is, the memory access line also becomes "1", and the memory for fetching the next instruction is Access is made. The memory request grant flip-flop 34 is then reset.

Although omitted in FIG. 1, if necessary, the memory access stop signal line 7-- can also be sent from other units.
It goes without saying that the same signal line as 1 is input to the memory bus conflict determination circuit 3 and the memory access prohibition gate circuit 8.

〔Effect of the invention〕

According to the present invention, as described above, after the memory bus conflict determination is completed, the information processing device that performs prefetch control of instructions issues an access prohibition signal under the condition that the memory request of the device is permitted, and the memory bus conflict circuit is activated. By adding the functions of resetting and inhibiting memory access, it is possible to stop instruction prefetching, so it is possible to greatly improve the performance of a program that includes many instructions with a high probability of jump establishment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the memory access control method according to the present invention, and FIG. 2 is a time chart of instruction prefetching. 1...Instruction execution control unit, 2-0, 2-1, 2-
2...Memory request signal line, 3...Memory bus conflict determination circuit, 4...Conflict determination output signal line, 6...Memory access signal line, 7-1...Memory access stop signal line, 8...Memory access Forbidden gate circuit.

Claims (1)

[Claims] 1. In a processing device system in which a plurality of devices including an information processing device that performs prefetch control of instructions use a common memory bus, a conflict between memory requests issued by the plurality of devices is determined and one of the memory requests is a memory bus conflict determination circuit that selectively notifies the device of a memory access permission signal and outputs a memory access signal;
The information processing device that performs preemption control of the instructions includes:
means for determining that a previously fetched instruction is a specific instruction and issuing a memory access stop signal under the condition that the memory bus conflict determination circuit notifies the memory access permission signal in response to a memory request of the device; and the memory bus conflict determination circuit side is provided with means for inhibiting the output of the memory access signal when the memory access stop signal arrives, and the specific instruction is fetched by the information processing device that performs prefetch control of the instruction. 1. A memory access control method characterized in that, when a memory bus conflict is determined, subsequent memory access is prohibited in the time range of memory bus conflict determination.