JPH0254979B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention transmits signals from a master station to a plurality of slave stations in a time-sharing manner, and each slave station receives signals in its own assigned time slot. This invention relates to an initial synchronization control method in a time-division multidirectional communication system that controls the transmission timing of each slave station so that the transmission signals from each slave station do not overlap at the master station.

[Conventional technology]

For example, as shown in FIG. 3, a time-division multidirectional communication network is composed of one master station A and a plurality of distributed slave stations B1 to Bn. Signals #1 to #n addressed to B1 to Bn are transmitted all at once in a time-division manner, and each slave station B1 to Bn detects a frame synchronization signal from the received signal and uses this frame synchronization signal as a reference to transmit each assigned signal. Slave station B1~Bn
It identifies the corresponding time zone, receives and processes signals addressed to its own station, and transmits signals *1 to *n, respectively, to the master station A after a predetermined internal delay time.

The signals *1 to *n transmitted by the slave stations B1 to Bn to the master station A, respectively, reach the master station A and are received after the propagation delay time between them and the master station A, The transmission signals *1 to *n of each slave station B1 to Bn are as follows:
It is necessary to set the transmission timing at the master station A so that the signals are arranged in an orderly manner on the time axis.

FIG. 4 is an explanatory diagram of the transmission/reception operation between the master station A and the slave stations B1 to Bn, where a indicates the transmission frame structure from the master station A, and signal #1 addressed to the slave stations B1 to Bn. ~#n constitute one frame F.
A frame synchronization signal (not shown) is added to the beginning of this frame F, and each slave station B1 to Bn detects this frame synchronization signal to identify the time slot assigned to the own station.

Furthermore, b, d, and f indicate received signals #1 to #3 of slave stations B1 to B3, respectively, and c, e, and g indicate transmitted signals *1 to *3 of slave stations B1 to B3. Also h
indicates received signals *1 to *n at master station A.
Also, τ1 to τ3, τ1' to τ3' are the master station A and slave station B1.
.about.B3, and Δ1 to Δ3 indicate internal delay times of the slave stations B1 to B3.

For example, slave station B1 receives the transmission signal from master station A after a propagation delay time τ1, and as shown in b, receives and processes signal #1 immediately after the frame synchronization signal as a signal addressed to its own station. , c, the signal *1 is transmitted to the master station A after a preset intra-device delay time Δ1. This transmission signal *1 will be received by the master station A after a propagation delay time τ1' (=τ1).

In addition, the slave stations B2 and B3 receive the transmission signal from the master station A after propagation delay times τ2 and τ3, respectively, and receive the transmission signal from the frame synchronization signal by 2 seconds as shown in d and f.
The second and third signals #2 and #3 are transmitted to slave stations B2 and B
As shown in e and g, the signals *2 and *3 are transmitted to the master station A after preset internal delay times Δ2 and Δ3. These transmission signals *2 and *n3 are received by the master station A after propagation delay times τ2' and τ3'. Transmission and reception is performed between the master station A and other slave stations in the same manner as described above, and the internal delay times Δ1 to Δn in each slave station B1 to Bn are
By setting control of each slave station B1 received by the master station A,
The signals *1 to *n from ~Bn do not overlap each other and are arranged in an orderly manner as shown in h.

[Problem that the invention seeks to solve]

If the propagation delay times τ1 to τn between the master station A and each slave station B1 to Bn are the same, by making the internal delay times Δ1 to Δn in each slave station B1 to Bn the same, the master station A The signals *1 to *n from the slave stations B1 to Bn are arranged in an orderly manner on the time axis. However, the distances between the master station A and the slave stations B1 to Bn are generally different, and the propagation delay times τ1 to τn (τ1' to τn') are also different. Therefore, when configuring a time-division multidirectional communication network or adding slave stations, the internal delay time Δ corresponding to the propagation delay times τ1 to τn
It is necessary to perform initial synchronization by setting 1 to Δn so that the signals *1 to *n from the slave stations B1 to Bn are arranged in an orderly manner on the time axis at the master station A.

In addition, slave stations B1 to Bn receive signals #1 to Bn from master station A.
The clock signal included in #n is extracted and signals *1 to *n are transmitted in synchronization with this clock signal, but the signals *1 to *n from each slave station B1 to Bn are
At the time when *n reaches the master station A, since the propagation delay times τ1 to τn are different, the phases are different, and the received signals *1 to *n are sampled by the reference clock signal of the master station A. When performing identification processing, if the phase difference is large, erroneous identification will occur.

Conventionally, as a means of initial synchronization for setting internal delay times Δ1 to Δn, a specific pattern signal is sent from a slave station, the master station detects this specific pattern signal, and detects the deviation from the reference specific pattern. measure,
A method is known in which information on the amount of deviation is notified to the slave station, and the slave station adjusts the internal delay time in accordance with the amount of deviation to shift the transmission timing. In this method, in order for the master station A to detect a specific pattern from the slave station, the master station A's reference clock signal is used to control the reception phase so that sampling can be identified, and then the specific pattern is detected. The amount of delay will be measured. Furthermore, it is necessary to provide specific pattern generators in the master station and slave stations, which has the disadvantage of complicating the configuration.

An object of the present invention is to perform initial synchronization in a time division multidirectional communication system with a simple configuration.

[Means for solving problems]

The initial synchronization control method of the present invention is a time-division multidirectional communication method, in which each slave station is provided with a means for transmitting an m-bit position confirmation signal that alternates between "1" and "0". Further, the master station includes a means for extracting a plurality of bits approximately in the center of the position confirmation signal in a time width smaller than m bits of the position confirmation signal and detecting a phase difference with the reference clock signal; means for extracting and counting a part of the position confirmation signal from approximately the center position in a time width corresponding to m/2 bits plus an arbitrary number of bits to detect the amount of bit delay. Information on the phase difference and information on the amount of bit delay are sent to the slave station, and the slave station uses these information to control the transmission clock phase and transmission timing.

[Effect]

The position confirmation signal is an m-bit signal that is alternately "1" and "0", and a part of the position confirmation signal received by the master station is counted, and the difference between the counted value and the reference value is calculated. Since it indicates the amount of bit delay, the difference from the counted value or reference value is sent to the slave station as bit delay amount information, and this bit delay amount information is used to adjust the delay time within the equipment of the slave station, and also to use it as a position confirmation signal. Detecting the phase difference with the reference clock signal and transmitting it to the slave station, controlling the phase of the transmission clock signal in the slave station, so that the signal from the slave station is received at a predetermined time position of the master station, Moreover, it is designed to be phase-synchronized with the reference clock signal of the master station.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, mainly showing the configuration that operates at the time of initial synchronization. In the figure, A is a master station, B is a slave station, 1 is a receiving section, 2 is a transmitting section, 3 is a clock generation circuit that generates a reference clock signal, 4 is a multiplier circuit, 5 is a detection circuit, and 6 is a detection circuit. 7 is an amplifier, 8 is an identification circuit for level discrimination, 9 is a burst signal forming circuit, 10 is a counter, 11 is a delay circuit, and 12 is a control signal applied from a control circuit (not shown) at the time of initial synchronization. Yes, also child station B
21 is a receiving section, 22 is a transmitting section, 23 is a control section that controls transmission timing, etc., 24 is a signal generation circuit that generates a position confirmation signal, and 25 is a device that controls internal delay time and transmits. A delay control circuit for determining timing, 26 a phase shift circuit for controlling the phase of a clock signal, and 27 a control signal applied at the time of initial synchronization.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention,
a shows the transmission frame structure of master station A, and b and c show examples of different timings of the m-bit position confirmation signal from slave station B, which are output from the signal generation circuit 24 of slave station B. It is. Further, d indicates a burst signal for detecting the amount of bit delay, and e indicates a burst signal for detecting a phase difference. In the embodiment shown in FIG. This shows a case where a burst signal with a bit time width is output and the burst signal is delayed by k/2 time by a delay circuit 11.
The time width of the burst signal is set to be a k-bit time width shorter than the time width of the m-bit position confirmation signal, and is set to be the sum of the m/2-bit time width and the l-bit time width. It is. Note that the burst signal shown in d can be advanced in time by k/2 with respect to the burst signal shown in e, and the burst signals d and e can be separated in time by separate circuits. It is also possible to form them so that they are different.

As shown in a, the transmitter 2 of the master station A sends a time-division signal in a transmission frame configuration consisting of a frame synchronization signal SYN, a control time slot C, and time slots #1, #2, etc. corresponding to each slave station. In the slave station B, the reception section 21 receives it, detects the frame synchronization signal SYN, applies the detection signal syn to the control section 23, and extracts the clock signal CK. This is added to the control section 23. A known structure can be used as the means for detecting the frame synchronization signal SYN and the means for extracting the clock signal ck. Also, the identification of the own station's allocated time zone during communication after initial synchronization is as follows:
Based on the detection signal syn of the frame synchronization signal SYN,
This is performed by the transmitter 21 or the controller 23. Such a control configuration is also similar to the conventional configuration.

In the control section 23, the phase of the clock signal ck is controlled by the phase shift circuit 26, and the phase of the clock signal ck is controlled by the transmission section 22.
In addition, the delay control circuit 25 also controls the detection signal syn
A transmission timing signal is formed based on the transmission unit 2.
This is in addition to 2. Also, when the control signal 27 is applied, the signal generation circuit 24 alternately outputs "1",
An m-bit position confirmation signal of "0" is output and added to the transmitter 22. The transmitting section 22 starts transmission in response to a transmission timing signal, and performs transmission in synchronization with a phase-controlled clock signal.

At the time of initial synchronization, a control signal 12 is applied to the burst signal forming circuit 9 of the master station A by a control circuit or a manual switch (not shown), and the control signal 12 is applied to the burst signal forming circuit 9 of the master station A for a time corresponding to the control time slot in the reception frame structure. At this time, a burst signal having a time width of k bits (k<m) is output based on the reference clock signal from the clock generation circuit 3 and is applied to the identification circuit 8 and the delay circuit 11. The delay circuit 11
The delayed burst signal is added as a count enable signal of the counter 10.

In the slave station B, a control signal 27 is applied to the signal generating circuit 24 by a control circuit (not shown) or a manual switch, etc., and the signals are alternately set to "1" and "1".
An m-bit position confirmation signal that is "0" is output. In this position confirmation signal, the number of bits m is set so that the time length is shorter than the time M, where M is the time that can be used for initial synchronization of all or among the control time slots C. Also, this position confirmation signal is a clock signal.
It is also possible to obtain ck by dividing the frequency by 1/2, for example.

The position confirmation signal from the signal generation circuit 24 is applied to the transmitting section 22, and is sent to the receiving section 1 of the master station A by the transmission timing signal from the delay control circuit 25 and the clock signal via the phase shift circuit 26. The signal is transmitted from the transmitter 22 so that it can be received within the control time slot C at the time. When this position confirmation signal is received by the receiving unit 1 of the master station A, the counter 10
and the multiplier circuit 4. The multiplier circuit 4 doubles the position confirmation signal so that it becomes a signal with the same period as the reference clock signal from the clock generation circuit 3, and the multiplied signal is applied to the detection circuit 5. .

The detection circuit 5 synchronizes the output signal of the multiplier circuit 4 with the reference clock signal from the clock generation circuit 3, and synchronizes when the phase of the position confirmation signal and the reference clock signal match. The detection output signal becomes maximum, and as the phase shifts, the synchronous detection output signal level decreases. Therefore, when the synchronous detection output signal of the detection circuit 5 is applied to the amplifier 7 via the low-pass filter 6 and amplified, a signal with a level corresponding to the phase difference between the position confirmation signal and the reference clock signal is obtained. 8
Level identification is performed using

The identification circuit 8 performs level identification only during the period of the burst signal, and adds the identification result to the transmitter 2, which transmits it to the slave station B as phase difference information. Incidentally, since the time when the synchronous detection output signal reaches the maximum value is the time when the phases match, it is also possible to convert the synchronous detection output signal into a digital signal and use it as phase difference information.

Further, the position confirmation signal received by the master station A is added to the counter 10 from the receiving section 1, and is counted during the period of the burst signal delayed by the delay circuit 11.
The count contents are added to the transmitter 2 and sent from the transmitter 2 to the slave station B as bit delay amount information.

When the position confirmation signal from the slave station B is received by the receiving unit 1 of the master station A as shown in b in FIG. 2 at approximately the center of the time M for initial synchronization, the burst signal shown in d is generated. When a part of the position confirmation signal is counted by the counter 10 using the count enable signal, the count becomes m/2. In other words, this count value m/2 is the reference value. For example, if the count value obtained by counting a part of the position confirmation signal is [(m+2)+1], the transmission timing of the position confirmation signal is This indicates that there is a delay of 1 bit, and in slave station B, if the intra-equipment delay time is advanced by 1 bit, it becomes the desired intra-equipment delay time. If the count value is [(m/2)-3], it indicates that the transmission timing of the position confirmation signal is advanced by 3 bits, and slave station B can delay the internal delay time by 3 bits. This results in the desired intra-device delay time. In this way, the amount of bit delay can be determined from the count value, and depending on the configuration of slave station B, the count value itself can be used as the bit delay amount information, or it is possible to use the count value itself depending on the configuration of slave station B. It is also possible to use the difference.

Also, as shown in Figure 2c, the position confirmation signal
Even in the case of extreme deviation, if an m/2-bit position confirmation signal is received within the burst signal period, the count value of the counter 10 will be m/2. In such a case, the bit delay amount is determined to be zero. However, since the position confirmation signal does not arrive during the burst signal period for detecting the phase difference, phase difference information cannot be obtained. Therefore, it can be seen that the information that the bit delay amount is zero in this case is incorrect. It is also possible to make such a judgment in the transmitter 2 of the master station A, and if the slave station B does not receive both the phase difference information and the bit delay amount information, it is possible to make such a judgment due to erroneous information. It can also be determined that there is. In this case, since the transmission timings are largely deviated, slave station B will advance or delay the transmission timing of the position confirmation signal and attempt initial synchronization again.

The slave station B that has received the bit delay amount information and the phase difference information automatically or manually controls the phase shift circuit 26 and the delay control circuit 25. The phase shift amount by the phase shift circuit 26 is adjusted based on the phase difference information. If it is done manually, a display section will be provided to display the bit delay amount information and phase difference information received from master station A, and the above-mentioned adjustments will be made. and can be adjusted together.

By adjusting the phase shift circuit 26 in the slave station B, the transmission clock signal phase is adjusted, and the reception signal phase of the master station A is synchronized with the reference clock signal phase.
In addition, the delay time within the device is adjusted, and by identifying and transmitting the own station's allocated time zone based on the detection signal syn of the frame synchronization signal SYN, the received signal at the master station A is aligned with the predetermined time position. The signals from each slave station with different propagation delay times are
At the master station A, the signals are received so that they do not overlap in time.

〔Effect of the invention〕

As explained above, the present invention provides a signal for transmitting an m-bit position confirmation signal that alternately becomes "1" and "0" to each slave station B1 to Bn in a time-division multidirectional communication system. A sending means such as a generating circuit 24 is provided,
This is to send a position confirmation signal at the time of initial synchronization, and the means for generating the position confirmation signal can also be realized by dividing the clock signal in half. This has the advantage that the configuration of slave station B is simplified.

In addition, the master station A is provided with a method for extracting k bits approximately in the center of the position confirmation signal, which are normally received in a time width shorter than m bits of the position confirmation signal, and detecting the phase difference with the reference clock signal. A phase difference detection means consisting of a multiplier circuit 4, a detection circuit 5, a low-pass filter 6, an amplifier 7, an identification circuit 8, etc., and l bits are added to m/2 bits from approximately the center position of the regularly received position confirmation signal. A bit delay amount detection means consisting of a counter 10 or the like that extracts and counts a part of the position confirmation signal in a certain time width is provided, and the phase difference information and the bit delay amount information are transmitted from the master station A to the slave station B. The slave station B uses the phase difference information to control the phase of the transmitted clock signal, and the bit delay amount information adjusts the internal delay time of the device.The master station A uses the reference clock signal This has the advantage that phase difference information and bit delay amount information can be obtained simultaneously, and initial synchronization can be performed in a short time.

In addition, in order to obtain phase difference information, by extracting k bits from approximately the center of the position confirmation signal,
This has the advantage that it is possible to eliminate portions where the phase is relatively unstable near both ends of the position confirmation signal, and accurate phase difference information can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of main parts of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the embodiment of the present invention, Fig. 3 is an explanatory diagram of the time division multidirectional communication system, and Fig. 4 is an explanation of its operation. It is a diagram. A is a master station, B is a slave station, 1 is a receiving section, 2 is a transmitting section, 3 is a clock generation circuit, 4 is a multiplier circuit, 5 is a detection circuit, 6 is a low-pass filter, 7 is an amplifier,
8 is an identification circuit, 9 is a burst signal forming circuit, 10
is a counter, 11 is a delay circuit (DL), 12 is a control signal, 21 is a reception section, 22 is a transmission section, 23 is a control section, 24 is a signal generation circuit that generates a position confirmation signal, 25 is a delay control circuit, 26 is a phase shift circuit, 27
is a control signal.

Claims (1)

[Claims] 1 A multidirectional communication network is configured by one master station and a plurality of slave stations, the master station transmits signals for each of the slave stations all at once in a time-sharing manner, and each of the slave stations communicates with the master station. In the time-division multi-directional communication system, each slave station alternately transmits "1" and "0" to the master station during its own assigned time slot in synchronization with a clock signal extracted from the transmission signal of the slave station. ”, the master station is provided with means for transmitting an m-bit position confirmation signal such that the master station transmits a plurality of bits approximately in the center of the position confirmation signal from the slave station in a time width smaller than the m bits of the position confirmation signal from the slave station. means for extracting the clock signal and detecting the phase difference with the reference clock signal; means for extracting and counting a part of the signal to detect the amount of bit delay, and transmitting information on the detected phase difference and information on the amount of bit delay to the slave station that sent the position confirmation signal, An initial synchronization control method characterized by controlling a transmission clock signal phase and internal delay time in a slave station that receives the information.