JPH0254946A - Mounting of semiconductor chip - Google Patents
Mounting of semiconductor chipInfo
- Publication number
- JPH0254946A JPH0254946A JP20676688A JP20676688A JPH0254946A JP H0254946 A JPH0254946 A JP H0254946A JP 20676688 A JP20676688 A JP 20676688A JP 20676688 A JP20676688 A JP 20676688A JP H0254946 A JPH0254946 A JP H0254946A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor chip
- circuit board
- bumps
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 12
- 239000000057 synthetic resin Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract 2
- 239000011347 resin Substances 0.000 abstract 2
- 239000012188 paraffin wax Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 10
- 210000003739 neck Anatomy 0.000 description 9
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
回路基板に半導体チップをフェースダウンに実装する方
法の改良に関し、
量産的で低コストの半導体チップの実装方法を提供する
ことを目的とし、
細径の頸部の両端に頭部を有する多数のバンプが、所定
のピッチで格子状に配列し、該頸部が合成樹脂フィルム
で固着され、それぞれの該頭部が該合成樹脂フィルムの
上面及び下面に突出した、バンプ配列層を設け、回路基
板の基板側パッドと半導体チップのパッドとが、該バン
プを介して対向するよう、該回路基板、該バンプ配列層
及び該半導体チップを重層し、該バンプを介して熱圧着
手段或いは半田リフロー手段により、該半導体チップを
該回路基板にフェースダウンに実装する構成とする。[Detailed Description of the Invention] [Summary] Regarding the improvement of the method for mounting semiconductor chips face-down on a circuit board, the present invention aims to provide a mass-produced, low-cost method for mounting semiconductor chips on a circuit board. A large number of bumps having heads at both ends are arranged in a grid at a predetermined pitch, the necks are fixed with a synthetic resin film, and each head protrudes from the upper and lower surfaces of the synthetic resin film. , a bump array layer is provided, and the circuit board, the bump array layer, and the semiconductor chip are stacked so that the board-side pads of the circuit board and the pads of the semiconductor chip face each other with the bumps interposed therebetween; The semiconductor chip is mounted face-down on the circuit board by thermocompression bonding means or solder reflow means.
本発明は、回路基板に半導体チップをフェースダウンに
実装する方法の改良に関する。The present invention relates to an improvement in a method for mounting a semiconductor chip face-down on a circuit board.
近年の電子部品及び電子機器は、軽薄短小傾向にあり、
同時に高密度化が一段と要求されている。In recent years, electronic parts and devices have become lighter, thinner, and smaller.
At the same time, higher density is required.
このような背景から半導体チップにおいても、人出力パ
ッドを集積回路を形成した表面に格子状に配列し、バン
プを介して回路基板の対応する基板側バッドに接続し、
フェースダウンに実装している。Against this background, in semiconductor chips as well, human output pads are arranged in a grid pattern on the surface on which an integrated circuit is formed, and connected to corresponding pads on the circuit board via bumps.
It is implemented face down.
バッドを格子状に配列した半導体チップは、チップの周
縁にバッドを配列したものに比較して、チップ自体を小
形にできるという、メリットがある。A semiconductor chip with pads arranged in a grid has the advantage that the chip itself can be made smaller than one with pads arranged around the periphery of the chip.
また、フェースダウンに実装することにより、チップ側
バッドと基板側パッドとが直接接続され、それだけパタ
ーン長が短くなり、高速化されるというメリットと、複
数の半導体チップを近接して実装することが可能となり
、高密度実装化が推進されるという利点がある。In addition, by face-down mounting, the chip-side pads and the substrate-side pads are directly connected, which shortens the pattern length, resulting in faster speeds and the ability to mount multiple semiconductor chips in close proximity. This has the advantage of promoting high-density packaging.
従来の半４体チップの実装方法を、第２図（ａ）。 FIG. 2(a) shows a conventional method for mounting a half-quad chip.
（ｂ）の工程図を参照して説明する。This will be explained with reference to the process diagram in (b).
第２図において、■は、シリコン基板等の表面（図の下
面）に集積回路を設けた半導体チップであって、表面に
所定のピッチ（例えば２００μｍ）で格子状にバッド２
を配列し、このようなバッドに集積回路の入出カバター
ンを接続しである。In FIG. 2, ■ is a semiconductor chip in which an integrated circuit is provided on the surface (lower surface of the figure) of a silicon substrate, etc., and pads 2 are arranged on the surface in a grid pattern at a predetermined pitch (for example, 200 μm).
are arranged and the input/output cover turns of the integrated circuit are connected to such pads.
まず、半導体チップｌのそれぞれのバッド２に、第２図
（ａ）に示すように、直径が１００μｍ程度のバンプ３
を固着する。なお、バンプ３は銅ボールを半田めっきし
たもので、半田リフロー手段により、バッド２に固着し
ている。First, bumps 3 with a diameter of about 100 μm are placed on each pad 2 of the semiconductor chip l, as shown in FIG. 2(a).
to fix. The bumps 3 are copper balls plated with solder, and are fixed to the pads 2 by solder reflow means.
第２図（ｂｌにおいて、５は、例えばセラミック基板よ
りなる回路基板であって、表面に薄膜、或いは厚膜で所
望の回路素子を設け、さらに半導体チップ１のバッド２
に対応して、格子状に基板側パッド６を配列形成しであ
る。In FIG. 2 (bl), 5 is a circuit board made of, for example, a ceramic substrate, on the surface of which a desired circuit element is provided with a thin film or a thick film, and a pad 2 of the semiconductor chip 1 is provided.
The substrate side pads 6 are arranged in a lattice pattern corresponding to the above.
このような回路基板５の表面に半導体チップ１をフェー
スダウンに重ね、それぞれのバンプ３を対応する基板側
パッド６に位置合わせし、加熱して半田リフロー手段で
、バンプ３と基板側パッド６とを半田付けして、半導体
チップ１を回路基板５に実装している。The semiconductor chips 1 are stacked face down on the surface of such a circuit board 5, each bump 3 is aligned with the corresponding board pad 6, and the bumps 3 and the board pad 6 are connected by heating and solder reflow means. The semiconductor chip 1 is mounted on the circuit board 5 by soldering.
しかしながら上記従来方法は、多数の小さい球状のバン
プ３を、一つ一つ半導体デツプ１のバッド２に載せ、そ
の後半田リフローして固着しており、作業性が劣るとい
う問題点と、球状のバンプ自体を製造するのが困難であ
るという問題点があった。However, in the above conventional method, a large number of small spherical bumps 3 are placed one by one on the pads 2 of the semiconductor depth 1, and then the solder is reflowed to fix them. There was a problem in that it was difficult to manufacture itself.
本発明はこのような点に鑑みて創作されたもので、量産
的で低コストの半導体チップの実装方法を提供すること
を目的としている。The present invention was created in view of these points, and an object of the present invention is to provide a mass-produced, low-cost semiconductor chip mounting method.
上記の目的を達成するために本発明は、第１図に示した
ように、細径の頸部１２の両端に大径の頭部１１を有す
る、良熱導電性金属よりなるバンプ１０を設ける。In order to achieve the above object, the present invention provides a bump 10 made of a metal with good thermal conductivity and having a large diameter head 11 at both ends of a small diameter neck 12, as shown in FIG. .
このようなバンプ１０を、多数所定のピッチで格子状箱
に配列し、それぞれの頸部１２を合成樹脂フィルム１５
で固着して、頭部１１が合成樹脂フィルム１５の上面及
び下面に突出したバンプ配列ＪＷ２０を設ける。A large number of such bumps 10 are arranged in a grid box at a predetermined pitch, and each neck 12 is covered with a synthetic resin film 15.
A bump array JW20 is provided in which the head portions 11 protrude from the upper and lower surfaces of the synthetic resin film 15.
次に、回路基板５の基板側パッド６と半導体チップ１の
バッド２とが、バンプ１０を介して対向するように、回
路基板５．バンプ配列層２０．半導体チップ１を重層し
、熱圧着手段、或いは半田リフロー手段により、バッド
２を一方の頭部１１に、基板側パッド６を他方の頭部１
１にそれぞれ接着して、半導体チップ１を回路基板５に
フェースダウンに実装するものとする。Next, the circuit board 5. Bump array layer 20. Semiconductor chips 1 are layered, and the pads 2 are attached to one head 11 and the substrate side pads 6 are attached to the other head 1 by thermocompression bonding means or solder reflow means.
1, and the semiconductor chip 1 is mounted face down on the circuit board 5.
上述のように頸部１２の両端に頭部１１を有するバンプ
ｌＯは、棒状のバンプ素材を転造することにより容易加
工でき、量産的であって低コストある。As described above, the bump lO having the heads 11 at both ends of the neck 12 can be easily processed by rolling a bar-shaped bump material, and can be mass-produced at low cost.
バンプ配列層２０は、それぞれのバンプ１０の頭部１１
が合成樹脂フィルム１５の上面、及び下面に突出した状
態で、格子状に配列し固定されている。The bump arrangement layer 20 has a head portion 11 of each bump 10.
are arranged and fixed in a grid pattern in a state of protruding from the upper and lower surfaces of the synthetic resin film 15.
したがって、対角線上の２つのバンプ１０に着目するこ
とにより、基板側パッド６、バンプ１０．及び半導体チ
ップｌのパッド２の位置合わせが容易に実施できる。ま
た、熱圧着手段、或いは半田リフロー手段により、総て
のバンプ１０を対応するパッド２．基板側パッド６に同
時に接着することができる。Therefore, by focusing on the two diagonal bumps 10, the substrate side pad 6, the bump 10. Also, the pads 2 of the semiconductor chip 1 can be easily aligned. Further, all the bumps 10 are bonded to the corresponding pads 2 by thermocompression bonding means or solder reflow means. It can be bonded to the substrate side pad 6 at the same time.
以下図を参照しながら、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。The present invention will be specifically described below with reference to the drawings. Note that the same reference numerals indicate the same objects throughout the figures.
第１図（ａｌ、 （ｂｌ、 （Ｃ１，（ｄ）は、本発明
方法の工程を示す図である。FIG. 1 (al, (bl, C1, (d)) is a diagram showing the steps of the method of the present invention.
第１図（ａｌに示すように、金線、アルミニウム線。Figure 1 (as shown in al., gold wire, aluminum wire.
銅線等の良導電性の金属線（例えば直径１００μｍの丸
線）よりなるバンプ素材を、例えば５００μｍのピッチ
で転造し、細径の頸部１２（頸部の長さは１００μｍ程
度）を設ける。その後、バンプ素材を切断を鎖線Ｘ−Ｘ
部分で切断して分割し、細径の頸部１２の両端に大径の
頭部１１を有する、多数のバンプ１０を設ける。A bump material made of a highly conductive metal wire such as a copper wire (for example, a round wire with a diameter of 100 μm) is rolled at a pitch of, for example, 500 μm, and a narrow neck portion 12 (the length of the neck is about 100 μm) is formed. establish. Then, cut the bump material along the chain line X-X
A large number of bumps 10 are provided by cutting and dividing into sections, each having a large-diameter head 11 at both ends of a narrow-diameter neck 12.
次に、第１図（ｂｌの断面図、（Ｃ）の斜視図に示すよ
うに、バンプ１０を垂直にして、所定のピッチ（例えば
２００μｍ）で格子状に配列し、パラフィン樹脂等でモ
ールドして、それぞれの頸部１２を一枚の合成樹脂フィ
ルムＩ５で固着して、バンプ配列層２０を設ける。Next, as shown in FIG. 1 (cross-sectional view in BL and perspective view in FIG. Then, each neck portion 12 is fixed with a single synthetic resin film I5, and a bump arrangement layer 20 is provided.
したがって、それぞれのバンプ１０の頭部１１は、合成
樹脂フィルム１５の上面及び下面に突出している。Therefore, the head 11 of each bump 10 protrudes from the upper and lower surfaces of the synthetic resin film 15.
次に第１図ｆｄｌに示すように、回路基板５の上方にハ
ンプ配列層２０を重ねて、それぞれのバンプ１０の頭部
１１を基板側パッド６に、位置合わせして載せる。Next, as shown in FIG. 1 fdl, the hump array layer 20 is stacked on top of the circuit board 5, and the head 11 of each bump 10 is placed on the board side pad 6 in alignment.
さらに、バンプ配列層２０の上方に半導体チ・ノブｌを
フェースダウンに重ね、それぞれのパッド２を、バンプ
１０の頭部１１に位置合わせして載せる。Furthermore, the semiconductor chip l is stacked face down above the bump array layer 20, and each pad 2 is positioned and placed on the head 11 of the bump 10.
その後熱圧着工具を半導体チップ１の裏面（図のの上面
）に押しつけ、バンプ１０を加熱（例えば４００℃）・
押圧して、バンプ１０の下側の頭部１１を基板側パッド
６に、バンプ１０の上側の頭部１１をパッド２に接着し
て、半導体チップｌを回路基板５に実装する。After that, a thermocompression bonding tool is pressed against the back surface of the semiconductor chip 1 (the top surface in the figure), and the bumps 10 are heated (for example, at 400° C.).
The semiconductor chip 1 is mounted on the circuit board 5 by pressing and bonding the lower head 11 of the bump 10 to the board-side pad 6 and the upper head 11 of the bump 10 to the pad 2.
バンプ材が金、銅の場合には、バンプ１０の頭部１１に
半田クリームを塗布して、半田リフロー法により、半導
体チップ１を回路基板５に実装しても良い。When the bump material is gold or copper, the semiconductor chip 1 may be mounted on the circuit board 5 by applying solder cream to the head 11 of the bump 10 and using a solder reflow method.
なお、有機溶剤槽に半導体チンブｌを実装した回路基板
５を浸漬して、必要に応じて合成樹脂フィルム１５を溶
解除去する。Note that the circuit board 5 on which the semiconductor chip 1 is mounted is immersed in an organic solvent bath, and the synthetic resin film 15 is dissolved and removed as necessary.
バンプ１０は上述のように製造することができ、量産的
である。またモールド型の下型にバンプ１０を格子状に
配列し、上型で覆ってモールド成型することにより、高
精度の配列ピンチで、バンプ配列層２０を低コストに製
造することができる。Bump 10 can be manufactured as described above and is mass-produced. Further, by arranging the bumps 10 in a lattice pattern on the lower part of the mold and covering them with the upper mold, the bump arrangement layer 20 can be manufactured at low cost with a highly accurate arrangement pinch.
さらにまた、対角線上の２つのバンプ１０を、対応する
パッドに合わせれば、他のバンプの総てが対応するバン
ドに一致する。即ち、重ね合わせ作業が極めて容易であ
る。Furthermore, if two diagonal bumps 10 are aligned with corresponding pads, all other bumps will be aligned with corresponding bands. That is, the overlapping work is extremely easy.
以上説明したように本発明は、バンプを格子状に配列し
たバンプ配列層を介して、半導体チップを回路基板に実
装する方法であって、実装の作業性が良く、且つ量産的
で、得られる半導体装置が低コストであるという、実用
上で優れた効果がある。As explained above, the present invention is a method for mounting a semiconductor chip on a circuit board via a bump array layer in which bumps are arranged in a lattice pattern, and is easy to work with and can be mass-produced. This has an excellent practical effect in that the semiconductor device is low in cost.
第１図は本発明方法の工程を示す図、 第２図は従来方法の工程を示す図である。 図において、 １は半導体チップ、 ２はパッド、 ３．１０はバンプ、 ５は回路基板、 ６は基板側パッド、 １１は頭部、 １２は頸部、 １−５は合成樹脂フィルム、 ２０はバンプ配列層をそれぞれ示す。 参警明方法の二扛を示す図 半 １ 父 FIG. 1 is a diagram showing the steps of the method of the present invention, FIG. 2 is a diagram showing the steps of a conventional method. In the figure, 1 is a semiconductor chip, 2 is a pad, 3.10 is a bump, 5 is a circuit board; 6 is the board side pad, 11 is the head; 12 is the neck; 1-5 is a synthetic resin film, Reference numerals 20 and 20 each indicate a bump arrangement layer. Diagram showing two methods of Sankeimei method half 1 father
Claims (1)
のバンプ（１０）が、所定のピッチで格子状に配列し、
該頸部（１２）が合成樹脂フィルム（１５）で固着され
、それぞれの該頭部（１１）が該合成樹脂フィルム（１
５）の上面及び下面に突出した、バンプ配列層（２０）
を設け、 回路基板（５）の基板側パッド（６）と半導体チップ（
１）のパッド（２）とが、該バンプ（１０）を介して対
向するよう、該回路基板（５）、該バンプ配列層（２０
）及び該半導体チップ（１）を重層し、該バンプ（１０
）を介して熱圧着手段或いは半田リフロー手段により、
該半導体チップ（１）を該回路基板（５）にフェースダ
ウンに、実装することを特徴とする半導体チップの実装
方法。[Claims] A large number of bumps (10) having heads (11) at both ends of a narrow neck (12) are arranged in a grid pattern at a predetermined pitch,
The neck (12) is fixed with a synthetic resin film (15), and each head (11) is fixed with a synthetic resin film (15).
5) Bump array layer (20) protruding from the upper and lower surfaces
is provided, and the board side pad (6) of the circuit board (5) and the semiconductor chip (
The circuit board (5) and the bump arrangement layer (20) are arranged so that the pads (2) of
) and the semiconductor chip (1), and the bumps (10
) by thermocompression bonding means or solder reflow means,
A method for mounting a semiconductor chip, comprising mounting the semiconductor chip (1) face-down on the circuit board (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20676688A JPH0254946A (en) | 1988-08-20 | 1988-08-20 | Mounting of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20676688A JPH0254946A (en) | 1988-08-20 | 1988-08-20 | Mounting of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0254946A true JPH0254946A (en) | 1990-02-23 |
Family
ID=16528737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20676688A Pending JPH0254946A (en) | 1988-08-20 | 1988-08-20 | Mounting of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0254946A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04164341A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Mounting method for semiconductor integrated circuit |
| US5204574A (en) * | 1990-11-30 | 1993-04-20 | Asmo Co., Ltd. | Commutator for a motor and method of manufacturing the same |
-
1988
- 1988-08-20 JP JP20676688A patent/JPH0254946A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04164341A (en) * | 1990-10-29 | 1992-06-10 | Nec Corp | Mounting method for semiconductor integrated circuit |
| US5204574A (en) * | 1990-11-30 | 1993-04-20 | Asmo Co., Ltd. | Commutator for a motor and method of manufacturing the same |
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