JPH0254620A - Ternary logic circuit - Google Patents

Ternary logic circuit

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Publication number
JPH0254620A
JPH0254620A JP63205830A JP20583088A JPH0254620A JP H0254620 A JPH0254620 A JP H0254620A JP 63205830 A JP63205830 A JP 63205830A JP 20583088 A JP20583088 A JP 20583088A JP H0254620 A JPH0254620 A JP H0254620A
Authority
JP
Japan
Prior art keywords
current mirror
output
current
terminal
signal terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63205830A
Other languages
Japanese (ja)
Inventor
Toshihiro Kanematsu
敏裕 金松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63205830A priority Critical patent/JPH0254620A/en
Publication of JPH0254620A publication Critical patent/JPH0254620A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To operate the circuit with a low voltage power supply by constituting the circuit with the combination of a constant current source, one set of transistor(TR) pairs and 6 current mirror circuits. CONSTITUTION:The circuit consists of a constant current source I1, current mirrors 1-6 and TR pairs Q4, Q5. With an input signal terminal A at a low potential (GND), a current I1 flows to a diode D5 and a base-emitter of a TR Q7 via a TR Q5 and the current mirror 2 and an output current is absorbed from an output signal terminal C. With the input signal terminal A at a high potential (VC), a current I1 flows to a diode D6 and a base-emitter of a TR Q8 via a TR Q4 and the current mirror 3 and an output current flows out of the output signal terminal D. When the input signal terminal A is in floating or at a potential fed to a reference potential terminal E1, the current mirror 4 is energized and the current I1 flows to the diode D4 and the base-emitter of the TR Q6 and an output circuit (b) is absorbed from an output signal termi nal B.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は３値論理回路、特に、低電源電圧で動作する３
値論理回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a three-value logic circuit, particularly a three-value logic circuit that operates at a low power supply voltage.
Regarding value logic circuits.

〔従来の技術〕[Conventional technology]

従来の３値論理回路について図面を参照して詳細に説明
する。A conventional ternary logic circuit will be described in detail with reference to the drawings.

第２図は従来の３値論理回路の一例を示す回路図である
。FIG. 2 is a circuit diagram showing an example of a conventional three-value logic circuit.

第２図に示す３値論理回路は、基準電位源Ｅ２、Ｅ３の
電位関係をＥ２〉Ｅ３とすると、入力信号端子Ａの電位
が基準電位源Ｅ３より低い時は、出力信号端子Ｂより電
流が出力される。In the three-value logic circuit shown in FIG. 2, if the potential relationship between reference potential sources E2 and E3 is E2>E3, when the potential of input signal terminal A is lower than reference potential source E3, the current flows from output signal terminal B. Output.

入力信号端子Ａの電位が基準電位源Ｅ２より高い時は、
出力信号端子Ｃより電流が出力される。When the potential of input signal terminal A is higher than reference potential source E2,
A current is output from the output signal terminal C.

入力信号端子Ａの電位が基準電位源Ｅ２とＥ３との間の
時は、出力信号端子りより電流が出力される。When the potential of the input signal terminal A is between the reference potential sources E2 and E3, a current is output from the output signal terminal.

電源電圧をＶｃ、）ランジスタＱ５のエミッタと電源Ｖ
ｃ間の電圧をＶｃｅ、ｈランジスタロ４のベース・エミ
ッタ間の電圧をＶｂｅ４．トランジスタＱ５のベース・
エミッタ間の電圧をＶｂｅ６．とした場合、基準電位源
Ｅ２の電位は、Ｖｃ−（Ｖｃｅ−１−Ｖｂｅ４　＋Ｖｂ
ｅ５）以下に設定し、さらに基準電位源Ｅ３の電位は、
ＧＮＤからトランジスタ１個分のＶｂｅ電圧以上に設定
しなければならない。The power supply voltage is Vc,) the emitter of transistor Q5 and the power supply V
The voltage between the base and emitter of the transistor 4 is Vbe4. Base of transistor Q5
The voltage between the emitters is Vbe6. In this case, the potential of the reference potential source E2 is Vc-(Vce-1-Vbe4 +Vb
e5) The potential of the reference potential source E3 is set as follows.
It must be set to a Vbe voltage equal to or higher than that of one transistor from GND.

次に、基準電位源Ｅ２．Ｅ５間の電位差をトランジスタ
１個分のＶ　ｂ　ｅだけ設けた場合、この回路を動作さ
せるためには、（Ｖｃ　ｅ　十Ｖｂ　ｅ　Ｘ４）ボルト
以上の電圧（３，８Ｖ）が必要となってくる。Next, reference potential source E2. If the potential difference between E5 is set by V b e equivalent to one transistor, a voltage (3.8 V) higher than (V c e + Vb e X4) volts will be required to operate this circuit. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の３値論理回路は、動作させるために、高
電圧電源が必要であるという欠点があった。The above-described conventional three-value logic circuit has the disadvantage that a high voltage power supply is required for operation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の３値論理回路は、 （入）第１の電源端子に一端が接続された定電流源、 （Ｂ）　’ｇη記第１の電源端子に共通端が接続され、
第１のレジスタの一端に出力端が接続された第１のカレ
ントミラー、 （Ｃ）第２の電源端子に共通端が接続され、前記第１の
カレントミラーの入力端に出力端が接続された第２のカ
レントミラー、 （Ｄ）前記第２の電源端子に共通端が接続され、第２の
レジスタの一端に出力端が接続された第３のカレントミ
ラー、 （Ｅ）前記定電流源の他端に共通接続されたエミッタが
接続され、前記第２の電源端子の電位に対する基準電位
を与えるための基準電位端子に第１のベースが接続され
、前記第１と第２のレジスタの他端に第２のベースが接
続され、前記第３のカレントミラーの入力端に第１のコ
レクタが接続され、前記第２のカレントミラーの入力端
に第２のコレクタが接続されたトランジスタ対、 （Ｆ）前記第１のカレントミラーの出力端に入力端が接
続され、前記第３のカレントミラーの出力端に共通端が
接続され、第１の出力信号端子に出力端が接続された第
４のカレントミラー、（Ｇ）前記第１のカレントミラー
の出力端に入力端が接続され、第２の出力信号端子に出
力端が接続された第５・のカレントミラー、 〈１１）前記第３のカレントミラーの出力端に入力端が
接続され、第３の出力信号端子に出力端が接続され、前
記第５のカレントミラーの共通端と入力信号端子に共通
端が接続された第６のカレントミラー、 とを含んで構成される。The three-value logic circuit of the present invention includes: (Input) a constant current source with one end connected to the first power supply terminal; (B) a common end connected to the first power supply terminal;
a first current mirror whose output end is connected to one end of the first resistor; (C) whose common end is connected to a second power supply terminal; and whose output end is connected to the input end of the first current mirror; a second current mirror; (D) a third current mirror whose common end is connected to the second power supply terminal and whose output end is connected to one end of the second resistor; (E) other than the constant current source; A commonly connected emitter is connected to one end, a first base is connected to a reference potential terminal for providing a reference potential with respect to the potential of the second power supply terminal, and the other end of the first and second resistors is connected to a first base. a transistor pair having a second base connected, a first collector connected to the input end of the third current mirror, and a second collector connected to the input end of the second current mirror; (F) a fourth current mirror having an input end connected to the output end of the first current mirror, a common end connected to the output end of the third current mirror, and an output end connected to the first output signal terminal; , (G) a fifth current mirror whose input end is connected to the output end of the first current mirror and whose output end is connected to the second output signal terminal; (11) of the third current mirror; a sixth current mirror having an input end connected to the output end, an output end connected to the third output signal terminal, and a common end connected to the common end of the fifth current mirror and the input signal terminal; It consists of:

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

第１図に示す３値論理回路は、 （＾）電源端子Ｖに一端が接続された定電流源ｌ１（Ｂ
）電源端子■に共通端が接続され、レジスタＲ１の一端
に出力端が接続されたカレントミラー１　、 （Ｃ）電源端子ＧＮＤに共通端が接続され、カレントミ
ラー１の入力端に出力端が接続されたカレントミラー２
、 （Ｄ＞電源端子ＧＮＤに共通端が接続され、レジスタＲ
２の一端に出力端が接続されたカレントミラー３、 （Ｅ）定電流源Ｉｔの他端に共通接続されたエミッタが
接続され、電源端子ＧＮＤの電位に対する基準電位を与
えるための基準電位端子Ｅに第１のベースが接続され、
レジスタＲ，，Ｒ２の他端に第２のベースが接続され、
カレントミラ３の入力端に第１のコレクタが接続され、
カレントミラー２の入力端に第２のコレクタが接続され
たトランジスタ対Ｑｌ、Ｑ２、 （Ｆ）カレントミラー１の出力端に入力端が接続され、
カレントミラー３の出力端に共通端が接続され、出力信
号端子Ｂに出力端が接続されたカレントミラー４、 （Ｇ）カレントミラー１の出力端に入力端が接続され、
出力信号端子Ｃに出力端が接続されたカレントミラー５
、 （ＩＩ）カレントミラー３の出力端に入力端が接続され
、出力信号端子りに出力端が接続され、カレントミラー
５の共通端と入力信号端子Ａに共通端が接続されたカレ
ントミラー６、 とを含んで構成される。The three-value logic circuit shown in Figure 1 consists of a constant current source l1 (B) whose one end is connected to the power supply terminal V.
) Current mirror 1 whose common end is connected to the power supply terminal ■, and whose output end is connected to one end of the resistor R1, (C) whose common end is connected to the power supply terminal GND, and whose output end is connected to the input end of current mirror 1. current mirror 2
, (D>The common end is connected to the power supply terminal GND, and the resistor R
(E) A reference potential terminal E, whose output end is connected to one end of the constant current source It, and (E) a reference potential terminal E, whose emitter is commonly connected to the other end of the constant current source It, and which provides a reference potential with respect to the potential of the power supply terminal GND. the first base is connected to,
A second base is connected to the other end of the register R,,R2,
A first collector is connected to the input end of the current mirror 3,
A transistor pair Ql, Q2 whose second collector is connected to the input end of current mirror 2; (F) whose input end is connected to the output end of current mirror 1;
(G) a current mirror 4 whose common end is connected to the output end of the current mirror 3, and whose output end is connected to the output signal terminal B; (G) whose input end is connected to the output end of the current mirror 1;
Current mirror 5 whose output end is connected to output signal terminal C
(II) a current mirror 6 whose input end is connected to the output end of the current mirror 3, whose output end is connected to the output signal terminal, and whose common end is connected to the common end of the current mirror 5 and the input signal terminal A; It consists of:

入力信号端子Ａが低電位（ＧＮＤ）の時は、定電流源１
１の電流がトランジスタＱ５およびカレントミラー２を
介してダイオードＤ５とトランジスタＱ７のベース・エ
ミッタ間に流れ、トランジスタＱ７のコレクタに接続さ
れた出力信号端子Ｃより出力電流が吸込まれる。When input signal terminal A is at low potential (GND), constant current source 1
A current of 1 flows between the diode D5 and the base-emitter of the transistor Q7 via the transistor Q5 and the current mirror 2, and the output current is sucked from the output signal terminal C connected to the collector of the transistor Q7.

入力信号端子Ａが高電位（Ｖｃ）の時は、定電流源■１
の電流がトランジスタＱ４およびカレントミラー３を介
してダイオードＤ６とトランジスタＱ８のベース・エミ
ッタ間に流れ、トランジスタＱ８のコレクタに接続され
た出力信号端子りより出力電流が流出する。When input signal terminal A is at high potential (Vc), constant current source ■1
A current flows between the diode D6 and the base-emitter of the transistor Q8 via the transistor Q4 and the current mirror 3, and the output current flows out from the output signal terminal connected to the collector of the transistor Q8.

入力信号端子Ａがフローティングまたは基準電位端子Ｅ
１に印加される電位の時は、カレントミラー４が導通し
て、定電流源工、の電流がダイオードＤ４とトランジス
タＱ６のベース・エミッタ間に流れ、トランジスタＱ６
のコレクタに接続された出力信号端子Ｂより出力電流す
が吸込まれる。Input signal terminal A is floating or reference potential terminal E
1, the current mirror 4 becomes conductive, and the current of the constant current source flows between the diode D4 and the base-emitter of the transistor Q6.
An output current is sucked into the output signal terminal B connected to the collector of the output signal terminal B.

出力電流すは次式で表される。The output current is expressed by the following formula.

ｂ　　＝　　［（Ｉ＋＋−Ｖｐ　４）／（Ｒ＋＋Ｒ２）
　　］、　　／　　［（ＳＤ４／５Ｑ６）＋１　　］こ
こに １＋＋　　：定電流源の電流 Ｖｐ４：　　ダイオードＤ４の順方向電圧ＳＤ４／ＳＱ
６：トランジスタＱ６とダイオードＤ４の面積比 すなわち、入力信号端子Ａの電位が高電位（ＶＣ）の時
、定電流源Ｉｌの電圧分ＶＣｅと、トランジスタＱ４の
コレクタ・エミッタ間電圧Ｖ　ｃ　ｅＱ４と、ダイオー
ドＤ３の順方向電圧Ｖ　ｆ　ｏｓ分の電源電圧Ｖｃ＝Ｖ
ｃｅ＋ＶｃｅＱ４＋Ｖｆｏｇがあれば動作可能となる。b = [(I++-Vp 4)/(R++R2)
], / [(SD4/5Q6)+1 ] 1++ here: Current Vp4 of constant current source: Forward voltage SD4/SQ of diode D4
6: Area ratio of transistor Q6 and diode D4, that is, when the potential of input signal terminal A is high potential (VC), voltage component VCe of constant current source Il and collector-emitter voltage V c eQ4 of transistor Q4, Power supply voltage Vc for forward voltage V f os of diode D3 = V
If ce+VceQ4+Vfog is present, operation becomes possible.

入力信号端子Ａの電位が低電位（ＧＮＤ）の時、定電流
源１．の電圧分Ｖｃｅと、１〜ランジスタＱ５のコレク
タ・エミッタ間電圧Ｖｃｅｑ５と、ダイオードＤ２の順
方向電圧Ｖ　ｆ　０２分の電源電圧Ｖｃ＝Ｖｃｅ＋Ｖｃ
ｅｑ５＋ＶｆＤ２があれば動作可能となる。When the potential of input signal terminal A is low potential (GND), constant current source 1. voltage Vce, collector-emitter voltage Vceq5 of transistors 1 to Q5, and power supply voltage Vc of forward voltage Vf02 of diode D2 = Vce+Vc
If eq5+VfD2 is present, operation is possible.

入力信号端子Ａがフローティングまたは基準電位端子Ｅ
１に印加される電位の時、トランジスタＱ１のコレクタ
・エミッタ間電圧ＶｃｅＨと、ダイオードＤ４の順方向
電圧Ｖ　ｆ　ｏ４と、トランジスタＱ３のコレクタ・エ
ミッタ間電圧Ｖ　ｃ　ｅ　Ｑ３の電源電圧Ｖ　ｃ　−Ｖ
　ｃ　ｅ　Ｑ　１　＋　Ｖ　ｆ　ｎ４　＋　Ｖ　ｃ　ｅ
　（１３かあれば動作可能となり、 Ｖｃ　ｅ＃Ｖｃ　ｅｑ４：Ｖｃ　ｅｑ５＃Ｖｃ　ｅｑ３
岬Ｖｃ　ｅｌ また、 Ｖｆ岬Ｖ　ｆ　０２触Ｖ　ｆ　Ｄ３絢Ｖｆｏ４とすると
、２Ｖｃｅ十Ｖｆ分の電源電圧があれば上記３条件を満
足することができる。Input signal terminal A is floating or reference potential terminal E
1, the collector-emitter voltage VceH of the transistor Q1, the forward voltage V fo4 of the diode D4, the collector-emitter voltage V ce of the transistor Q3, and the power supply voltage V c -V of Q3.
c e Q 1 + V f n4 + V c e
(If there are 13, it becomes operational, Vc e#Vc eq4: Vc eq5#Vc eq3
Misaki Vc el Further, assuming that Vf Misaki V f 02 Touch V f D3 Aya Vfo4, the above three conditions can be satisfied if there is a power supply voltage of 2Vce plus Vf.

また、電源電圧Ｖ　ｃ　＝　２　Ｖ　ｃ　ｅ　＋　Ｖ　
ｂ　ｅは約２．７■となり低電圧化が実現できる。Also, power supply voltage V c = 2 V c e + V
b e is approximately 2.7■, which makes it possible to realize a low voltage.

本実施例では、トランジスタＱ６はＮＰＮ型を用いたが
、これをＰＮＰ型に置換えると、出力信号端子Ｂからは
流出電流が得られる。In this embodiment, an NPN type transistor is used as the transistor Q6, but if this is replaced with a PNP type, an outflow current can be obtained from the output signal terminal B.

〔発明の効果〕〔Effect of the invention〕

本発明の３値論理回路は、低電圧電源で動作できるとい
う効果がある。The ternary logic circuit of the present invention has the advantage that it can operate with a low voltage power supply.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す回路図、第２図は従来
の一例を示す回路図である。 １〜６・・・・・・カレントミラー Ａ・・・・・入力信号端子、Ｂ〜Ｄ・・・・・・出力信
号端子、■・・・・・・電源電圧端子、Ｅ・・・・・・
基準電圧端子、Ｄ１〜Ｄ６・・・・・・ダイオード、■
１・・・・・・定電流源、Ｒ１−Ｒ２・・・・・・レジ
スタ、Ｑ１〜Ｑ８・・・・・・トランジスタ、 ｂ・・・・・出力電流。 代理人　弁理士　　内　原　　晋FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1 to 6... Current mirror A... Input signal terminal, B to D... Output signal terminal, ■... Power supply voltage terminal, E...・・・
Reference voltage terminal, D1 to D6... Diode, ■
1... Constant current source, R1-R2... Register, Q1-Q8... Transistor, b... Output current. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】 （Ａ）第１の電源端子に一端が接続された定電流源、 （Ｂ）前記第１の電源端子に共通端が接続され、第１の
レジスタの一端に出力端が接続された第１のカレントミ
ラー、 （Ｃ）第２の電源端子に共通端が接続され、前記第１の
カレントミラーの入力端に出力端が接続された第２のカ
レントミラー、 （Ｄ）前記第２の電源端子に共通端が接続され、第２の
レジスタの一端に出力端が接続された第３のカレントミ
ラー、 （Ｅ）前記定電流源の他端に共通接続されたエミッタが
接続され、前記第２の電源端子の電位に対する基準電位
を与えるための基準電位端子に第１のベースが接続され
、前記第１と第２のレジスタの他端に第２のベースが接
続され、前記第３のカレントミラーの入力端に第１のコ
レクタが接続され、前記第２のカレントミラーの入力端
に第２のコレクタが接続されたトランジスタ対、 （Ｆ）前記第１のカレントミラーの出力端に入力端が接
続され、前記第３のカレントミラーの出力端に共通端が
接続され、第１の出力信号端子に出力端が接続された第
４のカレントミラー、 （Ｇ）前記第１のカレントミラーの出力端に入力端が接
続され、第２の出力信号端子に出力端が接続された第５
のカレントミラー、 （Ｈ）前記第３のカレントミラーの出力端に入力端が接
続され、第３の出力信号端子に出力端が接続され、前記
第５のカレントミラーの共通端と入力信号端子に共通端
が接続された第６のカレントミラー、 とを含むことを特徴とする３値論理回路。[Claims] (A) a constant current source having one end connected to a first power supply terminal; (B) a common end connected to the first power supply terminal and an output end connected to one end of a first resistor; (C) a second current mirror whose common end is connected to the second power supply terminal and whose output end is connected to the input end of the first current mirror; (D) the above-mentioned current mirror; (E) a third current mirror having a common end connected to the second power supply terminal and an output end connected to one end of the second resistor; (E) an emitter connected in common to the other end of the constant current source; , a first base is connected to a reference potential terminal for providing a reference potential with respect to the potential of the second power supply terminal, a second base is connected to the other ends of the first and second resistors, and the second base is connected to the other ends of the first and second resistors. (F) a pair of transistors having a first collector connected to the input end of the current mirror No. 3 and a second collector connected to the input end of the second current mirror, (F) an output end of the first current mirror; a fourth current mirror having an input end connected thereto, a common end connected to the output end of the third current mirror, and an output end connected to the first output signal terminal; (G) the first current mirror; the input terminal is connected to the output terminal of the fifth terminal, and the output terminal is connected to the second output signal terminal.
(H) an input end is connected to the output end of the third current mirror, an output end is connected to the third output signal terminal, and a common end of the fifth current mirror and the input signal terminal are connected; A ternary logic circuit comprising: a sixth current mirror having a common end connected thereto.
JP63205830A 1988-08-18 1988-08-18 Ternary logic circuit Pending JPH0254620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63205830A JPH0254620A (en) 1988-08-18 1988-08-18 Ternary logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63205830A JPH0254620A (en) 1988-08-18 1988-08-18 Ternary logic circuit

Publications (1)

Publication Number Publication Date
JPH0254620A true JPH0254620A (en) 1990-02-23

Family

ID=16513417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63205830A Pending JPH0254620A (en) 1988-08-18 1988-08-18 Ternary logic circuit

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Country Link
JP (1) JPH0254620A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2648565C1 (en) * 2017-06-01 2018-03-26 Сергей Петрович Маслов Device of the ternary circuit design on current mirrors
US11919366B2 (en) 2018-03-30 2024-03-05 Panasonic Intellectual Property Management Co., Ltd. Vehicle heating device, and vehicle provided with vehicle heating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2648565C1 (en) * 2017-06-01 2018-03-26 Сергей Петрович Маслов Device of the ternary circuit design on current mirrors
US11919366B2 (en) 2018-03-30 2024-03-05 Panasonic Intellectual Property Management Co., Ltd. Vehicle heating device, and vehicle provided with vehicle heating device

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