JPH0254335A - Data processor - Google Patents

Abstract

PURPOSE:To attain the pipeline processing with high efficiency by inputting the next instruction address and processing this address based on a unit process code. CONSTITUTION:When a subroutine jump instruction is processed, an instruction decoding means 2 decomposes a 2nd pipeline process stage into a unit process code showing the process of the head address of a subroutine and another unit process code showing the process of the return destination address sent from the subroutine and transfers these two codes through a pipeline at a 1st pipeline process stage. A PC calculation part 3 calculates the next instruction address to be used as the return destination address sent from the subroutine. Then the next instruction address obtained from the part 3 is inputted and processed as a part of the 2nd unit process code which is transferred to the 2nd pipeline process stage from the 1st one based on the 2nd unit process code at the 2nd pipeline process stage.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device that processes a variable-length instruction set, and particularly to a device that performs data processing in parallel using a pipeline processing mechanism.

[Conventional technology]

FIG. 25 is a functional block diagram illustrating vibe line processing in a conventional data processing device, in which 51 is an instruction fetch stage (IF stage), which fetches an instruction code from memory and an instruction decode stage (D stage) 52.
Output to. 53 is an operand address calculation stage (
A stage) calculates the execution address of the operand.

54 is an operand fetch stage (F stage),
Retrieve the operand according to the calculated operand address from memory. Reference numeral 55 denotes an instruction execution stage (E stage), which executes predetermined operations on operands.

Next, the operation will be explained.

1F stage 51 takes in the instruction code from memory D
Output to stage 52. The D stage 52 analyzes the instruction code manually input from the IF stage 51 and outputs the analysis result to the A stage 53. The A stage 53 calculates the execution address of the operand specified in the instruction code, and outputs the calculated operand address to the F stage 54. The F stage 54 fetches an operand from the memory according to the operand address input from the A stage 53. The fetched operand is output to the E stage 55. The E stage 55 executes the operation specified in the instruction code on the operand input from the F stage 54. Furthermore, if necessary, the calculation result is written to memory.

In a pipelined data processing device as described above, the processing specified by each instruction is broken down into, for example, five parts.
The specified process is completed by executing the five processes in order.

Each of the five processes can operate in parallel on different instructions, and ideally, five instructions can be processed in parallel using the five-stage pipeline processing mechanism described above, and no pipeline processing is performed. It is designed to deliver up to five times the processing power compared to the previous version.

In a data processing device that performs pipeline processing as described above, for example, when executing an instruction that jumps to a subroutine, the address of the next instruction after the instruction that jumps to the subroutine is used for reference in the instruction that returns from the subroutine. It is necessary to put the return address from the abroutine on the stack.

In this case, when an instruction that jumps to a subroutine is generally pipelined, the program counter (PC) calculation unit sets the beginning of the instruction that jumps to a subroutine so that the return address can be stacked on the stack in the E stage 55. Either calculate the address of the return destination instruction from the subroutine by adding the address and the instruction length of this instruction, and store it in a register that can be manipulated in the E stage 55, or add the address of the instruction to jump to the subroutine and the instruction length of this instruction. The instruction length is stored in a register that can be operated at the E stage 55, and the E stage 55 adds the two to obtain the return destination address.

Furthermore, when executing an instruction to load a value into a control register, the conditions for processing instructions to be executed thereafter change at the time a new value is written to the control register. Therefore, when an instruction to load a value into this control register is executed in the E stage 55, the instruction taken into the subsequent pipeline will have the control value before the instruction to load a value into this control register is executed. There is no guarantee that the process is correct.

Therefore, after loading a value into the control register in the E stage 55, processing is performed to cancel the subsequent instructions being processed in the pipeline.

(Problems to be Solved by the Invention) In a data processing device that performs conventional pipeline processing, when processing an instruction that jumps to a subroutine as described above, the following (1) is performed.

There was a particular problem that required one of (2) to be provided.

(1) If the return address from the subroutine is calculated by the program counter calculation unit (PC calculation unit),
A latch is provided to hold this return address until it is processed in the instruction execution stage 55.

(2) If the starting address of the instruction to jump to the subroutine and the instruction length of this instruction are held until this instruction is executed, and the return destination address is calculated in the instruction execution stage 55, this instruction is transferred to the instruction execution stage 55. The return destination address and instruction length are held until the return address is reached, and the instruction execution stage 55
Provide a latch that can be operated with.

This invention was made to solve the above problems, and when processing a specific instruction, the instruction is decoded into multiple pipeline processing units and sequentially transferred to the subsequent processing stage. It is an object of the present invention to provide a data processing device that can efficiently transfer an address necessary for processing a specific instruction into a pipeline in parallel with instruction fetch.

(Means for Solving the Problems) A data processing device according to the present invention includes a decomposition decoding means for decomposing and decoding one instruction into one or more unit processing codes for a second pipeline stage;
address calculation means for executing a plurality of address operations for the instruction based on each unit processing code decoded by the decomposition decoding means; A transfer means for transferring the data to the pipeline stage is provided.

[Effect]

In this invention, when an instruction fetch is executed and one instruction is output to the first pipeline stage,
The decomposition decoding means decomposes and decodes one instruction into one or more unit processing codes for the second pipeline stage, and the address calculation means decomposes each unit processing code into one or more unit processing codes. Perform multiple address operations on the instruction based on the . Then, the transfer means sequentially transfers the calculated instruction address to the subsequent second pipeline stage as a unit processing code.

〔Example〕

FIG. 1 is a block diagram illustrating the configuration of a data processing device showing an embodiment of the present invention. Reference numeral 1 denotes an instruction fetch unit, which is composed of a branch buffer, an instruction queue, a control unit, etc. The address of the instruction is determined and the instruction is fetched from the branch buffer or memory outside the CPU. It also registers instructions in the branch buffer.

Since the branch buffer is small, it acts as a selective cache. The details of the operation of the franchise buffer are described in detail in Japanese Patent Application No. 61-202041.

Next, the address of the instruction to be fetched is calculated by a dedicated counter as the address of the instruction to be input into the instruction queue. When a branch or jump occurs, the address of a new instruction is transferred from the PC calculation unit 3 and data calculation unit 6, which will be described later.

When fetching an instruction from a memory external to the CPU, the address of the instruction to be fetched is output from the address output circuit 8 to the outside of the CPU through the external bus interface section 7, and the instruction code is fetched from the data input/output circuit 9. . Among the buffered instruction codes, the instruction decoding section 2 outputs the instruction code to be decoded next to the instruction decoding section 2.

The instruction decoding section 2 basically decodes instruction codes in 16-bit (halfword) units. This block includes an FHW decoder that decodes the opcode included in the first halfword, an NFHW decoder that decodes the opcode included in the second and third halfwords, and an addressing mode decoder that decodes the addressing mode.

Additionally, there is a decoder that further decodes the output of the FHW decoder and NFHW decoder to calculate the micro ROM entry address, a branch prediction mechanism that predicts branches of conditional branch instructions, and an address that checks pipeline conflicts when calculating operand addresses. A calculation conflict check mechanism is also provided.

Note that the instruction decoding section 2 decodes the instruction code inputted from the instruction fetch section 1 by 0 to 6 bytes every two clocks. Among the decoding results, information related to the calculation in the data calculation section 6 is sent to the micro ROM section 5, information related to operand address calculation is sent to the Averand address calculation section 4, and information related to program counter calculation is sent to the PC calculation section 3. Each is output.

The PC calculation section 3 is a PC output from the instruction decoding section 2.
It is hardwired and controlled by information related to calculation, and calculates the PC value on the eye side. The data processing device in this embodiment has a variable length instruction set, which will be described later, and the length of the instruction cannot be known until the instruction is decoded. Therefore, the PC calculation unit 3 creates the PC value of the next instruction by adding the instruction length output from the instruction decoding unit 2 to the PC value of the instruction being decoded.

Furthermore, when the instruction decoding unit 2 decodes a branch instruction and instructs a branch at the decoding stage, by adding the branch displacement to the PC value of the branch instruction instead of the instruction length,
Calculate the PC value of the branch destination instruction. Branching to a branch instruction at the instruction decoding stage is called a branch.

It should be noted that detailed description is given in Prebranch Ji No. 1204500, Japanese Patent Application No. 61-200557, etc., so the explanation will be omitted.

The calculation result of the PC calculation unit 3 is output as the pc value of each instruction together with the decoding result of the instruction, and at the time of pre-branch, it is output to the instruction fetch unit 1 as the address of the next instruction to be decoded.

It is also used as an address for branch prediction of the next instruction to be decoded by the instruction decoding unit 2. The above branch prediction processing is explained in detail in Japanese Patent Application No. 8394/1983.

The operand address calculation unit 4 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction code unit 2 and the like.

This block performs most of the processing related to operand address calculation. The address calculation result is sent to the external bus interface 7. Values of general-purpose registers and programs necessary for address calculation are input from the data calculation unit 6. Note that when performing memory indirect addressing,
Outputs the memory address to be referenced from the address output circuit 8 to the outside of the CPU through the external bus interface section 7, and fetches the indirect address value input from the data input/output section circuit 9 through the instruction decoding section 2/to the micro ROM section 5. is a micro ROM in which a micro program that mainly controls the data calculation section 6 is stored.
, a micro sequencer, a micro instruction decoder, etc. are provided, and micro instructions are read out from the micro ROM once every two clocks. The micro ROM unit 5 also manages store buffers. The micro ROM unit 5 receives interrupts that do not depend on instruction codes, flag information based on the results of arithmetic operations, and outputs of the instruction decoding unit 2 such as decoder outputs. The output of the micro-decoder is mainly output to the data calculation unit 6, but part of the information on other preceding processing stop information rings due to the execution of the jump instruction is also output to other blocks.

The data calculation section 6 is controlled by a microprogram,
According to the output information of the micro ROM unit 5, the registers and the arithmetic unit execute the operations necessary to realize the function of each instruction. The address calculated by the operand address calculation unit 4 may be obtained through the external bus interface unit 7, or the operand fetched at that address may be obtained from the data input/output circuit 9.

Examples of arithmetic units include an ALU, a barrel shifter, a priority encoder, a counter, and a shift register. The registers and the main arithmetic unit are connected by 3 buses, 1
One microinstruction that instructs an operation between two registers is processed in two clock cycles.

During data calculation, when it is necessary to access memory external to the CPU, the address is output from the address output circuit 8 to the outside of the CPU through the external bus interface section 7 according to instructions from the microprogram, and the address is output to the outside of the CPU by the data input/output circuit 1.
When storing data in a memory outside the CPU, the address is output from the address output circuit 8 through the external bus interface section 7, and at the same time, the data is output from the data input/output circuit 9 to the outside of the CPU. do. In order to efficiently store operands, the data calculation unit 6 includes a 4-byte store buffer. Note that when the data calculation unit 6 obtains a new instruction address by processing a jump instruction, exception handling, etc., it outputs this to the instruction fetch unit 1 and the PC calculation unit 3.

The external bus interface unit 7 controls communication on the external bus, and in particular, all memory accesses are performed in clock synchronization and can be performed in a minimum of two clock cycles.

Access requests to the memory are made by the instruction fetch section 1, operand address calculation section 4. These memory access requests are generated independently from the data calculation unit 6, and the external bus interface unit 7 arbitrates these memory access requests.

Furthermore, when accessing data at a memory address that straddles a 32-bit (word) aligned boundary, which is the data bus size that connects memory and the CPU, the block automatically detects that it straddles a word boundary, and This is done by breaking it down into multiple memory accesses.

It also performs conflict prevention processing and bypass processing from the store operand to the fetch operand when the operand to be fetched and the operand to be stored overlap.

Note that when an instruction is fetched by the instruction fetch unit 1, one instruction is transferred to the D stage 12 (described later) as shown in FIG. 2(a).
When the instruction is output to the first pipeline stage (first pipeline stage), the instruction decoding unit 2 serving as decomposition decoding means outputs one instruction to the second pipeline stage.
Each unit process decomposed into one or more unit processing codes for the A stage 13, which is a pipeline stage of Perform multiple address operations on instructions based on code. Then, the operand address calculation unit 4, which also serves as a transfer means, uses the calculated address information, such as the jump destination address of a subroutine jump instruction, the return destination address, or the start address of the next instruction by multiple load instructions, as a unit processing code for subsequent steps. The data is sequentially transferred to the second pipeline stage via the internal bus (details will be described later).

FIG. 2(a) is a configuration block diagram illustrating the pipeline processing of the data processing device shown in FIG. output to the subsequent stage. 12 is a decode stage (D stage) which decodes the instruction code 21, executes operand address calculation, and generates a D code 22.1 which is an intermediate decode result of the operation code. A code 23 serving as address calculation information is output to the subsequent stage. Reference numeral 13 denotes an operand address calculation stage (A stage) which outputs an R code 24 consisting of register and memory write reservations, microprogram entry addresses, parameters for the microprogram, etc., and an F code 25 which is the result of address calculation.

14 is the operand fetch stage (F stage),
It consists of an R stage 16° that performs micro ROM access, and an OF stage 17 that performs a pre-fetch of the operand. For example, a five-stage pipeline process is executed, in which each stage is output to the execution stage (E stage) 15. In addition, in E stage 15, there is a one-stage store buffer, and some of the high-performance instructions pipeline the instruction execution itself, so there are actually five stages.
Processing equivalent to pipeline processing with stages or higher can be performed.

Also, each stage operates independently of the other stages,
In theory, the five stages operate completely independently. Each stage can execute one process in a minimum of two clocks. Furthermore, in the data processing device in this embodiment, there are instructions such as inter-memory operations and memory indirect addressing that cannot be processed by just one basic pipeline process, but these processes are also balanced as much as possible. Designed for pipeline processing. For instructions with multiple memory operands, the instructions are decomposed into multiple pipeline processing units (step codes) based on the number of memory operands, and pipeline processing is performed. In particular, the method of decomposing the pipeline processing units is described in detail in Japanese Patent Application No. 1983-236456, and will not be described here.

Next, the pipeline processing unit in this invention will be explained with reference to FIG. 2(b).

FIG. 2(b) is a schematic diagram explaining the basic instruction format, and each instruction in this embodiment includes, for example, a 2-byte instruction basic part and an O to 4-byte addressing extension part, which are repeated 1 to 3 times. Consisted of.

The pipeline processing unit is determined using the format characteristics of the instruction set, and the instructions in this example are:
It is a 2-byte variable length instruction, and as shown in Figure 2(b), one instruction is basically completed by repeating the 2-byte basic instruction part + 0 to 4-byte addressing extension part 1 to 3 times. The instruction base often has an opcode section, an addressing mode specification section, and ends with a 2 or 4-byte instruction-specific extension section, depending on the instruction.

The instruction basic part includes an instruction opcode, basic addressing mode, literal, etc., and the addressing extension part is any one of a displacement, an absolute address, and a displacement of an immediate 1 branch instruction.

Additionally, instruction-specific extensions include register maps.

I-f　rryxa　 is specified as an immediate value of an instruction.

Next, the operation of each stage in FIG. 2(a) will be explained.

In the D stage 12, a 2-byte instruction basic part 0 to a 4-byte addressing extension part or instruction-specific extension part are processed as one decoding unit. The decoding result of each time is called a step code, and from the A stage 13 onwards, this step code is used as a unit of pipeline processing. Note that the number of step codes is unique for each instruction, and one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes. There is a possibility that all the step codes existing on the pipeline are for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction on which it is based. The program counter value that is attached to the step code and flows through each stage of the pipeline is called a step program counter (spc), and the step program counter is passed from one pipeline stage to another.

The input/output step code of each pipeline stage is given a code name as shown in FIG. It is divided into two series: a series that becomes parameters, etc. for the E stage 15, and a series that becomes operands for the microinstruction of the E stage 15.

The IF stage 11 fetches an instruction from an external memory or a branch buffer, inputs it into an instruction queue, and outputs an instruction code 21 to the D stage 12. Input to the instruction queue is performed in aligned 4-byte units. Fetching an instruction from memory requires a minimum of two clocks per four aligned bytes. When the branch buffer is hit, each aligned 4 byte can be fetched in one clock. The output unit of the instruction queue is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks.

Further, immediately after a branch, the instruction queue can be bypassed and the two bytes of the instruction basic part can be directly transferred to the instruction decoder.

The IF stage 11 also controls the registration and clearing of instructions in the branch buffer, manages the pre-fetch destination instruction address, and controls the instruction queue.9 The address of the next instruction to be fetched is the address of the instruction to be input into the instruction queue. is calculated using a dedicated counter. When a branch or jump occurs, the address of the new instruction is calculated by the PC calculation unit 3. shown in FIG. The data is transferred from the data calculation unit 6 via the internal bus.

When the instruction code 21 is input to the D stage 12, the D stage 12 uses the FH decoder, NFHW decoder, addressing mode decoder, etc. of the instruction decoding section 2 shown in FIG. decode once.

One decoding process consumes 0 to 6 bytes of instruction code, and one decoding process consumes the A code 23 (approximately 35 bits of control code and up to 32 bits of address modification) which becomes address calculation information for the A stage 13. information), a D code 22 which is an intermediate decoding result of the operation code, a control code of approximately 50 bits, and literal information of 8 bits are output to the A stage 13.

In addition, in the D stage 12, control 1 branch prediction processing of the PC calculation unit 3 for each instruction, bribranch processing for a bribranch instruction, and instruction code output control from the instruction queue are also performed.

When the A code 23 (approximately 35-bit control code, maximum 32-bit address modification information) and the D code 22, which is the intermediate decoding result of the operation code, are input to the A stage 13, the A stage 13 can be roughly divided into two types. Perform processing.

One is a process in which the decoder of the instruction decoding unit 2 is used to perform subsequent decoding of the operation code, and the other is a process in which the operand address calculation unit 4 calculates an operand address.

The subsequent decoding process of the operation code takes the D code 22 as input, and outputs the R code 24 which includes register and memory write reservations, the entry address of the microprogram, parameters for the microprogram, and the like. In addition,
Write reservation for registers and memories is to prevent the contents of registers and memories referenced in address calculations from being rewritten by instructions that precede them on the pipeline, resulting in incorrect address calculations. To avoid deadlock, write reservations for registers and memory are made for each instruction, not for each step code.

Note that writing reservations for registers and memories are described in detail in Japanese Patent Application No. 144394/1983.

On the other hand, regarding operand address calculation processing, the A code 23 is input, and the operand address calculation unit 4 performs address calculation by combining addition and memory indirect reference according to the A code 23, and outputs the calculation result as an F code 25. At this time, a conflict check is performed when reading the register or memory associated with address calculation, and if a conflict is indicated because the preceding instruction has not finished writing to the register or memory, the preceding instruction executes the write processing at E stage 15. Wait until it finishes. It also checks whether the operand address or memory indirect reference address falls within the I10 area mapped to memory.

In addition, in the A stage 13, the A stage stack pointer (ASP) that precedes the stack pointer (sp) in the E stage 15 is set to prevent stack pointer (sp) conflicts due to pop operations from the stack, push operations to the stack, etc. The A stage stack pointer (ASP) is updated at this stage in conjunction with pop and push operations. Therefore, the A stage stack pointer (ASP
) is updated at this stage.

Therefore, by referring to the A stage stack pointer (ASP) even immediately after a normal hop or push operation,
Processing can proceed without delaying step code processing due to stack pointer (sp) conflicts. The method of managing the stack pointer (sp) is described in detail in Japanese Patent Application No. 145852/1982.

The F stage 14, which is the subsequent stage of the A stage 13, also has code processing divided into two parts as described above, and is composed of an R stage 16 that performs micro ROM access processing and an OF stage 17 that performs operand prefetch processing. ing.

Note that the R stage 16 and the OF stage 17 do not necessarily operate simultaneously, but operate independently depending on whether memory access rights can be acquired or not.

Micro ROM access processing, which is the processing of R stage 16, includes micro ROM access and micro instruction decoding processing for creating E code 26, which is an execution control code used for execution in the next E stage 15, for R code 24. It is.

When processing for one R code is broken down into two or more microprograms, the micro ROM is used in the E stage 15, and the next R code 24 waits for access to the micro ROM. Micro RO for R code 24
The M access is performed at the time of execution of the last microinstruction in the previous E stage 15. In the data processing device of this embodiment, since most basic instructions are executed in one microprogram step, in reality, accesses to the micro ROM 7 to the R code 24 are often executed one after another.

On the other hand, in the OF stage 17, the 2
Among these processes, perform operand prefetch processing.

The operand briefetch takes the F code 25 as input and outputs the fetched operand and its address as the S code 27. One F code 25 specifies operand fetch of 4 bytes or less, although it may cross word boundaries. The F code 25 also includes a designation as to whether or not to access the operand, and the operand address itself and the immediate value calculated in the A stage 13 are sent to the E stage 15.
When transferring to , the contents of the F code 25 are transferred as the S code 27 without performing operand fetch. Also,
Operand to be prefetched and E stage 15
When the operand that the E stage 15 attempts to write satisfies the inclusion relationship, no memory access is performed for operand prefetch, and the value that the E stage 15 attempts to write is bypassed.

Further, operand prefetch is delayed for the I10 area, and operand fetch is performed after waiting until all preceding instructions are completed.

E code 26 from F stage 14. When the S code 27 is input to the E stage 15, data processing using various arithmetic units, data reading, data writing, etc. are executed.

ALU is a computing unit.

Barrel shifter, priority encoder, counter,
There are shift registers, etc. This E stage 15 is a stage for executing instructions, and all processes performed in stages before the F stage 14 are preprocessing for the E stage 15. When a jump instruction is executed at E stage 15, all processing from IF stage 11 to F stage 14 is invalidated, and the jump destination address is set to instruction fetch section 1.
is output to the PC calculation section 3. The E stage 15 is controlled by a microprogram and executes instructions by executing a series of microprograms starting from the microprogram entry address indicated in the R code 24.

Reading of the micro ROM and execution of micro instructions are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available.

Further, the E stage 15 can perform pipeline processing of operand storage within 4 bytes and execution of the next microinstruction by using the store buffer in the data calculation unit 6.

In the E stage 15, the write reservation for registers and memory made in the A stage 13 is canceled after the operand is written.

Each stage of the pipeline has a manual latch and an output latch, and basically operates independently from other stages. Each stage finishes the previous processing and transfers the processing result from the output latch to the input latch of the next stage, and when the input latch of its own stage has all the input signals necessary for the next processing, the next stage is started. The mechanism is such that each stage receives all input signals for the next process from the previous stage, and transfers the current processing result to the input latch of the next stage. When the output latch is empty, the next process begins.

It is necessary that all human input signals are available at the clock timing one before each stage operates.

If Shinshu Jinriki is not available, the stage will be in a waiting state (
Waiting for human power). When performing a transfer from the output latch to the next stage's manual latch, the next stage's manual latch must be free, and even if the next stage's input latch is not free, the pipeline stage It enters a waiting state (waiting for output). If the necessary memory access rights cannot be obtained, if a wait is inserted into the memory access being processed, or if other pipeline conflicts occur, the processing itself at each stage will be delayed.

Next, the processing functions shown in FIG. 1 will be explained in detail with reference to FIG.

FIG. 3 is a detailed block diagram of the data processing device shown in FIG.
SR instruction) and load value to control register instruction (L
Data processing based on DC command) will be explained along with its configuration.

Input terminal of instruction decoding section 2 and PC adder 3b.

The input end of the address adder 4d is connected by a DISP bus 30 that transfers the displacement value of the displacement value 9 branch instruction. The input side of the instruction decoding unit 2 and address adder 4d is the instruction code length used for step code generation;
They are connected by a correction value bus 32 that transfers the bridement value and the like in the stacked bush mode. In addition, the input terminals of the instruction decoding section 2 and the PC adder 3b are connected to an instruction length bus 3 that transfers the instruction code length used to generate the step code.
They are connected by 1. The register file 6d and the input side of the address adder 4d are connected by an A bus 33 that transfers address values stored in the register file 6d.

The output of the augend selection circuit 3a which manually selects either the value of the instruction length bus 31 or the value of the DISP bus 30, and D
D that holds the PC value of the instruction decoded in stage 12
Either the PC latch 3d or the TPO latch 3d that holds the working PC value each time the step code breaks is P.
It is manually input to the C adder 3b. The output of the pc adder 3b is
CA bus 6 and Po through PC adder output latch 3c.
It is output to bus 37. The Po bus 37 is coupled to a Tpc latch 3d, a DPC latch 3e, and an APC latch 3f that holds the PC value of the instruction being processed in the A stage 13. In order to input a new instruction address to the TPC latch 3d when a branch or jump occurs in the E stage 15,
There is also a manual route from the CA bus 6. The values of the correction value bus 32 and the DISP bus 30 are manually input to the displacement selection circuit 4b, and either one is input to the address adder 4d. DISP bus 30
and the value of the A bus 33 are input to the base address selection circuit 4c, and either one is input to the address adder 4d. The address adder 4d shifts the output of the displacement selection circuit 4b, the output of the base address selection circuit 4C, and the values inputted from the A bus 33 to obtain values of 1, 2, 4, and 8 times. Three-value addition is performed by inputting a total of three values output from the index value generation circuit 4a. The output value of the address adder 4d is output to the AO bus 4 through the address adder output latch 4e. The AO bus 4 is connected to an FA latch 7a that holds an operand address value that is output from the address output circuit 8 to the outside of the CPU through the AA bus 5 when an operand is fetched in the F stage 14.

FA latch 7a has an output path to SA latch 7b which holds the operand address calculated by address adder 4d for use in E stage 15. The SA latch 7b has an output path to the S1 bus 38, which is a general-purpose data bus of the data calculation section 6. The CA bus 6 that transfers the address of an instruction includes an address adder output latch 4e, a TPC latch 3d, and an instruction fetch unit 1.
QIN that manages the address of the instruction code that is briefly fetched by
Connects the CAA latch 7c that holds the value when outputting it from the PC counter 1b to the outside of the CPU, and the EB clutch C that manually inputs a new instruction address from the 32 bus 39 when a branch or jump occurs in the E stage 15. are doing. A
The PC latch 3e has an output path to the A bus 33 and the latch FPC 3f that holds the PC value being processed in the F stage 14. The FPC latch 3g has an output path to the CPC latch 3h which holds the PC value of the instruction being processed in the E stage 15. Further, the CPC latch 3h has an input/output path with the S1 bus 38. The register file 6d consists of general-purpose registers, working registers, etc., and is connected to the S1 bus 38.
It has an output path to the S2 bus 39 and the A path 33, and
○Has an input route from Babasu 0. The data calculation unit 6e, which is the calculation mechanism of the data calculation unit 6, is connected to the S1 bus 38. S2
It has a human route from bus 39 and an output route to DO bus 0.

PS where status information of data processing equipment is stored
The control register group 6b consists of the W register, the register storing the base address of the context block, the register storing the operation mode information of the debuff support mechanism, the register storing the mode information of the branch buffer, etc. It has an input path and an output path to the S2 bus 39. The AA register 7d, which stores data fetch and store addresses used by the E stage 15, has an input path from the S1 bus 38 and an output path to the AA bus 5. The DD register 6f, which stores fetch data and store data processed by the E stage 15, has a manual route from the DO bus 0 and is connected to the S1 bus 38. It has an output path to the S2 bus 39 and
It has an input/output route to the D bus 1. F at stage 14
The SD clutch g, which holds the operand data fetched from the external memory according to the operand address stored in the A latch 7a, is connected to the input path from the DD bus 1 and the S1 bus 38. It has an output path to the S2 bus 39. 4f
is a stack pointer (Asp), managed by the A stage 13, and D.

Stack pointer (FSP) 4g that has an input path from bus 40 and is managed by A bus 33 and F stage 14
has an output route to.

The stack pointer (FSP) 4g has an input path from the stack pointer (ASP) 4f, and the E stage 15
It has an output path to the stack pointer (CSP) 6a managed by CSP. The stack pointer (CSP) 6a has input paths from the Do bus 0 and the stack pointer (FSP) 4g, and the S1 bus 38. It has an output path to the S2 bus 39.

Next, in order to explain pipeline processing based on a subroutine jump instruction (JSR instruction) and an instruction to load a value into a control register (LDC instruction), we will specifically explain the pc calculation unit 3.
The detailed operation will be explained below.

When the instruction code is decoded in the D stage 12, the PC calculation unit 3 determines the instruction being decoded based on the length information of the instruction code decoded immediately before and the starting address of the instruction code decoded immediately before. Calculate the starting address of the code. In the PC calculation unit 3, the DPC latch 3e holds the PC value of the instruction, which is the address of the instruction break, and the TPO latch 3
d holds the address of the break in the step code.

At this time, the DPC latch 3e is updated only when the instruction break address is calculated, and the TPO latch 3d
is updated every time the step code break address is calculated. The PC value of the step code processed on the pipeline requires the PC value of the instruction that is the source of the step code, so the value of the DPC latch 3e is
The data is transferred to C latch 3f, FPC latch 3g, and CPC latch h.

Note that instruction code processing is performed in step code units as described above, and one decoding process consumes instructions of 0 to 6 bytes. Then, the length of the instruction code used at that time, which is determined for each instruction decoding process, is output from the instruction decoding section 2 to the instruction length bus 31.

Next, the subroutine jump instruction (J
Pipeline processing using the SR command will be explained with reference to the flowchart shown in FIG.

Note that a subroutine jump instruction (hereinafter referred to as JSR instruction) is decomposed into two step codes and processed in the D stage 12.

FIG. 4(a) is a schematic diagram showing the format of a subroutine jump instruction (JSR instruction). In this figure, 45a indicates the instruction basic part, and 45b indicates the new land specification part (newpc), which specifies the operand. This corresponds to the case of an instruction that jumps to a subroutine to the execution address of section 45b.

Reference numeral 45c is an extension section in which absolute addresses, displacements, etc. are defined for address calculation of the jump destination address.

FIG. 5 is a flowchart illustrating the subroutine jump instruction processing procedure according to the present invention.

Note that (1) to (16) indicate each step, the vertical line in the figure indicates each stage processing area, and the horizontal line indicates each step code processing order.

First, the first step code processing will be explained.

First, a JSR instruction is taken in at the IF stage 11 (1).

Next, the JSR instruction is decoded at the D stage 12,
A D code 22 indicating the first step code of the JSR instruction and an A code 23 for calculating the execution address of the jump destination address are generated (2). If an extension section 45c such as absolute address displacement is required to calculate the address of the jump destination, that data is also fetched from the instruction queue 1a at the same time. The instruction length taken into the instruction decoder 2 from the instruction queue 1a is also output to the augend selection circuit 3a. Therefore, in synchronization with the step in which the D stage 12 starts processing the JSR instruction, the PC calculation unit 3
Selection of an addend value that holds the value of the TPC latch 3d that holds the address value for the instruction immediately before the R instruction and the instruction length output from the D stage 12 in the final step of the instruction immediately before the JSR instruction. The value of the circuit 3a is added by the PC adder 3b, and the start address of the JSR instruction, which is the addition result, is written to the TPC latch 3d and DPC latch 3e (3)
.

Next, in the A stage 13, the operand address calculation unit 4 calculates the address of the jump destination according to the instructions of the A code 23, and the calculated address of the jump destination is transferred to D.
Transfer to FA register 7a via O bus 4 (4)
.

Next, in the F stage 14, the value of the FA register 7a is transferred to the SA register 7b (5). Next, in the E stage 15, the value of the SA register 7a in which the jump destination address is stored is transferred to the EB register 6C via the 51 bus 38.
(6) Next, processing related to the second step code will be explained.

In the D stage 12, an A code 23 is generated to indicate the second step code of the JSR instruction or to instruct processing related to the code 22 and the execution address of the return destination (7). Regarding the processing of this step code, instruction queue 1
No command data is fetched from a.

Next, in synchronization with the processing of step (2) of the JSR instruction processing in the D stage 12, the PCC calculation unit extracts the value of the TPC latch 3d in which the start address of the JSR instruction is stored and the output of the augend selection circuit 3a. The instruction length, which is the value, is added by the pc adder 3b and written to the TPO latch 3d (
8).

In the A stage 13, the instruction length consumed for processing the first step code of the JSR instruction is added to the PCC calculation unit, and the instruction length is added to the TP where the next instruction address of the JSR instruction is stored.
The value of the C latch 3d is input to the base address selection circuit 4c via the DISP bus 30, and output to the address adder 4d.

Furthermore, the outputs of the index value generation circuit 4a and displacement selection circuit 4b are cleared. The outputs of the index value generation circuit 4a, displacement selection circuit 4b, and base address selection circuit 4C are sent to the address adder 4.
The three values are added at step d, and the output of the address adder 4d, that is, the return destination address, is transferred to the FA register 7a via the AO bus 4 (9).

Furthermore, in the A stage 13, the value of the APC latch 3f is decremented and transferred to the FSP latch 4g (1
0).

In the F stage 14, the value of the FA register 7a is transferred to the SA register 7b (11), and the value of the FSP latch 4g is transferred to the CSP latch 6a (12).

In the E stage 15, the value of the C3P latch 6a in which the stack address is stored is transferred to the AA via the 51 bus 38.
The value of the SA register 7b in which the return destination address is stored is transferred to the register 7d (81 bus 38.13). Data calculation unit 6e, DD register 6f via Do bus 0
(14).

Next, after storing the contents of the DD register 6f at the address indicated by the AA register 7d (15), the EB register 6
A signal instructing a jump to the address indicated by C is output to all stages (16).

Next, pipeline processing based on loading a value into a control register (LDC instruction) will be described with reference to FIGS. 4(b) and 4(c) and FIG. 6.

FIGS. 4(b) and 4(c) are schematic diagrams illustrating the bit allocation of the LDC instruction in the present invention.

4B shows a general format (G format), 46a and 46e indicate basic instruction parts, and 46b is a specification field (RR) for specifying the source operand size. 46c is an operand specification field, and the value sr
c is set.

46d indicates an extension. 46f is a designation field in which a destination address (WW) is set.

46g is an operand specification field in which a value dest specifying a control register is set.

Figure (C) shows the E format, which corresponds to the case where the first operand is an 8-bit immediate value, 47a and 47c show the instruction basic part, 47b shows the immediate value specification field, 47d is the specification field, Destination address (WW) is set. 47e indicates an extension part.

FIG. 6 is a flowchart illustrating a load instruction processing procedure for loading a value into a control register according to the present invention.

Note that (1) to (17) indicate each step, the vertical lines in the figure indicate each stage processing area, and the horizontal lines indicate each step code processing order. Further, the LDC instruction format will be explained using the LDC instruction in the G format shown in FIG. 4(b) as an example.

First, the first step code processing will be explained.

First, an LDC instruction is taken in at the IF stage 11 (1).

Next, in the D stage 12, the LDC instruction generates a D code 22 indicating the first step code and an A code 23 for calculating the address of the value srC (2). If the extension section 46d shown in FIG. 4(b) is required to calculate the address of the value src, the data is also stored in the instruction queue 1.
A (see FIG. 3) are simultaneously taken into the instruction decoding section 2.

Here, since the G format is adopted, the value src is processed as an immediate value, so there is no need for address calculation.

The augend selection circuit 3a receives instruction queue 1 at that step.
The instruction length taken into the instruction decoding section 2 is output from a. In the PC calculation unit 3, one of the LDC instructions is processed in synchronization with the step in which the D stage 12 starts processing the LDC instruction.
The value of the TPC latch 3d that holds the address value related to the previous instruction and the value of the augend selection circuit 3a that holds the instruction length output from the D stage 12 at the final step of the instruction immediately before the LDC instruction. are added by the PC adder 3b, and the start address of the LDC instruction, which is the addition result, is written to the TPC latch 3d and DPC latch 3e (3) In the A stage 13, the value that becomes the immediate value according to the instruction of the A code 23 is written src is transferred within the operand address calculation unit 4 and sent to the FA via the AO bus 4.
It is transferred to register 7a (4).

In the F stage 14, the value of the FA register 7a is transferred to the SA register 7b (5). In the E stage 15, the value of the SA register 7b indicating SrC is transferred to the 31 bus 38. The data is transferred to the working register existing in the register file 6d via the data calculator 6e and the DO bus 0 (6).

In the processing related to the second step code, first, in the D stage 12, the second instruction basic part of the LDC instruction is fetched from the instruction queue 1a to the instruction decoding unit 2, and when decoded by the instruction decoding unit 2, the LDC instruction A D code 22 indicating the second step code and an A code 23 for calculating the address of the control register are generated (7) If the extension section 47f is required to calculate the address of the control register, its data is also stored in the instruction queue 1a. Import from simultaneously.

The addend selection circuit 3a receives the instruction queue 1a at that step.
The instruction length taken into the instruction decoding section 2 is output from the instruction decoder 2. In the PC calculation unit 3, the value of the TPO latch 3d that holds the start address of the LDC instruction and the output value of the augend selection circuit 3a that holds the instruction length transferred from the instruction decoding unit 2 in step (1) are calculated as PC. Added by adder 3b, T
Written to the PC latch 3d (8) In the A stage 13, the address of the specified control register is calculated in the operand address calculation unit 4 according to the instruction of the A code 23, and the calculated address of the control register is sent to the AO bus 4 to the FA register 7a (9).

In the F stage 14, the value of the FA register 7a is transferred to the SA register 7b (10).

In the E stage 15, the contents of the working register storing the value to be loaded in the first step code are transferred to and stored in the control register indicated by the address in the SA register 7b (11).

Furthermore, the processing regarding the third step code is first performed by D
In stage 12, no instruction data is fetched from the instruction queue 1a regarding the processing of the third step code of the LDC instruction. At this time, the third step code, D code 22. The A code 23 is generated (12), and the PCC calculation unit calculates the value of the TPO latch 3d and the value of the augend selection circuit 3a in the PC adder 3b in synchronization with the processing of step (3) of the D stage 12. The first address of the next instruction is written to the TPO latch 3d (13).

At A stage 13, the LD
TPC latch 3 where the next instruction address of the C instruction is stored
The value of d is input to the base address selection circuit 4C via the DISP bus 30, and output to the address adder 4d. Furthermore, the outputs of the index value generation circuit 4a and displacement selection circuit 4b are cleared. Index value generation circuit 4a and displacement selection circuit 4b
and the output of the base address selection circuit 4c are added in three values (addition of "0") by the address adder 4d.
The output of d, that is, the next instruction address of the LDC instruction is A
Transferred to the FA register 7a via the O bus 4 (1
4).

In the F stage 14, the value of the FA register 7a is transferred to the SA register 7b (15).

In the E stage 15, the value of the SA register 7b, which stores the address of the next instruction after the LDC instruction, is transferred to the S1 bus 3B.
After transferring to the EB register 6c via (16), the EB
Instruct 1 to jump to the address indicated by register 6c.
7) Finish the pipeline process for loading the value into the control register.

Next, the instruction format in this invention will be explained with reference to FIGS. 7 to 17.

Note that the data processing device in this embodiment basically has a configuration of 4 bytes + extension part for 2 oherand instructions, and has a general format that can use all addressing modes, as well as frequently used instructions and addressing. Two formats of abbreviated formats are defined in which only modes can be used.

Figures 7 to 16 are schematic diagrams explaining the bit assignments of the instruction formats used. - in each figure indicates an opcode area, # indicates an area for literal or immediate value assignments, and Ea indicates an 8-bit bit. sh indicates an area for specifying an operand in the general addressing mode, sh indicates an area for specifying an operand in a 6-bit abbreviated addressing mode, and Rn indicates an area for specifying an operand on a register by a register number.

Note that the format is LSB on the right side as shown in Figure 7.
on the side, and has a high address.

The instruction format cannot be determined without looking at the two bytes of address N and address N+1, but this is because it is assumed that instructions are always fetched and decoded in units of 16 bits (2 bytes). be.

In addition, in any format, the extended part of area Ea or area sh of each operand must be area E.
It is placed immediately after the halfword containing a or the basic part of area sh. This overrides any immediate data or extensions of the instruction that are implicitly specified by the instruction. Therefore, for an instruction of 4 bytes or more, the operation code of the instruction may be divided by the extension part of area Ea.

Next, the format of the abbreviated two-operand instruction will be explained with reference to FIGS. 8 to 11.

Figure 8 shows the format of an operation instruction between memory registers, and the L-forma where the source operand side is memory.
There is an S-format in which the t and destination operand sides are memories.

In particular, in L-format, sh indicates the specified field of the source operand, and Rn indicates the specified field s.
Indicates the specification of the operand size of h, and the size of the destination operand placed on the register is 32
Fixed to bit. Sign extension is performed when the size of the register side and the memory side are different and the size of the source side is small.

In the S-format, sh indicates a destination operand specification field, and Rn indicates the operand size specification of the specification field sh. If the size of the register side and the memory side are different, and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

Figure 9 shows the format (R-format) of a register-register operation instruction, where Rn indicates the destination register specification field, Ftm indicates the source register specification field, and the operand size is only 32 bits. be.

FIG. 10 shows the format (Q-format) of a literal-memory operation instruction, where MM indicates a destination operand size specification field,
sh indicates the designated field of the destination operand.

Figure 11 shows the format of an immediate-memory operation instruction (I
-format), and MM is the operand size specification field (common for source and destination)
, sh indicates the specified field of the destination operand, the size of the immediate value of I-format is 8.16.32 bits, which is the same as the size of the destination operand, and zero extension and sign extension are Not done.

Figure 12 shows the general format of a one-operand instruction (G
MM indicates the operand size specification field. In addition, Gl-for
In the mat instruction, there is an extension part outside the area Ea. There are also instructions that do not use the designated field MM.

Figures 13 to 16 show the general format of a two-operand instruction, which has a maximum of two operands in the general addressing mode specified by 8 bits.
The total number of operands itself may be three or more.

FIG. 13 shows an instruction format (G-format) in which the first operand requires memory read, and EaM
indicates a destination operand specification field, MM indicates a destination operand size specification field, EaR indicates a source operand specification field, and RR indicates a source operand size specification field.

Figure 14 shows the format of an instruction whose first operand is an 8-bit immediate value (E-format), EaM indicates the destination operand specification field, and M
M indicates a destination operand size specification field, and # indicates a source operand value.

Figure 15 shows an instruction format (GA-format) in which the first operand is only address calculation, EaW indicates the destination operand specification field, WW indicates the destination operand specification field, and EaA indicates the source operand specification field. field, and the execution address calculation result itself is used as the source operand.

FIG. 16 shows the format of a short branch instruction, CCCC indicates a branch condition specification field, and di
sp:8 indicates a displacement specification field with respect to the jump destination,
In this embodiment, when specifying displacement using 8 bits, the specified value in the bit pattern is doubled to obtain the displacement value.

Next, the addressing mode in this embodiment will be explained with reference to FIGS. 17 to 24.

In this embodiment, there are two methods for specifying the addressing mode of the data processing device: an abbreviated form in which the addressing mode is specified using 6 bits including the register, and a general form in which the addressing mode is specified using 8 bits. or if a combination of addressing modes that is semantically incorrect is specified, a reserved instruction exception is generated and exception handling is started, just as if an undefined instruction were executed.

This applies, for example, when the destination is in immediate mode, or when immediate mode is specified in the addressing mode specification field that should involve address calculation.

Note that in the formats shown in FIGS. 17 to 24, Rn indicates a register specification field, and mem [
EA] indicates the memory contents of the addresses indicated by F and A, (sh) indicates the specification method in the 6-bit abbreviated addressing mode, and (Ea) indicates the specification method in the 8-bit general addressing mode. The dotted line portion in the figure indicates the expanded portion.

In this embodiment, the following basic addressing modes, register direct mode, register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC relative indirect mode, stack pop mode, stack bush mode, etc. Support each mode.

Figure 17 shows the format of register direct mode,
This is a mode in which the contents of the register are used as operands as they are, and Rn indicates the number of the general-purpose register.

Figure 18 shows the format of register indirect mode,
This is a mode in which the contents of the register are the addresses and the contents of the memory are the operands, and Rn indicates the number of the general-purpose register.

Figure 19 shows the format of the register relative indirect mode, which is divided into two types depending on whether the displacement value is 16 bits or 32 bits.
This is a mode in which the operand is the contents of the memory, which is the address to which a 6-bit or 32-bit displacement value has been added. Rn indicates the general-purpose register number, and dis
p:1B.

disp:32 indicates displacement values of 16 bits and 32 bits, respectively, and the displacement values are treated as signed.

Figure 20 shows the format of the immediate value mode, in which the bit pattern specified in the instruction code is converted into a binary number and a digit as is.
It is a mode that is used as an operand, and imm dat
a indicates an immediate value. The size of i+nm data is specified in the instruction as the operand size.

Figure 21 shows the format of the absolute mode, which is divided into 21-inch sections depending on whether the address value is expressed in 16 bits or 32 bits. This mode uses the contents of the memory as the operand, and abs:16° and abs:32 indicate 16-bit and 32-bit address values, respectively, and when an address is indicated by abs:16, the specified address value is set to 32 bits.
Sign extend to bits.

Figure 22 shows the format of PC relative indirect mode,
This mode is divided into two types depending on whether the displacement value is 16 bits or 32 bits, and the operand is the contents of the memory whose address is the value obtained by adding the 16-bit or 32-bit displacement value to the contents of the program counter. :16,disp
:32 indicates a 16-bit and 32-bit displacement value, respectively, and the displacement value is treated as signed.

Note that the value of the program counter referenced in PC relative indirect mode is the start address of the instruction that includes the operand, and when the value of the program counter is referenced in multistage indirect addressing mode, it is also the start address of the instruction that includes the operand. dress is used as the PC-relative reference value.

Figure 23 shows the format of the stack pop mode, which uses the contents of the stack pointer (sp) as the address and the contents of the memory as the operand, and after the operand is accessed, the stack pointer SP is incremented by the operand size. When handling 32-bit data, the stack pointer SP is updated by +4 after operand access. It is also possible to specify stack pop mode for overlands of size B and H, and the stack pointer SP is updated by +1 and +2, respectively. Note that a reserved instruction exception is generated for operands for which the stack pop mode has no meaning. Specifically, the write operand is a reserved instruction exception.

This is the stack pop mode specification for the read-modify-write operand.

Figure 24 shows the format of stack bush mode. In this mode, the operand is the memory content whose address is the content obtained by decrementing the content of the stack pointer (sp) by the operand size. In stack bush mode, operand access is The stack pointer (sp) is decremented before. For example, when handling 32 bit data, the stack pointer (sp) is updated by "-4" before accessing the operand.

It is also possible to specify the stack bush mode for operands of size B and H, and the stack pointer (sp) is updated by -1 and -2, respectively. In addition,
A reserved instruction exception is generated for operands for which the stack mode has no meaning. Specifically, the reserved instruction exception is the write operand, r
This is the stack bush mode specification for the ead-mod fy-wr ite operand.

(Effects of the Invention) As explained above, the present invention includes a disassembly decoding means for disassembling and decoding one instruction into one or more unit processing codes for the second pipeline stage, and decoding by this disassembly decoding means. address calculation means for executing a plurality of address operations for instructions based on each unit processing code, and a transfer for transferring the instruction address calculated by the address calculation means to a subsequent second pipeline stage as a unit processing code. For example, when processing a subroutine jump instruction, the first step code is divided into two step codes and passed through the pipeline, and the first step code executes processing related to the jump address to the subroutine. It is possible to execute processing related to the return destination address from the subroutine using step code 2, and pipeline processing can be performed efficiently without providing a latch means for holding address information as in the past.

Also, when processing a load instruction to a control register, 3
By dividing the code into three step codes and running them through the pipeline, the first step code handles processing related to source operands, the second step code handles processing related to loading into control registers, and the third step code handles processing related to the next step. Processing related to jumping to an instruction can be performed. Therefore, the start address of the next instruction of the two types of instructions can be passed through the pipeline as the operand address accompanying the step code, and a special transfer path can be eliminated for processing the program counter value of the next instruction. Pipeline processing becomes possible.

Furthermore, when pipeline processing is performed on a load instruction to a control register, after the value is loaded into the control register in the instruction execution stage, it is possible to jump to the start address of the next instruction loaded in the register, and the value is Can cancel any instruction in the pipeline that has been fetched with a control register whose value was previously loaded, and a new instruction following the instruction that loads this control register can be fetched under the control of the correct control register. It has excellent effects such as being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the configuration of a data processing device showing an embodiment of the present invention, and FIG. 2(a) is a configuration block diagram explaining the vibe line processing of the data processing device shown in FIG. , FIG. 2(b) is a schematic diagram explaining the basic instruction format, FIG. 3 is a detailed block diagram of the data processing device shown in FIG. 1, and FIG. 4(a) is a schematic diagram explaining the format of the subroutine jump instruction. Schematic diagram shown in Fig. 4(b)
, (C) is a schematic diagram explaining the bit allocation of the load instruction according to the present invention, FIG. 5 is a flowchart explaining the subroutine jump instruction processing procedure according to the present invention, and FIG. Flowchart explaining load instruction processing procedure, Fig. 7~
Fig. 6 is a schematic diagram explaining the allocated bits of the instruction format used, Figs. It is a functional block diagram explaining. In the figure, 1 is an instruction fetch unit, 2 is an instruction decode unit, 3 is a PC calculation unit, 4 is an operand address calculation unit, and 5
1 is a micro ROM section, 6 is a data calculation section, 7 is an external interface section, 8 is an address output circuit, and 9 is a data input/output circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 other people) (2 bytes) (θ ~ 4A bytes) (a) JSR Address of Figure 〉 N◆l N+2 N+3 Figure byte: N+2-1 Figure byte: N lo Figure byte : N+2-1 Figure byte: N+2-1 Byte 2 N+2 2 in N◆M-1 Figure 12 byte: N+2-1 Figure byte: N+2-1 Byte: N+2 To2◆1 2 in N+2 ・-・・・・ N battle 2 10 ◆ 2-1 Figure byte: Byte : N middle 4-1 Figure byte: N ◆ 2-1 Byte: N ◆ 2 To 2 ◆ l N ◆ 2 ◆ 2 ・・・・・・・ N middle 20th 2-1 Figure byte: Figure 2, Figure byte: Figure 2, Figure 2, Figure E: Command execution stage 1, incident display 21, title of the invention (spontaneous). ) Patent Application No. Sho 3-205584, December 2009 Data Processing Device 5, Full text of the specification to be amended and Drawing 6, Contents of the amendment (1) The entire text of the specification shall be amended as shown in the attached sheet. (2) In the drawings, FIGS. 3, 4(b), (C), 5 and 6 will be corrected as shown in the attached sheet. Above 3. Relationship with the case of the person making the amendment

Claims (1)

[Claims] a first pipeline stage for decoding instructions;
In a data processing device having a pipeline processing mechanism consisting of a plurality of second pipeline stages, which are pipeline stages subsequent to the first pipeline stage, one instruction is sent to the second pipeline stage. or decomposition decoding means for disassembling and decoding into a plurality of unit processing codes, address calculation means for executing a plurality of address operations for the instruction based on each unit processing code decoded by the decomposition decoding means, and the address operation A data processing device comprising: transfer means for transferring an instruction address calculated by the means to a subsequent second pipeline stage as the unit processing code.